base_dyn_inst.hh revision 5177
11060SN/A/* 22702Sktlim@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 31060SN/A * All rights reserved. 41060SN/A * 51060SN/A * Redistribution and use in source and binary forms, with or without 61060SN/A * modification, are permitted provided that the following conditions are 71060SN/A * met: redistributions of source code must retain the above copyright 81060SN/A * notice, this list of conditions and the following disclaimer; 91060SN/A * redistributions in binary form must reproduce the above copyright 101060SN/A * notice, this list of conditions and the following disclaimer in the 111060SN/A * documentation and/or other materials provided with the distribution; 121060SN/A * neither the name of the copyright holders nor the names of its 131060SN/A * contributors may be used to endorse or promote products derived from 141060SN/A * this software without specific prior written permission. 151060SN/A * 161060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291060SN/A */ 301060SN/A 311464SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 321464SN/A#define __CPU_BASE_DYN_INST_HH__ 331060SN/A 342731Sktlim@umich.edu#include <bitset> 352292SN/A#include <list> 361464SN/A#include <string> 371060SN/A 382669Sktlim@umich.edu#include "arch/faults.hh" 391060SN/A#include "base/fast_alloc.hh" 401060SN/A#include "base/trace.hh" 411858SN/A#include "config/full_system.hh" 423770Sgblack@eecs.umich.edu#include "cpu/o3/comm.hh" 431464SN/A#include "cpu/exetrace.hh" 441464SN/A#include "cpu/inst_seq.hh" 452669Sktlim@umich.edu#include "cpu/op_class.hh" 461060SN/A#include "cpu/static_inst.hh" 472669Sktlim@umich.edu#include "mem/packet.hh" 482292SN/A#include "sim/system.hh" 491060SN/A 501060SN/A/** 511060SN/A * @file 521060SN/A * Defines a dynamic instruction context. 531060SN/A */ 541060SN/A 551061SN/A// Forward declaration. 561061SN/Aclass StaticInstPtr; 571060SN/A 581060SN/Atemplate <class Impl> 591061SN/Aclass BaseDynInst : public FastAlloc, public RefCounted 601060SN/A{ 611060SN/A public: 621060SN/A // Typedef for the CPU. 632733Sktlim@umich.edu typedef typename Impl::CPUType ImplCPU; 642733Sktlim@umich.edu typedef typename ImplCPU::ImplState ImplState; 651060SN/A 662292SN/A // Logical register index type. 672107SN/A typedef TheISA::RegIndex RegIndex; 682690Sktlim@umich.edu // Integer register type. 692107SN/A typedef TheISA::IntReg IntReg; 702690Sktlim@umich.edu // Floating point register type. 712690Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 721060SN/A 732292SN/A // The DynInstPtr type. 742292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 752292SN/A 762292SN/A // The list of instructions iterator type. 772292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 782292SN/A 791060SN/A enum { 802292SN/A MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 812292SN/A MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 821060SN/A }; 831060SN/A 842292SN/A /** The StaticInst used by this BaseDynInst. */ 852107SN/A StaticInstPtr staticInst; 861060SN/A 871060SN/A //////////////////////////////////////////// 881060SN/A // 891060SN/A // INSTRUCTION EXECUTION 901060SN/A // 911060SN/A //////////////////////////////////////////// 922292SN/A /** InstRecord that tracks this instructions. */ 931060SN/A Trace::InstRecord *traceData; 941060SN/A 952292SN/A /** 962292SN/A * Does a read to a given address. 972292SN/A * @param addr The address to read. 982292SN/A * @param data The read's data is written into this parameter. 992292SN/A * @param flags The request's flags. 1002292SN/A * @return Returns any fault due to the read. 1012292SN/A */ 1021060SN/A template <class T> 1032132SN/A Fault read(Addr addr, T &data, unsigned flags); 1041060SN/A 1055177Sgblack@eecs.umich.edu Fault translateDataReadAddr(Addr vaddr, Addr &paddr, 1065177Sgblack@eecs.umich.edu int size, unsigned flags); 1075177Sgblack@eecs.umich.edu 1082292SN/A /** 1092292SN/A * Does a write to a given address. 1102292SN/A * @param data The data to be written. 1112292SN/A * @param addr The address to write to. 1122292SN/A * @param flags The request's flags. 1132292SN/A * @param res The result of the write (for load locked/store conditionals). 1142292SN/A * @return Returns any fault due to the write. 1152292SN/A */ 1161060SN/A template <class T> 1172132SN/A Fault write(T data, Addr addr, unsigned flags, 1181060SN/A uint64_t *res); 1191060SN/A 1205177Sgblack@eecs.umich.edu Fault translateDataWriteAddr(Addr vaddr, Addr &paddr, 1215177Sgblack@eecs.umich.edu int size, unsigned flags); 1225177Sgblack@eecs.umich.edu 1231060SN/A void prefetch(Addr addr, unsigned flags); 1241060SN/A void writeHint(Addr addr, int size, unsigned flags); 1252132SN/A Fault copySrcTranslate(Addr src); 1262132SN/A Fault copy(Addr dest); 1271060SN/A 1281684SN/A /** @todo: Consider making this private. */ 1291060SN/A public: 1301060SN/A /** The sequence number of the instruction. */ 1311060SN/A InstSeqNum seqNum; 1321060SN/A 1332731Sktlim@umich.edu enum Status { 1342731Sktlim@umich.edu IqEntry, /// Instruction is in the IQ 1352731Sktlim@umich.edu RobEntry, /// Instruction is in the ROB 1362731Sktlim@umich.edu LsqEntry, /// Instruction is in the LSQ 1372731Sktlim@umich.edu Completed, /// Instruction has completed 1382731Sktlim@umich.edu ResultReady, /// Instruction has its result 1392731Sktlim@umich.edu CanIssue, /// Instruction can issue and execute 1402731Sktlim@umich.edu Issued, /// Instruction has issued 1412731Sktlim@umich.edu Executed, /// Instruction has executed 1422731Sktlim@umich.edu CanCommit, /// Instruction can commit 1432731Sktlim@umich.edu AtCommit, /// Instruction has reached commit 1442731Sktlim@umich.edu Committed, /// Instruction has committed 1452731Sktlim@umich.edu Squashed, /// Instruction is squashed 1462731Sktlim@umich.edu SquashedInIQ, /// Instruction is squashed in the IQ 1472731Sktlim@umich.edu SquashedInLSQ, /// Instruction is squashed in the LSQ 1482731Sktlim@umich.edu SquashedInROB, /// Instruction is squashed in the ROB 1492731Sktlim@umich.edu RecoverInst, /// Is a recover instruction 1502731Sktlim@umich.edu BlockingInst, /// Is a blocking instruction 1512731Sktlim@umich.edu ThreadsyncWait, /// Is a thread synchronization instruction 1522731Sktlim@umich.edu SerializeBefore, /// Needs to serialize on 1532731Sktlim@umich.edu /// instructions ahead of it 1542731Sktlim@umich.edu SerializeAfter, /// Needs to serialize instructions behind it 1552731Sktlim@umich.edu SerializeHandled, /// Serialization has been handled 1562731Sktlim@umich.edu NumStatus 1572731Sktlim@umich.edu }; 1582292SN/A 1592731Sktlim@umich.edu /** The status of this BaseDynInst. Several bits can be set. */ 1602731Sktlim@umich.edu std::bitset<NumStatus> status; 1611060SN/A 1621060SN/A /** The thread this instruction is from. */ 1631060SN/A short threadNumber; 1641060SN/A 1651060SN/A /** data address space ID, for loads & stores. */ 1661060SN/A short asid; 1671060SN/A 1682292SN/A /** How many source registers are ready. */ 1692292SN/A unsigned readyRegs; 1702292SN/A 1712733Sktlim@umich.edu /** Pointer to the Impl's CPU object. */ 1722733Sktlim@umich.edu ImplCPU *cpu; 1731060SN/A 1742680Sktlim@umich.edu /** Pointer to the thread state. */ 1752292SN/A ImplState *thread; 1761060SN/A 1771060SN/A /** The kind of fault this instruction has generated. */ 1782132SN/A Fault fault; 1791060SN/A 1802702Sktlim@umich.edu /** Pointer to the data for the memory access. */ 1812669Sktlim@umich.edu uint8_t *memData; 1822292SN/A 1831060SN/A /** The effective virtual address (lds & stores only). */ 1841060SN/A Addr effAddr; 1851060SN/A 1864032Sktlim@umich.edu /** Is the effective virtual address valid. */ 1874032Sktlim@umich.edu bool effAddrValid; 1884032Sktlim@umich.edu 1891060SN/A /** The effective physical address. */ 1901060SN/A Addr physEffAddr; 1911060SN/A 1921060SN/A /** Effective virtual address for a copy source. */ 1931060SN/A Addr copySrcEffAddr; 1941060SN/A 1951060SN/A /** Effective physical address for a copy source. */ 1961060SN/A Addr copySrcPhysEffAddr; 1971060SN/A 1981060SN/A /** The memory request flags (from translation). */ 1991060SN/A unsigned memReqFlags; 2001060SN/A 2011464SN/A union Result { 2021464SN/A uint64_t integer; 2032356SN/A// float fp; 2041464SN/A double dbl; 2051464SN/A }; 2061060SN/A 2071464SN/A /** The result of the instruction; assumes for now that there's only one 2081464SN/A * destination register. 2091464SN/A */ 2101464SN/A Result instResult; 2111060SN/A 2123326Sktlim@umich.edu /** Records changes to result? */ 2133326Sktlim@umich.edu bool recordResult; 2143326Sktlim@umich.edu 2151060SN/A /** PC of this instruction. */ 2161060SN/A Addr PC; 2171060SN/A 2184636Sgblack@eecs.umich.edu /** Micro PC of this instruction. */ 2194636Sgblack@eecs.umich.edu Addr microPC; 2204636Sgblack@eecs.umich.edu 2213965Sgblack@eecs.umich.edu protected: 2221060SN/A /** Next non-speculative PC. It is not filled in at fetch, but rather 2231060SN/A * once the target of the branch is truly known (either decode or 2241060SN/A * execute). 2251060SN/A */ 2261060SN/A Addr nextPC; 2271060SN/A 2282935Sksewell@umich.edu /** Next non-speculative NPC. Target PC for Mips or Sparc. */ 2292935Sksewell@umich.edu Addr nextNPC; 2302935Sksewell@umich.edu 2314636Sgblack@eecs.umich.edu /** Next non-speculative micro PC. */ 2324636Sgblack@eecs.umich.edu Addr nextMicroPC; 2334636Sgblack@eecs.umich.edu 2341060SN/A /** Predicted next PC. */ 2351060SN/A Addr predPC; 2361060SN/A 2373794Sgblack@eecs.umich.edu /** Predicted next NPC. */ 2383794Sgblack@eecs.umich.edu Addr predNPC; 2393794Sgblack@eecs.umich.edu 2404636Sgblack@eecs.umich.edu /** Predicted next microPC */ 2414636Sgblack@eecs.umich.edu Addr predMicroPC; 2424636Sgblack@eecs.umich.edu 2433794Sgblack@eecs.umich.edu /** If this is a branch that was predicted taken */ 2443794Sgblack@eecs.umich.edu bool predTaken; 2453794Sgblack@eecs.umich.edu 2463965Sgblack@eecs.umich.edu public: 2473965Sgblack@eecs.umich.edu 2481060SN/A /** Count of total number of dynamic instructions. */ 2491060SN/A static int instcount; 2501060SN/A 2512292SN/A#ifdef DEBUG 2522292SN/A void dumpSNList(); 2532292SN/A#endif 2542292SN/A 2552292SN/A /** Whether or not the source register is ready. 2562292SN/A * @todo: Not sure this should be here vs the derived class. 2571060SN/A */ 2581060SN/A bool _readySrcRegIdx[MaxInstSrcRegs]; 2591060SN/A 2603770Sgblack@eecs.umich.edu protected: 2613770Sgblack@eecs.umich.edu /** Flattened register index of the destination registers of this 2623770Sgblack@eecs.umich.edu * instruction. 2633770Sgblack@eecs.umich.edu */ 2643770Sgblack@eecs.umich.edu TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 2653770Sgblack@eecs.umich.edu 2663770Sgblack@eecs.umich.edu /** Flattened register index of the source registers of this 2673770Sgblack@eecs.umich.edu * instruction. 2683770Sgblack@eecs.umich.edu */ 2693770Sgblack@eecs.umich.edu TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 2703770Sgblack@eecs.umich.edu 2713770Sgblack@eecs.umich.edu /** Physical register index of the destination registers of this 2723770Sgblack@eecs.umich.edu * instruction. 2733770Sgblack@eecs.umich.edu */ 2743770Sgblack@eecs.umich.edu PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 2753770Sgblack@eecs.umich.edu 2763770Sgblack@eecs.umich.edu /** Physical register index of the source registers of this 2773770Sgblack@eecs.umich.edu * instruction. 2783770Sgblack@eecs.umich.edu */ 2793770Sgblack@eecs.umich.edu PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 2803770Sgblack@eecs.umich.edu 2813770Sgblack@eecs.umich.edu /** Physical register index of the previous producers of the 2823770Sgblack@eecs.umich.edu * architected destinations. 2833770Sgblack@eecs.umich.edu */ 2843770Sgblack@eecs.umich.edu PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 2853770Sgblack@eecs.umich.edu 2861060SN/A public: 2873770Sgblack@eecs.umich.edu 2883770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th destination 2893770Sgblack@eecs.umich.edu * register. 2903770Sgblack@eecs.umich.edu */ 2913770Sgblack@eecs.umich.edu PhysRegIndex renamedDestRegIdx(int idx) const 2923770Sgblack@eecs.umich.edu { 2933770Sgblack@eecs.umich.edu return _destRegIdx[idx]; 2943770Sgblack@eecs.umich.edu } 2953770Sgblack@eecs.umich.edu 2963770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th source register. */ 2973770Sgblack@eecs.umich.edu PhysRegIndex renamedSrcRegIdx(int idx) const 2983770Sgblack@eecs.umich.edu { 2993770Sgblack@eecs.umich.edu return _srcRegIdx[idx]; 3003770Sgblack@eecs.umich.edu } 3013770Sgblack@eecs.umich.edu 3023770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th destination 3033770Sgblack@eecs.umich.edu * register. 3043770Sgblack@eecs.umich.edu */ 3053770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedDestRegIdx(int idx) const 3063770Sgblack@eecs.umich.edu { 3073770Sgblack@eecs.umich.edu return _flatDestRegIdx[idx]; 3083770Sgblack@eecs.umich.edu } 3093770Sgblack@eecs.umich.edu 3103770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th source register */ 3113770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedSrcRegIdx(int idx) const 3123770Sgblack@eecs.umich.edu { 3133770Sgblack@eecs.umich.edu return _flatSrcRegIdx[idx]; 3143770Sgblack@eecs.umich.edu } 3153770Sgblack@eecs.umich.edu 3163770Sgblack@eecs.umich.edu /** Returns the physical register index of the previous physical register 3173770Sgblack@eecs.umich.edu * that remapped to the same logical register index. 3183770Sgblack@eecs.umich.edu */ 3193770Sgblack@eecs.umich.edu PhysRegIndex prevDestRegIdx(int idx) const 3203770Sgblack@eecs.umich.edu { 3213770Sgblack@eecs.umich.edu return _prevDestRegIdx[idx]; 3223770Sgblack@eecs.umich.edu } 3233770Sgblack@eecs.umich.edu 3243770Sgblack@eecs.umich.edu /** Renames a destination register to a physical register. Also records 3253770Sgblack@eecs.umich.edu * the previous physical register that the logical register mapped to. 3263770Sgblack@eecs.umich.edu */ 3273770Sgblack@eecs.umich.edu void renameDestReg(int idx, 3283770Sgblack@eecs.umich.edu PhysRegIndex renamed_dest, 3293770Sgblack@eecs.umich.edu PhysRegIndex previous_rename) 3303770Sgblack@eecs.umich.edu { 3313770Sgblack@eecs.umich.edu _destRegIdx[idx] = renamed_dest; 3323770Sgblack@eecs.umich.edu _prevDestRegIdx[idx] = previous_rename; 3333770Sgblack@eecs.umich.edu } 3343770Sgblack@eecs.umich.edu 3353770Sgblack@eecs.umich.edu /** Renames a source logical register to the physical register which 3363770Sgblack@eecs.umich.edu * has/will produce that logical register's result. 3373770Sgblack@eecs.umich.edu * @todo: add in whether or not the source register is ready. 3383770Sgblack@eecs.umich.edu */ 3393770Sgblack@eecs.umich.edu void renameSrcReg(int idx, PhysRegIndex renamed_src) 3403770Sgblack@eecs.umich.edu { 3413770Sgblack@eecs.umich.edu _srcRegIdx[idx] = renamed_src; 3423770Sgblack@eecs.umich.edu } 3433770Sgblack@eecs.umich.edu 3443770Sgblack@eecs.umich.edu /** Flattens a source architectural register index into a logical index. 3453770Sgblack@eecs.umich.edu */ 3463770Sgblack@eecs.umich.edu void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 3473770Sgblack@eecs.umich.edu { 3483770Sgblack@eecs.umich.edu _flatSrcRegIdx[idx] = flattened_src; 3493770Sgblack@eecs.umich.edu } 3503770Sgblack@eecs.umich.edu 3513770Sgblack@eecs.umich.edu /** Flattens a destination architectural register index into a logical 3523770Sgblack@eecs.umich.edu * index. 3533770Sgblack@eecs.umich.edu */ 3543770Sgblack@eecs.umich.edu void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 3553770Sgblack@eecs.umich.edu { 3563770Sgblack@eecs.umich.edu _flatDestRegIdx[idx] = flattened_dest; 3573770Sgblack@eecs.umich.edu } 3584636Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. 3594636Sgblack@eecs.umich.edu * @param staticInst A StaticInstPtr to the underlying instruction. 3604636Sgblack@eecs.umich.edu * @param PC The PC of the instruction. 3614636Sgblack@eecs.umich.edu * @param pred_PC The predicted next PC. 3624636Sgblack@eecs.umich.edu * @param pred_NPC The predicted next NPC. 3634636Sgblack@eecs.umich.edu * @param seq_num The sequence number of the instruction. 3644636Sgblack@eecs.umich.edu * @param cpu Pointer to the instruction's CPU. 3654636Sgblack@eecs.umich.edu */ 3664636Sgblack@eecs.umich.edu BaseDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC, 3674636Sgblack@eecs.umich.edu Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 3684636Sgblack@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu); 3693770Sgblack@eecs.umich.edu 3702292SN/A /** BaseDynInst constructor given a binary instruction. 3712292SN/A * @param inst The binary instruction. 3722292SN/A * @param PC The PC of the instruction. 3732292SN/A * @param pred_PC The predicted next PC. 3743794Sgblack@eecs.umich.edu * @param pred_NPC The predicted next NPC. 3752292SN/A * @param seq_num The sequence number of the instruction. 3762292SN/A * @param cpu Pointer to the instruction's CPU. 3772292SN/A */ 3784636Sgblack@eecs.umich.edu BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC, 3794636Sgblack@eecs.umich.edu Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 3803770Sgblack@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu); 3811060SN/A 3822292SN/A /** BaseDynInst constructor given a StaticInst pointer. 3832292SN/A * @param _staticInst The StaticInst for this BaseDynInst. 3842292SN/A */ 3852107SN/A BaseDynInst(StaticInstPtr &_staticInst); 3861060SN/A 3871060SN/A /** BaseDynInst destructor. */ 3881060SN/A ~BaseDynInst(); 3891060SN/A 3901464SN/A private: 3911684SN/A /** Function to initialize variables in the constructors. */ 3921464SN/A void initVars(); 3931060SN/A 3941464SN/A public: 3951060SN/A /** Dumps out contents of this BaseDynInst. */ 3961060SN/A void dump(); 3971060SN/A 3981060SN/A /** Dumps out contents of this BaseDynInst into given string. */ 3991060SN/A void dump(std::string &outstring); 4001060SN/A 4013326Sktlim@umich.edu /** Read this CPU's ID. */ 4023326Sktlim@umich.edu int readCpuId() { return cpu->readCpuId(); } 4033326Sktlim@umich.edu 4041060SN/A /** Returns the fault type. */ 4052132SN/A Fault getFault() { return fault; } 4061060SN/A 4071060SN/A /** Checks whether or not this instruction has had its branch target 4081060SN/A * calculated yet. For now it is not utilized and is hacked to be 4091060SN/A * always false. 4102292SN/A * @todo: Actually use this instruction. 4111060SN/A */ 4121060SN/A bool doneTargCalc() { return false; } 4131060SN/A 4141684SN/A /** Returns the next PC. This could be the speculative next PC if it is 4151684SN/A * called prior to the actual branch target being calculated. 4161684SN/A */ 4171060SN/A Addr readNextPC() { return nextPC; } 4181060SN/A 4192935Sksewell@umich.edu /** Returns the next NPC. This could be the speculative next NPC if it is 4202935Sksewell@umich.edu * called prior to the actual branch target being calculated. 4212935Sksewell@umich.edu */ 4223965Sgblack@eecs.umich.edu Addr readNextNPC() 4233965Sgblack@eecs.umich.edu { 4243965Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 4253965Sgblack@eecs.umich.edu return nextNPC; 4263965Sgblack@eecs.umich.edu#else 4273965Sgblack@eecs.umich.edu return nextPC + sizeof(TheISA::MachInst); 4283965Sgblack@eecs.umich.edu#endif 4293965Sgblack@eecs.umich.edu } 4302935Sksewell@umich.edu 4314636Sgblack@eecs.umich.edu Addr readNextMicroPC() 4324636Sgblack@eecs.umich.edu { 4334636Sgblack@eecs.umich.edu return nextMicroPC; 4344636Sgblack@eecs.umich.edu } 4354636Sgblack@eecs.umich.edu 4361060SN/A /** Set the predicted target of this current instruction. */ 4374636Sgblack@eecs.umich.edu void setPredTarg(Addr predicted_PC, Addr predicted_NPC, 4384636Sgblack@eecs.umich.edu Addr predicted_MicroPC) 4393794Sgblack@eecs.umich.edu { 4403794Sgblack@eecs.umich.edu predPC = predicted_PC; 4413794Sgblack@eecs.umich.edu predNPC = predicted_NPC; 4424636Sgblack@eecs.umich.edu predMicroPC = predicted_MicroPC; 4433794Sgblack@eecs.umich.edu } 4441060SN/A 4453794Sgblack@eecs.umich.edu /** Returns the predicted PC immediately after the branch. */ 4463794Sgblack@eecs.umich.edu Addr readPredPC() { return predPC; } 4473794Sgblack@eecs.umich.edu 4483794Sgblack@eecs.umich.edu /** Returns the predicted PC two instructions after the branch */ 4493794Sgblack@eecs.umich.edu Addr readPredNPC() { return predNPC; } 4501060SN/A 4514636Sgblack@eecs.umich.edu /** Returns the predicted micro PC after the branch */ 4524636Sgblack@eecs.umich.edu Addr readPredMicroPC() { return predMicroPC; } 4534636Sgblack@eecs.umich.edu 4541060SN/A /** Returns whether the instruction was predicted taken or not. */ 4553794Sgblack@eecs.umich.edu bool readPredTaken() 4563794Sgblack@eecs.umich.edu { 4573794Sgblack@eecs.umich.edu return predTaken; 4583794Sgblack@eecs.umich.edu } 4593794Sgblack@eecs.umich.edu 4603794Sgblack@eecs.umich.edu void setPredTaken(bool predicted_taken) 4613794Sgblack@eecs.umich.edu { 4623794Sgblack@eecs.umich.edu predTaken = predicted_taken; 4633794Sgblack@eecs.umich.edu } 4641060SN/A 4651060SN/A /** Returns whether the instruction mispredicted. */ 4662935Sksewell@umich.edu bool mispredicted() 4673794Sgblack@eecs.umich.edu { 4683965Sgblack@eecs.umich.edu return readPredPC() != readNextPC() || 4694636Sgblack@eecs.umich.edu readPredNPC() != readNextNPC() || 4704636Sgblack@eecs.umich.edu readPredMicroPC() != readNextMicroPC(); 4713794Sgblack@eecs.umich.edu } 4723794Sgblack@eecs.umich.edu 4731060SN/A // 4741060SN/A // Instruction types. Forward checks to StaticInst object. 4751060SN/A // 4761060SN/A bool isNop() const { return staticInst->isNop(); } 4771060SN/A bool isMemRef() const { return staticInst->isMemRef(); } 4781060SN/A bool isLoad() const { return staticInst->isLoad(); } 4791060SN/A bool isStore() const { return staticInst->isStore(); } 4802336SN/A bool isStoreConditional() const 4812336SN/A { return staticInst->isStoreConditional(); } 4821060SN/A bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 4831060SN/A bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 4841060SN/A bool isCopy() const { return staticInst->isCopy(); } 4851060SN/A bool isInteger() const { return staticInst->isInteger(); } 4861060SN/A bool isFloating() const { return staticInst->isFloating(); } 4871060SN/A bool isControl() const { return staticInst->isControl(); } 4881060SN/A bool isCall() const { return staticInst->isCall(); } 4891060SN/A bool isReturn() const { return staticInst->isReturn(); } 4901060SN/A bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 4911060SN/A bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 4921060SN/A bool isCondCtrl() const { return staticInst->isCondCtrl(); } 4931060SN/A bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 4942935Sksewell@umich.edu bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 4951060SN/A bool isThreadSync() const { return staticInst->isThreadSync(); } 4961060SN/A bool isSerializing() const { return staticInst->isSerializing(); } 4972292SN/A bool isSerializeBefore() const 4982731Sktlim@umich.edu { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 4992292SN/A bool isSerializeAfter() const 5002731Sktlim@umich.edu { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 5011060SN/A bool isMemBarrier() const { return staticInst->isMemBarrier(); } 5021060SN/A bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 5031060SN/A bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 5042292SN/A bool isQuiesce() const { return staticInst->isQuiesce(); } 5052336SN/A bool isIprAccess() const { return staticInst->isIprAccess(); } 5062308SN/A bool isUnverifiable() const { return staticInst->isUnverifiable(); } 5074828Sgblack@eecs.umich.edu bool isSyscall() const { return staticInst->isSyscall(); } 5084654Sgblack@eecs.umich.edu bool isMacroop() const { return staticInst->isMacroop(); } 5094654Sgblack@eecs.umich.edu bool isMicroop() const { return staticInst->isMicroop(); } 5104636Sgblack@eecs.umich.edu bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 5114654Sgblack@eecs.umich.edu bool isLastMicroop() const { return staticInst->isLastMicroop(); } 5124654Sgblack@eecs.umich.edu bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 5134636Sgblack@eecs.umich.edu bool isMicroBranch() const { return staticInst->isMicroBranch(); } 5142292SN/A 5152292SN/A /** Temporarily sets this instruction as a serialize before instruction. */ 5162731Sktlim@umich.edu void setSerializeBefore() { status.set(SerializeBefore); } 5172292SN/A 5182292SN/A /** Clears the serializeBefore part of this instruction. */ 5192731Sktlim@umich.edu void clearSerializeBefore() { status.reset(SerializeBefore); } 5202292SN/A 5212292SN/A /** Checks if this serializeBefore is only temporarily set. */ 5222731Sktlim@umich.edu bool isTempSerializeBefore() { return status[SerializeBefore]; } 5232292SN/A 5242292SN/A /** Temporarily sets this instruction as a serialize after instruction. */ 5252731Sktlim@umich.edu void setSerializeAfter() { status.set(SerializeAfter); } 5262292SN/A 5272292SN/A /** Clears the serializeAfter part of this instruction.*/ 5282731Sktlim@umich.edu void clearSerializeAfter() { status.reset(SerializeAfter); } 5292292SN/A 5302292SN/A /** Checks if this serializeAfter is only temporarily set. */ 5312731Sktlim@umich.edu bool isTempSerializeAfter() { return status[SerializeAfter]; } 5322292SN/A 5332731Sktlim@umich.edu /** Sets the serialization part of this instruction as handled. */ 5342731Sktlim@umich.edu void setSerializeHandled() { status.set(SerializeHandled); } 5352292SN/A 5362292SN/A /** Checks if the serialization part of this instruction has been 5372292SN/A * handled. This does not apply to the temporary serializing 5382292SN/A * state; it only applies to this instruction's own permanent 5392292SN/A * serializing state. 5402292SN/A */ 5412731Sktlim@umich.edu bool isSerializeHandled() { return status[SerializeHandled]; } 5421060SN/A 5431464SN/A /** Returns the opclass of this instruction. */ 5441464SN/A OpClass opClass() const { return staticInst->opClass(); } 5451464SN/A 5461464SN/A /** Returns the branch target address. */ 5471464SN/A Addr branchTarget() const { return staticInst->branchTarget(PC); } 5481464SN/A 5492292SN/A /** Returns the number of source registers. */ 5502292SN/A int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 5511684SN/A 5522292SN/A /** Returns the number of destination registers. */ 5531060SN/A int8_t numDestRegs() const { return staticInst->numDestRegs(); } 5541060SN/A 5551060SN/A // the following are used to track physical register usage 5561060SN/A // for machines with separate int & FP reg files 5571060SN/A int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 5581060SN/A int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 5591060SN/A 5601060SN/A /** Returns the logical register index of the i'th destination register. */ 5612292SN/A RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 5621060SN/A 5631060SN/A /** Returns the logical register index of the i'th source register. */ 5642292SN/A RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 5651060SN/A 5661684SN/A /** Returns the result of an integer instruction. */ 5671464SN/A uint64_t readIntResult() { return instResult.integer; } 5681684SN/A 5691684SN/A /** Returns the result of a floating point instruction. */ 5702356SN/A float readFloatResult() { return (float)instResult.dbl; } 5711684SN/A 5721684SN/A /** Returns the result of a floating point (double) instruction. */ 5731464SN/A double readDoubleResult() { return instResult.dbl; } 5741060SN/A 5752702Sktlim@umich.edu /** Records an integer register being set to a value. */ 5763735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 5771060SN/A { 5783326Sktlim@umich.edu if (recordResult) 5793326Sktlim@umich.edu instResult.integer = val; 5801060SN/A } 5811060SN/A 5822702Sktlim@umich.edu /** Records an fp register being set to a value. */ 5833735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 5843735Sstever@eecs.umich.edu int width) 5852690Sktlim@umich.edu { 5863326Sktlim@umich.edu if (recordResult) { 5873326Sktlim@umich.edu if (width == 32) 5883326Sktlim@umich.edu instResult.dbl = (double)val; 5893326Sktlim@umich.edu else if (width == 64) 5903326Sktlim@umich.edu instResult.dbl = val; 5913326Sktlim@umich.edu else 5923326Sktlim@umich.edu panic("Unsupported width!"); 5933326Sktlim@umich.edu } 5942690Sktlim@umich.edu } 5952690Sktlim@umich.edu 5962702Sktlim@umich.edu /** Records an fp register being set to a value. */ 5973735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 5981060SN/A { 5993326Sktlim@umich.edu if (recordResult) 6003326Sktlim@umich.edu instResult.dbl = (double)val; 6012308SN/A } 6021060SN/A 6032702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 6043735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 6053735Sstever@eecs.umich.edu int width) 6062308SN/A { 6073326Sktlim@umich.edu if (recordResult) 6083326Sktlim@umich.edu instResult.integer = val; 6092308SN/A } 6101060SN/A 6112702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 6123735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 6132308SN/A { 6143326Sktlim@umich.edu if (recordResult) 6153326Sktlim@umich.edu instResult.integer = val; 6161060SN/A } 6171060SN/A 6182190SN/A /** Records that one of the source registers is ready. */ 6192292SN/A void markSrcRegReady(); 6202190SN/A 6212331SN/A /** Marks a specific register as ready. */ 6222292SN/A void markSrcRegReady(RegIndex src_idx); 6232190SN/A 6241684SN/A /** Returns if a source register is ready. */ 6251464SN/A bool isReadySrcRegIdx(int idx) const 6261464SN/A { 6271464SN/A return this->_readySrcRegIdx[idx]; 6281464SN/A } 6291464SN/A 6301684SN/A /** Sets this instruction as completed. */ 6312731Sktlim@umich.edu void setCompleted() { status.set(Completed); } 6321464SN/A 6332292SN/A /** Returns whether or not this instruction is completed. */ 6342731Sktlim@umich.edu bool isCompleted() const { return status[Completed]; } 6351464SN/A 6362731Sktlim@umich.edu /** Marks the result as ready. */ 6372731Sktlim@umich.edu void setResultReady() { status.set(ResultReady); } 6382308SN/A 6392731Sktlim@umich.edu /** Returns whether or not the result is ready. */ 6402731Sktlim@umich.edu bool isResultReady() const { return status[ResultReady]; } 6412308SN/A 6421060SN/A /** Sets this instruction as ready to issue. */ 6432731Sktlim@umich.edu void setCanIssue() { status.set(CanIssue); } 6441060SN/A 6451060SN/A /** Returns whether or not this instruction is ready to issue. */ 6462731Sktlim@umich.edu bool readyToIssue() const { return status[CanIssue]; } 6471060SN/A 6484032Sktlim@umich.edu /** Clears this instruction being able to issue. */ 6494032Sktlim@umich.edu void clearCanIssue() { status.reset(CanIssue); } 6504032Sktlim@umich.edu 6511060SN/A /** Sets this instruction as issued from the IQ. */ 6522731Sktlim@umich.edu void setIssued() { status.set(Issued); } 6531060SN/A 6541060SN/A /** Returns whether or not this instruction has issued. */ 6552731Sktlim@umich.edu bool isIssued() const { return status[Issued]; } 6561060SN/A 6574032Sktlim@umich.edu /** Clears this instruction as being issued. */ 6584032Sktlim@umich.edu void clearIssued() { status.reset(Issued); } 6594032Sktlim@umich.edu 6601060SN/A /** Sets this instruction as executed. */ 6612731Sktlim@umich.edu void setExecuted() { status.set(Executed); } 6621060SN/A 6631060SN/A /** Returns whether or not this instruction has executed. */ 6642731Sktlim@umich.edu bool isExecuted() const { return status[Executed]; } 6651060SN/A 6661060SN/A /** Sets this instruction as ready to commit. */ 6672731Sktlim@umich.edu void setCanCommit() { status.set(CanCommit); } 6681060SN/A 6691061SN/A /** Clears this instruction as being ready to commit. */ 6702731Sktlim@umich.edu void clearCanCommit() { status.reset(CanCommit); } 6711061SN/A 6721060SN/A /** Returns whether or not this instruction is ready to commit. */ 6732731Sktlim@umich.edu bool readyToCommit() const { return status[CanCommit]; } 6742731Sktlim@umich.edu 6752731Sktlim@umich.edu void setAtCommit() { status.set(AtCommit); } 6762731Sktlim@umich.edu 6772731Sktlim@umich.edu bool isAtCommit() { return status[AtCommit]; } 6781060SN/A 6792292SN/A /** Sets this instruction as committed. */ 6802731Sktlim@umich.edu void setCommitted() { status.set(Committed); } 6812292SN/A 6822292SN/A /** Returns whether or not this instruction is committed. */ 6832731Sktlim@umich.edu bool isCommitted() const { return status[Committed]; } 6842292SN/A 6851060SN/A /** Sets this instruction as squashed. */ 6862731Sktlim@umich.edu void setSquashed() { status.set(Squashed); } 6871060SN/A 6881060SN/A /** Returns whether or not this instruction is squashed. */ 6892731Sktlim@umich.edu bool isSquashed() const { return status[Squashed]; } 6901060SN/A 6912292SN/A //Instruction Queue Entry 6922292SN/A //----------------------- 6932292SN/A /** Sets this instruction as a entry the IQ. */ 6942731Sktlim@umich.edu void setInIQ() { status.set(IqEntry); } 6952292SN/A 6962292SN/A /** Sets this instruction as a entry the IQ. */ 6972731Sktlim@umich.edu void clearInIQ() { status.reset(IqEntry); } 6982731Sktlim@umich.edu 6992731Sktlim@umich.edu /** Returns whether or not this instruction has issued. */ 7002731Sktlim@umich.edu bool isInIQ() const { return status[IqEntry]; } 7012292SN/A 7021060SN/A /** Sets this instruction as squashed in the IQ. */ 7032731Sktlim@umich.edu void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 7041060SN/A 7051060SN/A /** Returns whether or not this instruction is squashed in the IQ. */ 7062731Sktlim@umich.edu bool isSquashedInIQ() const { return status[SquashedInIQ]; } 7072292SN/A 7082292SN/A 7092292SN/A //Load / Store Queue Functions 7102292SN/A //----------------------- 7112292SN/A /** Sets this instruction as a entry the LSQ. */ 7122731Sktlim@umich.edu void setInLSQ() { status.set(LsqEntry); } 7132292SN/A 7142292SN/A /** Sets this instruction as a entry the LSQ. */ 7152731Sktlim@umich.edu void removeInLSQ() { status.reset(LsqEntry); } 7162731Sktlim@umich.edu 7172731Sktlim@umich.edu /** Returns whether or not this instruction is in the LSQ. */ 7182731Sktlim@umich.edu bool isInLSQ() const { return status[LsqEntry]; } 7192292SN/A 7202292SN/A /** Sets this instruction as squashed in the LSQ. */ 7212731Sktlim@umich.edu void setSquashedInLSQ() { status.set(SquashedInLSQ);} 7222292SN/A 7232292SN/A /** Returns whether or not this instruction is squashed in the LSQ. */ 7242731Sktlim@umich.edu bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 7252292SN/A 7262292SN/A 7272292SN/A //Reorder Buffer Functions 7282292SN/A //----------------------- 7292292SN/A /** Sets this instruction as a entry the ROB. */ 7302731Sktlim@umich.edu void setInROB() { status.set(RobEntry); } 7312292SN/A 7322292SN/A /** Sets this instruction as a entry the ROB. */ 7332731Sktlim@umich.edu void clearInROB() { status.reset(RobEntry); } 7342731Sktlim@umich.edu 7352731Sktlim@umich.edu /** Returns whether or not this instruction is in the ROB. */ 7362731Sktlim@umich.edu bool isInROB() const { return status[RobEntry]; } 7372292SN/A 7382292SN/A /** Sets this instruction as squashed in the ROB. */ 7392731Sktlim@umich.edu void setSquashedInROB() { status.set(SquashedInROB); } 7402292SN/A 7412292SN/A /** Returns whether or not this instruction is squashed in the ROB. */ 7422731Sktlim@umich.edu bool isSquashedInROB() const { return status[SquashedInROB]; } 7432292SN/A 7441060SN/A /** Read the PC of this instruction. */ 7451464SN/A const Addr readPC() const { return PC; } 7461060SN/A 7474636Sgblack@eecs.umich.edu /**Read the micro PC of this instruction. */ 7484636Sgblack@eecs.umich.edu const Addr readMicroPC() const { return microPC; } 7494636Sgblack@eecs.umich.edu 7501060SN/A /** Set the next PC of this instruction (its actual target). */ 7514636Sgblack@eecs.umich.edu void setNextPC(Addr val) 7522308SN/A { 7532308SN/A nextPC = val; 7542308SN/A } 7552190SN/A 7562935Sksewell@umich.edu /** Set the next NPC of this instruction (the target in Mips or Sparc).*/ 7574636Sgblack@eecs.umich.edu void setNextNPC(Addr val) 7582935Sksewell@umich.edu { 7594632Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 7602935Sksewell@umich.edu nextNPC = val; 7614632Sgblack@eecs.umich.edu#endif 7622935Sksewell@umich.edu } 7632935Sksewell@umich.edu 7644636Sgblack@eecs.umich.edu void setNextMicroPC(Addr val) 7654636Sgblack@eecs.umich.edu { 7664636Sgblack@eecs.umich.edu nextMicroPC = val; 7674636Sgblack@eecs.umich.edu } 7684636Sgblack@eecs.umich.edu 7692702Sktlim@umich.edu /** Sets the ASID. */ 7702292SN/A void setASID(short addr_space_id) { asid = addr_space_id; } 7712292SN/A 7722702Sktlim@umich.edu /** Sets the thread id. */ 7732702Sktlim@umich.edu void setTid(unsigned tid) { threadNumber = tid; } 7742292SN/A 7752731Sktlim@umich.edu /** Sets the pointer to the thread state. */ 7762702Sktlim@umich.edu void setThreadState(ImplState *state) { thread = state; } 7771060SN/A 7782731Sktlim@umich.edu /** Returns the thread context. */ 7792680Sktlim@umich.edu ThreadContext *tcBase() { return thread->getTC(); } 7801464SN/A 7811464SN/A private: 7821684SN/A /** Instruction effective address. 7831684SN/A * @todo: Consider if this is necessary or not. 7841684SN/A */ 7851464SN/A Addr instEffAddr; 7862292SN/A 7871684SN/A /** Whether or not the effective address calculation is completed. 7881684SN/A * @todo: Consider if this is necessary or not. 7891684SN/A */ 7901464SN/A bool eaCalcDone; 7911464SN/A 7924032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 7934032Sktlim@umich.edu bool isUncacheable; 7944032Sktlim@umich.edu 7954032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 7964032Sktlim@umich.edu bool reqMade; 7974032Sktlim@umich.edu 7981464SN/A public: 7991684SN/A /** Sets the effective address. */ 8001464SN/A void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 8011684SN/A 8021684SN/A /** Returns the effective address. */ 8031464SN/A const Addr &getEA() const { return instEffAddr; } 8041684SN/A 8051684SN/A /** Returns whether or not the eff. addr. calculation has been completed. */ 8061464SN/A bool doneEACalc() { return eaCalcDone; } 8071684SN/A 8081684SN/A /** Returns whether or not the eff. addr. source registers are ready. */ 8091464SN/A bool eaSrcsReady(); 8101681SN/A 8112292SN/A /** Whether or not the memory operation is done. */ 8122292SN/A bool memOpDone; 8132292SN/A 8144032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 8154032Sktlim@umich.edu bool uncacheable() { return isUncacheable; } 8164032Sktlim@umich.edu 8174032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 8184032Sktlim@umich.edu bool hasRequest() { return reqMade; } 8194032Sktlim@umich.edu 8201681SN/A public: 8211684SN/A /** Load queue index. */ 8221681SN/A int16_t lqIdx; 8231684SN/A 8241684SN/A /** Store queue index. */ 8251681SN/A int16_t sqIdx; 8262292SN/A 8272292SN/A /** Iterator pointing to this BaseDynInst in the list of all insts. */ 8282292SN/A ListIt instListIt; 8292292SN/A 8302292SN/A /** Returns iterator to this instruction in the list of all insts. */ 8312292SN/A ListIt &getInstListIt() { return instListIt; } 8322292SN/A 8332292SN/A /** Sets iterator for this instruction in the list of all insts. */ 8342292SN/A void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 8353326Sktlim@umich.edu 8363326Sktlim@umich.edu public: 8373326Sktlim@umich.edu /** Returns the number of consecutive store conditional failures. */ 8383326Sktlim@umich.edu unsigned readStCondFailures() 8393326Sktlim@umich.edu { return thread->storeCondFailures; } 8403326Sktlim@umich.edu 8413326Sktlim@umich.edu /** Sets the number of consecutive store conditional failures. */ 8423326Sktlim@umich.edu void setStCondFailures(unsigned sc_failures) 8433326Sktlim@umich.edu { thread->storeCondFailures = sc_failures; } 8441060SN/A}; 8451060SN/A 8461060SN/Atemplate<class Impl> 8475177Sgblack@eecs.umich.eduFault 8485177Sgblack@eecs.umich.eduBaseDynInst<Impl>::translateDataReadAddr(Addr vaddr, Addr &paddr, 8495177Sgblack@eecs.umich.edu int size, unsigned flags) 8505177Sgblack@eecs.umich.edu{ 8515177Sgblack@eecs.umich.edu if (traceData) { 8525177Sgblack@eecs.umich.edu traceData->setAddr(vaddr); 8535177Sgblack@eecs.umich.edu } 8545177Sgblack@eecs.umich.edu 8555177Sgblack@eecs.umich.edu reqMade = true; 8565177Sgblack@eecs.umich.edu Request *req = new Request(); 8575177Sgblack@eecs.umich.edu req->setVirt(asid, vaddr, size, flags, PC); 8585177Sgblack@eecs.umich.edu req->setThreadContext(thread->readCpuId(), threadNumber); 8595177Sgblack@eecs.umich.edu 8605177Sgblack@eecs.umich.edu fault = cpu->translateDataReadReq(req, thread); 8615177Sgblack@eecs.umich.edu 8625177Sgblack@eecs.umich.edu if (fault == NoFault) 8635177Sgblack@eecs.umich.edu paddr = req->getPaddr(); 8645177Sgblack@eecs.umich.edu 8655177Sgblack@eecs.umich.edu delete req; 8665177Sgblack@eecs.umich.edu return fault; 8675177Sgblack@eecs.umich.edu} 8685177Sgblack@eecs.umich.edu 8695177Sgblack@eecs.umich.edutemplate<class Impl> 8701060SN/Atemplate<class T> 8712132SN/Ainline Fault 8721060SN/ABaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 8731060SN/A{ 8744032Sktlim@umich.edu reqMade = true; 8754032Sktlim@umich.edu Request *req = new Request(); 8764032Sktlim@umich.edu req->setVirt(asid, addr, sizeof(T), flags, this->PC); 8774032Sktlim@umich.edu req->setThreadContext(thread->readCpuId(), threadNumber); 8782292SN/A 8792690Sktlim@umich.edu fault = cpu->translateDataReadReq(req, thread); 8801060SN/A 8814032Sktlim@umich.edu if (req->isUncacheable()) 8824032Sktlim@umich.edu isUncacheable = true; 8834032Sktlim@umich.edu 8842678Sktlim@umich.edu if (fault == NoFault) { 8852678Sktlim@umich.edu effAddr = req->getVaddr(); 8864032Sktlim@umich.edu effAddrValid = true; 8872678Sktlim@umich.edu physEffAddr = req->getPaddr(); 8882678Sktlim@umich.edu memReqFlags = req->getFlags(); 8891060SN/A 8902690Sktlim@umich.edu#if 0 8912292SN/A if (cpu->system->memctrl->badaddr(physEffAddr)) { 8922292SN/A fault = TheISA::genMachineCheckFault(); 8932292SN/A data = (T)-1; 8942292SN/A this->setExecuted(); 8952292SN/A } else { 8962292SN/A fault = cpu->read(req, data, lqIdx); 8972292SN/A } 8982292SN/A#else 8991681SN/A fault = cpu->read(req, data, lqIdx); 9002632Sstever@eecs.umich.edu#endif 9011684SN/A } else { 9021060SN/A // Return a fixed value to keep simulation deterministic even 9031060SN/A // along misspeculated paths. 9041060SN/A data = (T)-1; 9052292SN/A 9062292SN/A // Commit will have to clean up whatever happened. Set this 9072292SN/A // instruction as executed. 9082292SN/A this->setExecuted(); 9094032Sktlim@umich.edu delete req; 9101060SN/A } 9111060SN/A 9121060SN/A if (traceData) { 9131060SN/A traceData->setAddr(addr); 9141060SN/A traceData->setData(data); 9151060SN/A } 9161060SN/A 9171060SN/A return fault; 9181060SN/A} 9191060SN/A 9201060SN/Atemplate<class Impl> 9215177Sgblack@eecs.umich.eduFault 9225177Sgblack@eecs.umich.eduBaseDynInst<Impl>::translateDataWriteAddr(Addr vaddr, Addr &paddr, 9235177Sgblack@eecs.umich.edu int size, unsigned flags) 9245177Sgblack@eecs.umich.edu{ 9255177Sgblack@eecs.umich.edu if (traceData) { 9265177Sgblack@eecs.umich.edu traceData->setAddr(vaddr); 9275177Sgblack@eecs.umich.edu } 9285177Sgblack@eecs.umich.edu 9295177Sgblack@eecs.umich.edu reqMade = true; 9305177Sgblack@eecs.umich.edu Request *req = new Request(); 9315177Sgblack@eecs.umich.edu req->setVirt(asid, vaddr, size, flags, PC); 9325177Sgblack@eecs.umich.edu req->setThreadContext(thread->readCpuId(), threadNumber); 9335177Sgblack@eecs.umich.edu 9345177Sgblack@eecs.umich.edu fault = cpu->translateDataWriteReq(req, thread); 9355177Sgblack@eecs.umich.edu 9365177Sgblack@eecs.umich.edu if (fault == NoFault) 9375177Sgblack@eecs.umich.edu paddr = req->getPaddr(); 9385177Sgblack@eecs.umich.edu 9395177Sgblack@eecs.umich.edu delete req; 9405177Sgblack@eecs.umich.edu return fault; 9415177Sgblack@eecs.umich.edu} 9425177Sgblack@eecs.umich.edu 9435177Sgblack@eecs.umich.edutemplate<class Impl> 9441060SN/Atemplate<class T> 9452132SN/Ainline Fault 9461060SN/ABaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 9471060SN/A{ 9481060SN/A if (traceData) { 9491060SN/A traceData->setAddr(addr); 9501060SN/A traceData->setData(data); 9511060SN/A } 9521060SN/A 9534032Sktlim@umich.edu reqMade = true; 9544032Sktlim@umich.edu Request *req = new Request(); 9552669Sktlim@umich.edu req->setVirt(asid, addr, sizeof(T), flags, this->PC); 9562683Sktlim@umich.edu req->setThreadContext(thread->readCpuId(), threadNumber); 9571060SN/A 9582690Sktlim@umich.edu fault = cpu->translateDataWriteReq(req, thread); 9591060SN/A 9604032Sktlim@umich.edu if (req->isUncacheable()) 9614032Sktlim@umich.edu isUncacheable = true; 9624032Sktlim@umich.edu 9632090SN/A if (fault == NoFault) { 9642678Sktlim@umich.edu effAddr = req->getVaddr(); 9654032Sktlim@umich.edu effAddrValid = true; 9662678Sktlim@umich.edu physEffAddr = req->getPaddr(); 9672678Sktlim@umich.edu memReqFlags = req->getFlags(); 9684350Sgblack@eecs.umich.edu 9694350Sgblack@eecs.umich.edu if (req->isCondSwap()) { 9704350Sgblack@eecs.umich.edu assert(res); 9714350Sgblack@eecs.umich.edu req->setExtraData(*res); 9724350Sgblack@eecs.umich.edu } 9732690Sktlim@umich.edu#if 0 9742292SN/A if (cpu->system->memctrl->badaddr(physEffAddr)) { 9752292SN/A fault = TheISA::genMachineCheckFault(); 9762292SN/A } else { 9772292SN/A fault = cpu->write(req, data, sqIdx); 9782292SN/A } 9792292SN/A#else 9801681SN/A fault = cpu->write(req, data, sqIdx); 9812632Sstever@eecs.umich.edu#endif 9824032Sktlim@umich.edu } else { 9834032Sktlim@umich.edu delete req; 9841060SN/A } 9851060SN/A 9861060SN/A return fault; 9871060SN/A} 9881060SN/A 9891464SN/A#endif // __CPU_BASE_DYN_INST_HH__ 990