base_dyn_inst.hh revision 4632
11060SN/A/* 22702Sktlim@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 31060SN/A * All rights reserved. 41060SN/A * 51060SN/A * Redistribution and use in source and binary forms, with or without 61060SN/A * modification, are permitted provided that the following conditions are 71060SN/A * met: redistributions of source code must retain the above copyright 81060SN/A * notice, this list of conditions and the following disclaimer; 91060SN/A * redistributions in binary form must reproduce the above copyright 101060SN/A * notice, this list of conditions and the following disclaimer in the 111060SN/A * documentation and/or other materials provided with the distribution; 121060SN/A * neither the name of the copyright holders nor the names of its 131060SN/A * contributors may be used to endorse or promote products derived from 141060SN/A * this software without specific prior written permission. 151060SN/A * 161060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291060SN/A */ 301060SN/A 311464SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 321464SN/A#define __CPU_BASE_DYN_INST_HH__ 331060SN/A 342731Sktlim@umich.edu#include <bitset> 352292SN/A#include <list> 361464SN/A#include <string> 371060SN/A 382669Sktlim@umich.edu#include "arch/faults.hh" 391060SN/A#include "base/fast_alloc.hh" 401060SN/A#include "base/trace.hh" 411858SN/A#include "config/full_system.hh" 423770Sgblack@eecs.umich.edu#include "cpu/o3/comm.hh" 431464SN/A#include "cpu/exetrace.hh" 441464SN/A#include "cpu/inst_seq.hh" 452669Sktlim@umich.edu#include "cpu/op_class.hh" 461060SN/A#include "cpu/static_inst.hh" 472669Sktlim@umich.edu#include "mem/packet.hh" 482292SN/A#include "sim/system.hh" 491060SN/A 501060SN/A/** 511060SN/A * @file 521060SN/A * Defines a dynamic instruction context. 531060SN/A */ 541060SN/A 551061SN/A// Forward declaration. 561061SN/Aclass StaticInstPtr; 571060SN/A 581060SN/Atemplate <class Impl> 591061SN/Aclass BaseDynInst : public FastAlloc, public RefCounted 601060SN/A{ 611060SN/A public: 621060SN/A // Typedef for the CPU. 632733Sktlim@umich.edu typedef typename Impl::CPUType ImplCPU; 642733Sktlim@umich.edu typedef typename ImplCPU::ImplState ImplState; 651060SN/A 662292SN/A // Logical register index type. 672107SN/A typedef TheISA::RegIndex RegIndex; 682690Sktlim@umich.edu // Integer register type. 692107SN/A typedef TheISA::IntReg IntReg; 702690Sktlim@umich.edu // Floating point register type. 712690Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 721060SN/A 732292SN/A // The DynInstPtr type. 742292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 752292SN/A 762292SN/A // The list of instructions iterator type. 772292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 782292SN/A 791060SN/A enum { 802292SN/A MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 812292SN/A MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 821060SN/A }; 831060SN/A 842292SN/A /** The StaticInst used by this BaseDynInst. */ 852107SN/A StaticInstPtr staticInst; 861060SN/A 871060SN/A //////////////////////////////////////////// 881060SN/A // 891060SN/A // INSTRUCTION EXECUTION 901060SN/A // 911060SN/A //////////////////////////////////////////// 922292SN/A /** InstRecord that tracks this instructions. */ 931060SN/A Trace::InstRecord *traceData; 941060SN/A 952292SN/A /** 962292SN/A * Does a read to a given address. 972292SN/A * @param addr The address to read. 982292SN/A * @param data The read's data is written into this parameter. 992292SN/A * @param flags The request's flags. 1002292SN/A * @return Returns any fault due to the read. 1012292SN/A */ 1021060SN/A template <class T> 1032132SN/A Fault read(Addr addr, T &data, unsigned flags); 1041060SN/A 1052292SN/A /** 1062292SN/A * Does a write to a given address. 1072292SN/A * @param data The data to be written. 1082292SN/A * @param addr The address to write to. 1092292SN/A * @param flags The request's flags. 1102292SN/A * @param res The result of the write (for load locked/store conditionals). 1112292SN/A * @return Returns any fault due to the write. 1122292SN/A */ 1131060SN/A template <class T> 1142132SN/A Fault write(T data, Addr addr, unsigned flags, 1151060SN/A uint64_t *res); 1161060SN/A 1171060SN/A void prefetch(Addr addr, unsigned flags); 1181060SN/A void writeHint(Addr addr, int size, unsigned flags); 1192132SN/A Fault copySrcTranslate(Addr src); 1202132SN/A Fault copy(Addr dest); 1211060SN/A 1221684SN/A /** @todo: Consider making this private. */ 1231060SN/A public: 1241060SN/A /** The sequence number of the instruction. */ 1251060SN/A InstSeqNum seqNum; 1261060SN/A 1272731Sktlim@umich.edu enum Status { 1282731Sktlim@umich.edu IqEntry, /// Instruction is in the IQ 1292731Sktlim@umich.edu RobEntry, /// Instruction is in the ROB 1302731Sktlim@umich.edu LsqEntry, /// Instruction is in the LSQ 1312731Sktlim@umich.edu Completed, /// Instruction has completed 1322731Sktlim@umich.edu ResultReady, /// Instruction has its result 1332731Sktlim@umich.edu CanIssue, /// Instruction can issue and execute 1342731Sktlim@umich.edu Issued, /// Instruction has issued 1352731Sktlim@umich.edu Executed, /// Instruction has executed 1362731Sktlim@umich.edu CanCommit, /// Instruction can commit 1372731Sktlim@umich.edu AtCommit, /// Instruction has reached commit 1382731Sktlim@umich.edu Committed, /// Instruction has committed 1392731Sktlim@umich.edu Squashed, /// Instruction is squashed 1402731Sktlim@umich.edu SquashedInIQ, /// Instruction is squashed in the IQ 1412731Sktlim@umich.edu SquashedInLSQ, /// Instruction is squashed in the LSQ 1422731Sktlim@umich.edu SquashedInROB, /// Instruction is squashed in the ROB 1432731Sktlim@umich.edu RecoverInst, /// Is a recover instruction 1442731Sktlim@umich.edu BlockingInst, /// Is a blocking instruction 1452731Sktlim@umich.edu ThreadsyncWait, /// Is a thread synchronization instruction 1462731Sktlim@umich.edu SerializeBefore, /// Needs to serialize on 1472731Sktlim@umich.edu /// instructions ahead of it 1482731Sktlim@umich.edu SerializeAfter, /// Needs to serialize instructions behind it 1492731Sktlim@umich.edu SerializeHandled, /// Serialization has been handled 1502731Sktlim@umich.edu NumStatus 1512731Sktlim@umich.edu }; 1522292SN/A 1532731Sktlim@umich.edu /** The status of this BaseDynInst. Several bits can be set. */ 1542731Sktlim@umich.edu std::bitset<NumStatus> status; 1551060SN/A 1561060SN/A /** The thread this instruction is from. */ 1571060SN/A short threadNumber; 1581060SN/A 1591060SN/A /** data address space ID, for loads & stores. */ 1601060SN/A short asid; 1611060SN/A 1622292SN/A /** How many source registers are ready. */ 1632292SN/A unsigned readyRegs; 1642292SN/A 1652733Sktlim@umich.edu /** Pointer to the Impl's CPU object. */ 1662733Sktlim@umich.edu ImplCPU *cpu; 1671060SN/A 1682680Sktlim@umich.edu /** Pointer to the thread state. */ 1692292SN/A ImplState *thread; 1701060SN/A 1711060SN/A /** The kind of fault this instruction has generated. */ 1722132SN/A Fault fault; 1731060SN/A 1742702Sktlim@umich.edu /** Pointer to the data for the memory access. */ 1752669Sktlim@umich.edu uint8_t *memData; 1762292SN/A 1771060SN/A /** The effective virtual address (lds & stores only). */ 1781060SN/A Addr effAddr; 1791060SN/A 1804032Sktlim@umich.edu /** Is the effective virtual address valid. */ 1814032Sktlim@umich.edu bool effAddrValid; 1824032Sktlim@umich.edu 1831060SN/A /** The effective physical address. */ 1841060SN/A Addr physEffAddr; 1851060SN/A 1861060SN/A /** Effective virtual address for a copy source. */ 1871060SN/A Addr copySrcEffAddr; 1881060SN/A 1891060SN/A /** Effective physical address for a copy source. */ 1901060SN/A Addr copySrcPhysEffAddr; 1911060SN/A 1921060SN/A /** The memory request flags (from translation). */ 1931060SN/A unsigned memReqFlags; 1941060SN/A 1951464SN/A union Result { 1961464SN/A uint64_t integer; 1972356SN/A// float fp; 1981464SN/A double dbl; 1991464SN/A }; 2001060SN/A 2011464SN/A /** The result of the instruction; assumes for now that there's only one 2021464SN/A * destination register. 2031464SN/A */ 2041464SN/A Result instResult; 2051060SN/A 2063326Sktlim@umich.edu /** Records changes to result? */ 2073326Sktlim@umich.edu bool recordResult; 2083326Sktlim@umich.edu 2091060SN/A /** PC of this instruction. */ 2101060SN/A Addr PC; 2111060SN/A 2123965Sgblack@eecs.umich.edu protected: 2131060SN/A /** Next non-speculative PC. It is not filled in at fetch, but rather 2141060SN/A * once the target of the branch is truly known (either decode or 2151060SN/A * execute). 2161060SN/A */ 2171060SN/A Addr nextPC; 2181060SN/A 2192935Sksewell@umich.edu /** Next non-speculative NPC. Target PC for Mips or Sparc. */ 2202935Sksewell@umich.edu Addr nextNPC; 2212935Sksewell@umich.edu 2221060SN/A /** Predicted next PC. */ 2231060SN/A Addr predPC; 2241060SN/A 2253794Sgblack@eecs.umich.edu /** Predicted next NPC. */ 2263794Sgblack@eecs.umich.edu Addr predNPC; 2273794Sgblack@eecs.umich.edu 2283794Sgblack@eecs.umich.edu /** If this is a branch that was predicted taken */ 2293794Sgblack@eecs.umich.edu bool predTaken; 2303794Sgblack@eecs.umich.edu 2313965Sgblack@eecs.umich.edu public: 2323965Sgblack@eecs.umich.edu 2331060SN/A /** Count of total number of dynamic instructions. */ 2341060SN/A static int instcount; 2351060SN/A 2362292SN/A#ifdef DEBUG 2372292SN/A void dumpSNList(); 2382292SN/A#endif 2392292SN/A 2402292SN/A /** Whether or not the source register is ready. 2412292SN/A * @todo: Not sure this should be here vs the derived class. 2421060SN/A */ 2431060SN/A bool _readySrcRegIdx[MaxInstSrcRegs]; 2441060SN/A 2453770Sgblack@eecs.umich.edu protected: 2463770Sgblack@eecs.umich.edu /** Flattened register index of the destination registers of this 2473770Sgblack@eecs.umich.edu * instruction. 2483770Sgblack@eecs.umich.edu */ 2493770Sgblack@eecs.umich.edu TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 2503770Sgblack@eecs.umich.edu 2513770Sgblack@eecs.umich.edu /** Flattened register index of the source registers of this 2523770Sgblack@eecs.umich.edu * instruction. 2533770Sgblack@eecs.umich.edu */ 2543770Sgblack@eecs.umich.edu TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 2553770Sgblack@eecs.umich.edu 2563770Sgblack@eecs.umich.edu /** Physical register index of the destination registers of this 2573770Sgblack@eecs.umich.edu * instruction. 2583770Sgblack@eecs.umich.edu */ 2593770Sgblack@eecs.umich.edu PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 2603770Sgblack@eecs.umich.edu 2613770Sgblack@eecs.umich.edu /** Physical register index of the source registers of this 2623770Sgblack@eecs.umich.edu * instruction. 2633770Sgblack@eecs.umich.edu */ 2643770Sgblack@eecs.umich.edu PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 2653770Sgblack@eecs.umich.edu 2663770Sgblack@eecs.umich.edu /** Physical register index of the previous producers of the 2673770Sgblack@eecs.umich.edu * architected destinations. 2683770Sgblack@eecs.umich.edu */ 2693770Sgblack@eecs.umich.edu PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 2703770Sgblack@eecs.umich.edu 2711060SN/A public: 2723770Sgblack@eecs.umich.edu 2733770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th destination 2743770Sgblack@eecs.umich.edu * register. 2753770Sgblack@eecs.umich.edu */ 2763770Sgblack@eecs.umich.edu PhysRegIndex renamedDestRegIdx(int idx) const 2773770Sgblack@eecs.umich.edu { 2783770Sgblack@eecs.umich.edu return _destRegIdx[idx]; 2793770Sgblack@eecs.umich.edu } 2803770Sgblack@eecs.umich.edu 2813770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th source register. */ 2823770Sgblack@eecs.umich.edu PhysRegIndex renamedSrcRegIdx(int idx) const 2833770Sgblack@eecs.umich.edu { 2843770Sgblack@eecs.umich.edu return _srcRegIdx[idx]; 2853770Sgblack@eecs.umich.edu } 2863770Sgblack@eecs.umich.edu 2873770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th destination 2883770Sgblack@eecs.umich.edu * register. 2893770Sgblack@eecs.umich.edu */ 2903770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedDestRegIdx(int idx) const 2913770Sgblack@eecs.umich.edu { 2923770Sgblack@eecs.umich.edu return _flatDestRegIdx[idx]; 2933770Sgblack@eecs.umich.edu } 2943770Sgblack@eecs.umich.edu 2953770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th source register */ 2963770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedSrcRegIdx(int idx) const 2973770Sgblack@eecs.umich.edu { 2983770Sgblack@eecs.umich.edu return _flatSrcRegIdx[idx]; 2993770Sgblack@eecs.umich.edu } 3003770Sgblack@eecs.umich.edu 3013770Sgblack@eecs.umich.edu /** Returns the physical register index of the previous physical register 3023770Sgblack@eecs.umich.edu * that remapped to the same logical register index. 3033770Sgblack@eecs.umich.edu */ 3043770Sgblack@eecs.umich.edu PhysRegIndex prevDestRegIdx(int idx) const 3053770Sgblack@eecs.umich.edu { 3063770Sgblack@eecs.umich.edu return _prevDestRegIdx[idx]; 3073770Sgblack@eecs.umich.edu } 3083770Sgblack@eecs.umich.edu 3093770Sgblack@eecs.umich.edu /** Renames a destination register to a physical register. Also records 3103770Sgblack@eecs.umich.edu * the previous physical register that the logical register mapped to. 3113770Sgblack@eecs.umich.edu */ 3123770Sgblack@eecs.umich.edu void renameDestReg(int idx, 3133770Sgblack@eecs.umich.edu PhysRegIndex renamed_dest, 3143770Sgblack@eecs.umich.edu PhysRegIndex previous_rename) 3153770Sgblack@eecs.umich.edu { 3163770Sgblack@eecs.umich.edu _destRegIdx[idx] = renamed_dest; 3173770Sgblack@eecs.umich.edu _prevDestRegIdx[idx] = previous_rename; 3183770Sgblack@eecs.umich.edu } 3193770Sgblack@eecs.umich.edu 3203770Sgblack@eecs.umich.edu /** Renames a source logical register to the physical register which 3213770Sgblack@eecs.umich.edu * has/will produce that logical register's result. 3223770Sgblack@eecs.umich.edu * @todo: add in whether or not the source register is ready. 3233770Sgblack@eecs.umich.edu */ 3243770Sgblack@eecs.umich.edu void renameSrcReg(int idx, PhysRegIndex renamed_src) 3253770Sgblack@eecs.umich.edu { 3263770Sgblack@eecs.umich.edu _srcRegIdx[idx] = renamed_src; 3273770Sgblack@eecs.umich.edu } 3283770Sgblack@eecs.umich.edu 3293770Sgblack@eecs.umich.edu /** Flattens a source architectural register index into a logical index. 3303770Sgblack@eecs.umich.edu */ 3313770Sgblack@eecs.umich.edu void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 3323770Sgblack@eecs.umich.edu { 3333770Sgblack@eecs.umich.edu _flatSrcRegIdx[idx] = flattened_src; 3343770Sgblack@eecs.umich.edu } 3353770Sgblack@eecs.umich.edu 3363770Sgblack@eecs.umich.edu /** Flattens a destination architectural register index into a logical 3373770Sgblack@eecs.umich.edu * index. 3383770Sgblack@eecs.umich.edu */ 3393770Sgblack@eecs.umich.edu void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 3403770Sgblack@eecs.umich.edu { 3413770Sgblack@eecs.umich.edu _flatDestRegIdx[idx] = flattened_dest; 3423770Sgblack@eecs.umich.edu } 3433770Sgblack@eecs.umich.edu 3442292SN/A /** BaseDynInst constructor given a binary instruction. 3452292SN/A * @param inst The binary instruction. 3462292SN/A * @param PC The PC of the instruction. 3472292SN/A * @param pred_PC The predicted next PC. 3483794Sgblack@eecs.umich.edu * @param pred_NPC The predicted next NPC. 3492292SN/A * @param seq_num The sequence number of the instruction. 3502292SN/A * @param cpu Pointer to the instruction's CPU. 3512292SN/A */ 3523801Sgblack@eecs.umich.edu BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, 3533794Sgblack@eecs.umich.edu Addr pred_PC, Addr pred_NPC, 3543770Sgblack@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu); 3551060SN/A 3562292SN/A /** BaseDynInst constructor given a StaticInst pointer. 3572292SN/A * @param _staticInst The StaticInst for this BaseDynInst. 3582292SN/A */ 3592107SN/A BaseDynInst(StaticInstPtr &_staticInst); 3601060SN/A 3611060SN/A /** BaseDynInst destructor. */ 3621060SN/A ~BaseDynInst(); 3631060SN/A 3641464SN/A private: 3651684SN/A /** Function to initialize variables in the constructors. */ 3661464SN/A void initVars(); 3671060SN/A 3681464SN/A public: 3691060SN/A /** Dumps out contents of this BaseDynInst. */ 3701060SN/A void dump(); 3711060SN/A 3721060SN/A /** Dumps out contents of this BaseDynInst into given string. */ 3731060SN/A void dump(std::string &outstring); 3741060SN/A 3753326Sktlim@umich.edu /** Read this CPU's ID. */ 3763326Sktlim@umich.edu int readCpuId() { return cpu->readCpuId(); } 3773326Sktlim@umich.edu 3781060SN/A /** Returns the fault type. */ 3792132SN/A Fault getFault() { return fault; } 3801060SN/A 3811060SN/A /** Checks whether or not this instruction has had its branch target 3821060SN/A * calculated yet. For now it is not utilized and is hacked to be 3831060SN/A * always false. 3842292SN/A * @todo: Actually use this instruction. 3851060SN/A */ 3861060SN/A bool doneTargCalc() { return false; } 3871060SN/A 3881684SN/A /** Returns the next PC. This could be the speculative next PC if it is 3891684SN/A * called prior to the actual branch target being calculated. 3901684SN/A */ 3911060SN/A Addr readNextPC() { return nextPC; } 3921060SN/A 3932935Sksewell@umich.edu /** Returns the next NPC. This could be the speculative next NPC if it is 3942935Sksewell@umich.edu * called prior to the actual branch target being calculated. 3952935Sksewell@umich.edu */ 3963965Sgblack@eecs.umich.edu Addr readNextNPC() 3973965Sgblack@eecs.umich.edu { 3983965Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 3993965Sgblack@eecs.umich.edu return nextNPC; 4003965Sgblack@eecs.umich.edu#else 4013965Sgblack@eecs.umich.edu return nextPC + sizeof(TheISA::MachInst); 4023965Sgblack@eecs.umich.edu#endif 4033965Sgblack@eecs.umich.edu } 4042935Sksewell@umich.edu 4051060SN/A /** Set the predicted target of this current instruction. */ 4063794Sgblack@eecs.umich.edu void setPredTarg(Addr predicted_PC, Addr predicted_NPC) 4073794Sgblack@eecs.umich.edu { 4083794Sgblack@eecs.umich.edu predPC = predicted_PC; 4093794Sgblack@eecs.umich.edu predNPC = predicted_NPC; 4103794Sgblack@eecs.umich.edu } 4111060SN/A 4123794Sgblack@eecs.umich.edu /** Returns the predicted PC immediately after the branch. */ 4133794Sgblack@eecs.umich.edu Addr readPredPC() { return predPC; } 4143794Sgblack@eecs.umich.edu 4153794Sgblack@eecs.umich.edu /** Returns the predicted PC two instructions after the branch */ 4163794Sgblack@eecs.umich.edu Addr readPredNPC() { return predNPC; } 4171060SN/A 4181060SN/A /** Returns whether the instruction was predicted taken or not. */ 4193794Sgblack@eecs.umich.edu bool readPredTaken() 4203794Sgblack@eecs.umich.edu { 4213794Sgblack@eecs.umich.edu return predTaken; 4223794Sgblack@eecs.umich.edu } 4233794Sgblack@eecs.umich.edu 4243794Sgblack@eecs.umich.edu void setPredTaken(bool predicted_taken) 4253794Sgblack@eecs.umich.edu { 4263794Sgblack@eecs.umich.edu predTaken = predicted_taken; 4273794Sgblack@eecs.umich.edu } 4281060SN/A 4291060SN/A /** Returns whether the instruction mispredicted. */ 4302935Sksewell@umich.edu bool mispredicted() 4313794Sgblack@eecs.umich.edu { 4323965Sgblack@eecs.umich.edu return readPredPC() != readNextPC() || 4333965Sgblack@eecs.umich.edu readPredNPC() != readNextNPC(); 4343794Sgblack@eecs.umich.edu } 4353794Sgblack@eecs.umich.edu 4361060SN/A // 4371060SN/A // Instruction types. Forward checks to StaticInst object. 4381060SN/A // 4391060SN/A bool isNop() const { return staticInst->isNop(); } 4401060SN/A bool isMemRef() const { return staticInst->isMemRef(); } 4411060SN/A bool isLoad() const { return staticInst->isLoad(); } 4421060SN/A bool isStore() const { return staticInst->isStore(); } 4432336SN/A bool isStoreConditional() const 4442336SN/A { return staticInst->isStoreConditional(); } 4451060SN/A bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 4461060SN/A bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 4471060SN/A bool isCopy() const { return staticInst->isCopy(); } 4481060SN/A bool isInteger() const { return staticInst->isInteger(); } 4491060SN/A bool isFloating() const { return staticInst->isFloating(); } 4501060SN/A bool isControl() const { return staticInst->isControl(); } 4511060SN/A bool isCall() const { return staticInst->isCall(); } 4521060SN/A bool isReturn() const { return staticInst->isReturn(); } 4531060SN/A bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 4541060SN/A bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 4551060SN/A bool isCondCtrl() const { return staticInst->isCondCtrl(); } 4561060SN/A bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 4572935Sksewell@umich.edu bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 4581060SN/A bool isThreadSync() const { return staticInst->isThreadSync(); } 4591060SN/A bool isSerializing() const { return staticInst->isSerializing(); } 4602292SN/A bool isSerializeBefore() const 4612731Sktlim@umich.edu { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 4622292SN/A bool isSerializeAfter() const 4632731Sktlim@umich.edu { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 4641060SN/A bool isMemBarrier() const { return staticInst->isMemBarrier(); } 4651060SN/A bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 4661060SN/A bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 4672292SN/A bool isQuiesce() const { return staticInst->isQuiesce(); } 4682336SN/A bool isIprAccess() const { return staticInst->isIprAccess(); } 4692308SN/A bool isUnverifiable() const { return staticInst->isUnverifiable(); } 4702292SN/A 4712292SN/A /** Temporarily sets this instruction as a serialize before instruction. */ 4722731Sktlim@umich.edu void setSerializeBefore() { status.set(SerializeBefore); } 4732292SN/A 4742292SN/A /** Clears the serializeBefore part of this instruction. */ 4752731Sktlim@umich.edu void clearSerializeBefore() { status.reset(SerializeBefore); } 4762292SN/A 4772292SN/A /** Checks if this serializeBefore is only temporarily set. */ 4782731Sktlim@umich.edu bool isTempSerializeBefore() { return status[SerializeBefore]; } 4792292SN/A 4802292SN/A /** Temporarily sets this instruction as a serialize after instruction. */ 4812731Sktlim@umich.edu void setSerializeAfter() { status.set(SerializeAfter); } 4822292SN/A 4832292SN/A /** Clears the serializeAfter part of this instruction.*/ 4842731Sktlim@umich.edu void clearSerializeAfter() { status.reset(SerializeAfter); } 4852292SN/A 4862292SN/A /** Checks if this serializeAfter is only temporarily set. */ 4872731Sktlim@umich.edu bool isTempSerializeAfter() { return status[SerializeAfter]; } 4882292SN/A 4892731Sktlim@umich.edu /** Sets the serialization part of this instruction as handled. */ 4902731Sktlim@umich.edu void setSerializeHandled() { status.set(SerializeHandled); } 4912292SN/A 4922292SN/A /** Checks if the serialization part of this instruction has been 4932292SN/A * handled. This does not apply to the temporary serializing 4942292SN/A * state; it only applies to this instruction's own permanent 4952292SN/A * serializing state. 4962292SN/A */ 4972731Sktlim@umich.edu bool isSerializeHandled() { return status[SerializeHandled]; } 4981060SN/A 4991464SN/A /** Returns the opclass of this instruction. */ 5001464SN/A OpClass opClass() const { return staticInst->opClass(); } 5011464SN/A 5021464SN/A /** Returns the branch target address. */ 5031464SN/A Addr branchTarget() const { return staticInst->branchTarget(PC); } 5041464SN/A 5052292SN/A /** Returns the number of source registers. */ 5062292SN/A int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 5071684SN/A 5082292SN/A /** Returns the number of destination registers. */ 5091060SN/A int8_t numDestRegs() const { return staticInst->numDestRegs(); } 5101060SN/A 5111060SN/A // the following are used to track physical register usage 5121060SN/A // for machines with separate int & FP reg files 5131060SN/A int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 5141060SN/A int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 5151060SN/A 5161060SN/A /** Returns the logical register index of the i'th destination register. */ 5172292SN/A RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 5181060SN/A 5191060SN/A /** Returns the logical register index of the i'th source register. */ 5202292SN/A RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 5211060SN/A 5221684SN/A /** Returns the result of an integer instruction. */ 5231464SN/A uint64_t readIntResult() { return instResult.integer; } 5241684SN/A 5251684SN/A /** Returns the result of a floating point instruction. */ 5262356SN/A float readFloatResult() { return (float)instResult.dbl; } 5271684SN/A 5281684SN/A /** Returns the result of a floating point (double) instruction. */ 5291464SN/A double readDoubleResult() { return instResult.dbl; } 5301060SN/A 5312702Sktlim@umich.edu /** Records an integer register being set to a value. */ 5323735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 5331060SN/A { 5343326Sktlim@umich.edu if (recordResult) 5353326Sktlim@umich.edu instResult.integer = val; 5361060SN/A } 5371060SN/A 5382702Sktlim@umich.edu /** Records an fp register being set to a value. */ 5393735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 5403735Sstever@eecs.umich.edu int width) 5412690Sktlim@umich.edu { 5423326Sktlim@umich.edu if (recordResult) { 5433326Sktlim@umich.edu if (width == 32) 5443326Sktlim@umich.edu instResult.dbl = (double)val; 5453326Sktlim@umich.edu else if (width == 64) 5463326Sktlim@umich.edu instResult.dbl = val; 5473326Sktlim@umich.edu else 5483326Sktlim@umich.edu panic("Unsupported width!"); 5493326Sktlim@umich.edu } 5502690Sktlim@umich.edu } 5512690Sktlim@umich.edu 5522702Sktlim@umich.edu /** Records an fp register being set to a value. */ 5533735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 5541060SN/A { 5553326Sktlim@umich.edu if (recordResult) 5563326Sktlim@umich.edu instResult.dbl = (double)val; 5572308SN/A } 5581060SN/A 5592702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 5603735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 5613735Sstever@eecs.umich.edu int width) 5622308SN/A { 5633326Sktlim@umich.edu if (recordResult) 5643326Sktlim@umich.edu instResult.integer = val; 5652308SN/A } 5661060SN/A 5672702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 5683735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 5692308SN/A { 5703326Sktlim@umich.edu if (recordResult) 5713326Sktlim@umich.edu instResult.integer = val; 5721060SN/A } 5731060SN/A 5742190SN/A /** Records that one of the source registers is ready. */ 5752292SN/A void markSrcRegReady(); 5762190SN/A 5772331SN/A /** Marks a specific register as ready. */ 5782292SN/A void markSrcRegReady(RegIndex src_idx); 5792190SN/A 5801684SN/A /** Returns if a source register is ready. */ 5811464SN/A bool isReadySrcRegIdx(int idx) const 5821464SN/A { 5831464SN/A return this->_readySrcRegIdx[idx]; 5841464SN/A } 5851464SN/A 5861684SN/A /** Sets this instruction as completed. */ 5872731Sktlim@umich.edu void setCompleted() { status.set(Completed); } 5881464SN/A 5892292SN/A /** Returns whether or not this instruction is completed. */ 5902731Sktlim@umich.edu bool isCompleted() const { return status[Completed]; } 5911464SN/A 5922731Sktlim@umich.edu /** Marks the result as ready. */ 5932731Sktlim@umich.edu void setResultReady() { status.set(ResultReady); } 5942308SN/A 5952731Sktlim@umich.edu /** Returns whether or not the result is ready. */ 5962731Sktlim@umich.edu bool isResultReady() const { return status[ResultReady]; } 5972308SN/A 5981060SN/A /** Sets this instruction as ready to issue. */ 5992731Sktlim@umich.edu void setCanIssue() { status.set(CanIssue); } 6001060SN/A 6011060SN/A /** Returns whether or not this instruction is ready to issue. */ 6022731Sktlim@umich.edu bool readyToIssue() const { return status[CanIssue]; } 6031060SN/A 6044032Sktlim@umich.edu /** Clears this instruction being able to issue. */ 6054032Sktlim@umich.edu void clearCanIssue() { status.reset(CanIssue); } 6064032Sktlim@umich.edu 6071060SN/A /** Sets this instruction as issued from the IQ. */ 6082731Sktlim@umich.edu void setIssued() { status.set(Issued); } 6091060SN/A 6101060SN/A /** Returns whether or not this instruction has issued. */ 6112731Sktlim@umich.edu bool isIssued() const { return status[Issued]; } 6121060SN/A 6134032Sktlim@umich.edu /** Clears this instruction as being issued. */ 6144032Sktlim@umich.edu void clearIssued() { status.reset(Issued); } 6154032Sktlim@umich.edu 6161060SN/A /** Sets this instruction as executed. */ 6172731Sktlim@umich.edu void setExecuted() { status.set(Executed); } 6181060SN/A 6191060SN/A /** Returns whether or not this instruction has executed. */ 6202731Sktlim@umich.edu bool isExecuted() const { return status[Executed]; } 6211060SN/A 6221060SN/A /** Sets this instruction as ready to commit. */ 6232731Sktlim@umich.edu void setCanCommit() { status.set(CanCommit); } 6241060SN/A 6251061SN/A /** Clears this instruction as being ready to commit. */ 6262731Sktlim@umich.edu void clearCanCommit() { status.reset(CanCommit); } 6271061SN/A 6281060SN/A /** Returns whether or not this instruction is ready to commit. */ 6292731Sktlim@umich.edu bool readyToCommit() const { return status[CanCommit]; } 6302731Sktlim@umich.edu 6312731Sktlim@umich.edu void setAtCommit() { status.set(AtCommit); } 6322731Sktlim@umich.edu 6332731Sktlim@umich.edu bool isAtCommit() { return status[AtCommit]; } 6341060SN/A 6352292SN/A /** Sets this instruction as committed. */ 6362731Sktlim@umich.edu void setCommitted() { status.set(Committed); } 6372292SN/A 6382292SN/A /** Returns whether or not this instruction is committed. */ 6392731Sktlim@umich.edu bool isCommitted() const { return status[Committed]; } 6402292SN/A 6411060SN/A /** Sets this instruction as squashed. */ 6422731Sktlim@umich.edu void setSquashed() { status.set(Squashed); } 6431060SN/A 6441060SN/A /** Returns whether or not this instruction is squashed. */ 6452731Sktlim@umich.edu bool isSquashed() const { return status[Squashed]; } 6461060SN/A 6472292SN/A //Instruction Queue Entry 6482292SN/A //----------------------- 6492292SN/A /** Sets this instruction as a entry the IQ. */ 6502731Sktlim@umich.edu void setInIQ() { status.set(IqEntry); } 6512292SN/A 6522292SN/A /** Sets this instruction as a entry the IQ. */ 6532731Sktlim@umich.edu void clearInIQ() { status.reset(IqEntry); } 6542731Sktlim@umich.edu 6552731Sktlim@umich.edu /** Returns whether or not this instruction has issued. */ 6562731Sktlim@umich.edu bool isInIQ() const { return status[IqEntry]; } 6572292SN/A 6581060SN/A /** Sets this instruction as squashed in the IQ. */ 6592731Sktlim@umich.edu void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 6601060SN/A 6611060SN/A /** Returns whether or not this instruction is squashed in the IQ. */ 6622731Sktlim@umich.edu bool isSquashedInIQ() const { return status[SquashedInIQ]; } 6632292SN/A 6642292SN/A 6652292SN/A //Load / Store Queue Functions 6662292SN/A //----------------------- 6672292SN/A /** Sets this instruction as a entry the LSQ. */ 6682731Sktlim@umich.edu void setInLSQ() { status.set(LsqEntry); } 6692292SN/A 6702292SN/A /** Sets this instruction as a entry the LSQ. */ 6712731Sktlim@umich.edu void removeInLSQ() { status.reset(LsqEntry); } 6722731Sktlim@umich.edu 6732731Sktlim@umich.edu /** Returns whether or not this instruction is in the LSQ. */ 6742731Sktlim@umich.edu bool isInLSQ() const { return status[LsqEntry]; } 6752292SN/A 6762292SN/A /** Sets this instruction as squashed in the LSQ. */ 6772731Sktlim@umich.edu void setSquashedInLSQ() { status.set(SquashedInLSQ);} 6782292SN/A 6792292SN/A /** Returns whether or not this instruction is squashed in the LSQ. */ 6802731Sktlim@umich.edu bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 6812292SN/A 6822292SN/A 6832292SN/A //Reorder Buffer Functions 6842292SN/A //----------------------- 6852292SN/A /** Sets this instruction as a entry the ROB. */ 6862731Sktlim@umich.edu void setInROB() { status.set(RobEntry); } 6872292SN/A 6882292SN/A /** Sets this instruction as a entry the ROB. */ 6892731Sktlim@umich.edu void clearInROB() { status.reset(RobEntry); } 6902731Sktlim@umich.edu 6912731Sktlim@umich.edu /** Returns whether or not this instruction is in the ROB. */ 6922731Sktlim@umich.edu bool isInROB() const { return status[RobEntry]; } 6932292SN/A 6942292SN/A /** Sets this instruction as squashed in the ROB. */ 6952731Sktlim@umich.edu void setSquashedInROB() { status.set(SquashedInROB); } 6962292SN/A 6972292SN/A /** Returns whether or not this instruction is squashed in the ROB. */ 6982731Sktlim@umich.edu bool isSquashedInROB() const { return status[SquashedInROB]; } 6992292SN/A 7001060SN/A /** Read the PC of this instruction. */ 7011464SN/A const Addr readPC() const { return PC; } 7021060SN/A 7031060SN/A /** Set the next PC of this instruction (its actual target). */ 7042308SN/A void setNextPC(uint64_t val) 7052308SN/A { 7062308SN/A nextPC = val; 7072308SN/A } 7082190SN/A 7092935Sksewell@umich.edu /** Set the next NPC of this instruction (the target in Mips or Sparc).*/ 7102935Sksewell@umich.edu void setNextNPC(uint64_t val) 7112935Sksewell@umich.edu { 7124632Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 7132935Sksewell@umich.edu nextNPC = val; 7144632Sgblack@eecs.umich.edu#endif 7152935Sksewell@umich.edu } 7162935Sksewell@umich.edu 7172702Sktlim@umich.edu /** Sets the ASID. */ 7182292SN/A void setASID(short addr_space_id) { asid = addr_space_id; } 7192292SN/A 7202702Sktlim@umich.edu /** Sets the thread id. */ 7212702Sktlim@umich.edu void setTid(unsigned tid) { threadNumber = tid; } 7222292SN/A 7232731Sktlim@umich.edu /** Sets the pointer to the thread state. */ 7242702Sktlim@umich.edu void setThreadState(ImplState *state) { thread = state; } 7251060SN/A 7262731Sktlim@umich.edu /** Returns the thread context. */ 7272680Sktlim@umich.edu ThreadContext *tcBase() { return thread->getTC(); } 7281464SN/A 7291464SN/A private: 7301684SN/A /** Instruction effective address. 7311684SN/A * @todo: Consider if this is necessary or not. 7321684SN/A */ 7331464SN/A Addr instEffAddr; 7342292SN/A 7351684SN/A /** Whether or not the effective address calculation is completed. 7361684SN/A * @todo: Consider if this is necessary or not. 7371684SN/A */ 7381464SN/A bool eaCalcDone; 7391464SN/A 7404032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 7414032Sktlim@umich.edu bool isUncacheable; 7424032Sktlim@umich.edu 7434032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 7444032Sktlim@umich.edu bool reqMade; 7454032Sktlim@umich.edu 7461464SN/A public: 7471684SN/A /** Sets the effective address. */ 7481464SN/A void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 7491684SN/A 7501684SN/A /** Returns the effective address. */ 7511464SN/A const Addr &getEA() const { return instEffAddr; } 7521684SN/A 7531684SN/A /** Returns whether or not the eff. addr. calculation has been completed. */ 7541464SN/A bool doneEACalc() { return eaCalcDone; } 7551684SN/A 7561684SN/A /** Returns whether or not the eff. addr. source registers are ready. */ 7571464SN/A bool eaSrcsReady(); 7581681SN/A 7592292SN/A /** Whether or not the memory operation is done. */ 7602292SN/A bool memOpDone; 7612292SN/A 7624032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 7634032Sktlim@umich.edu bool uncacheable() { return isUncacheable; } 7644032Sktlim@umich.edu 7654032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 7664032Sktlim@umich.edu bool hasRequest() { return reqMade; } 7674032Sktlim@umich.edu 7681681SN/A public: 7691684SN/A /** Load queue index. */ 7701681SN/A int16_t lqIdx; 7711684SN/A 7721684SN/A /** Store queue index. */ 7731681SN/A int16_t sqIdx; 7742292SN/A 7752292SN/A /** Iterator pointing to this BaseDynInst in the list of all insts. */ 7762292SN/A ListIt instListIt; 7772292SN/A 7782292SN/A /** Returns iterator to this instruction in the list of all insts. */ 7792292SN/A ListIt &getInstListIt() { return instListIt; } 7802292SN/A 7812292SN/A /** Sets iterator for this instruction in the list of all insts. */ 7822292SN/A void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 7833326Sktlim@umich.edu 7843326Sktlim@umich.edu public: 7853326Sktlim@umich.edu /** Returns the number of consecutive store conditional failures. */ 7863326Sktlim@umich.edu unsigned readStCondFailures() 7873326Sktlim@umich.edu { return thread->storeCondFailures; } 7883326Sktlim@umich.edu 7893326Sktlim@umich.edu /** Sets the number of consecutive store conditional failures. */ 7903326Sktlim@umich.edu void setStCondFailures(unsigned sc_failures) 7913326Sktlim@umich.edu { thread->storeCondFailures = sc_failures; } 7921060SN/A}; 7931060SN/A 7941060SN/Atemplate<class Impl> 7951060SN/Atemplate<class T> 7962132SN/Ainline Fault 7971060SN/ABaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 7981060SN/A{ 7994032Sktlim@umich.edu reqMade = true; 8004032Sktlim@umich.edu Request *req = new Request(); 8014032Sktlim@umich.edu req->setVirt(asid, addr, sizeof(T), flags, this->PC); 8024032Sktlim@umich.edu req->setThreadContext(thread->readCpuId(), threadNumber); 8032292SN/A 8042669Sktlim@umich.edu if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() > 8052292SN/A TheISA::VMPageSize) { 8064032Sktlim@umich.edu delete req; 8072292SN/A return TheISA::genAlignmentFault(); 8082292SN/A } 8091060SN/A 8102690Sktlim@umich.edu fault = cpu->translateDataReadReq(req, thread); 8111060SN/A 8124032Sktlim@umich.edu if (req->isUncacheable()) 8134032Sktlim@umich.edu isUncacheable = true; 8144032Sktlim@umich.edu 8152678Sktlim@umich.edu if (fault == NoFault) { 8162678Sktlim@umich.edu effAddr = req->getVaddr(); 8174032Sktlim@umich.edu effAddrValid = true; 8182678Sktlim@umich.edu physEffAddr = req->getPaddr(); 8192678Sktlim@umich.edu memReqFlags = req->getFlags(); 8201060SN/A 8212690Sktlim@umich.edu#if 0 8222292SN/A if (cpu->system->memctrl->badaddr(physEffAddr)) { 8232292SN/A fault = TheISA::genMachineCheckFault(); 8242292SN/A data = (T)-1; 8252292SN/A this->setExecuted(); 8262292SN/A } else { 8272292SN/A fault = cpu->read(req, data, lqIdx); 8282292SN/A } 8292292SN/A#else 8301681SN/A fault = cpu->read(req, data, lqIdx); 8312632Sstever@eecs.umich.edu#endif 8321684SN/A } else { 8331060SN/A // Return a fixed value to keep simulation deterministic even 8341060SN/A // along misspeculated paths. 8351060SN/A data = (T)-1; 8362292SN/A 8372292SN/A // Commit will have to clean up whatever happened. Set this 8382292SN/A // instruction as executed. 8392292SN/A this->setExecuted(); 8404032Sktlim@umich.edu delete req; 8411060SN/A } 8421060SN/A 8431060SN/A if (traceData) { 8441060SN/A traceData->setAddr(addr); 8451060SN/A traceData->setData(data); 8461060SN/A } 8471060SN/A 8481060SN/A return fault; 8491060SN/A} 8501060SN/A 8511060SN/Atemplate<class Impl> 8521060SN/Atemplate<class T> 8532132SN/Ainline Fault 8541060SN/ABaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 8551060SN/A{ 8561060SN/A if (traceData) { 8571060SN/A traceData->setAddr(addr); 8581060SN/A traceData->setData(data); 8591060SN/A } 8601060SN/A 8614032Sktlim@umich.edu reqMade = true; 8624032Sktlim@umich.edu Request *req = new Request(); 8632669Sktlim@umich.edu req->setVirt(asid, addr, sizeof(T), flags, this->PC); 8642683Sktlim@umich.edu req->setThreadContext(thread->readCpuId(), threadNumber); 8651060SN/A 8662669Sktlim@umich.edu if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() > 8672292SN/A TheISA::VMPageSize) { 8684032Sktlim@umich.edu delete req; 8692292SN/A return TheISA::genAlignmentFault(); 8702292SN/A } 8711060SN/A 8722690Sktlim@umich.edu fault = cpu->translateDataWriteReq(req, thread); 8731060SN/A 8744032Sktlim@umich.edu if (req->isUncacheable()) 8754032Sktlim@umich.edu isUncacheable = true; 8764032Sktlim@umich.edu 8772090SN/A if (fault == NoFault) { 8782678Sktlim@umich.edu effAddr = req->getVaddr(); 8794032Sktlim@umich.edu effAddrValid = true; 8802678Sktlim@umich.edu physEffAddr = req->getPaddr(); 8812678Sktlim@umich.edu memReqFlags = req->getFlags(); 8824350Sgblack@eecs.umich.edu 8834350Sgblack@eecs.umich.edu if (req->isCondSwap()) { 8844350Sgblack@eecs.umich.edu assert(res); 8854350Sgblack@eecs.umich.edu req->setExtraData(*res); 8864350Sgblack@eecs.umich.edu } 8872690Sktlim@umich.edu#if 0 8882292SN/A if (cpu->system->memctrl->badaddr(physEffAddr)) { 8892292SN/A fault = TheISA::genMachineCheckFault(); 8902292SN/A } else { 8912292SN/A fault = cpu->write(req, data, sqIdx); 8922292SN/A } 8932292SN/A#else 8941681SN/A fault = cpu->write(req, data, sqIdx); 8952632Sstever@eecs.umich.edu#endif 8964032Sktlim@umich.edu } else { 8974032Sktlim@umich.edu delete req; 8981060SN/A } 8991060SN/A 9001060SN/A return fault; 9011060SN/A} 9021060SN/A 9031464SN/A#endif // __CPU_BASE_DYN_INST_HH__ 904