base_dyn_inst.hh revision 3801
11060SN/A/* 22702Sktlim@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 31060SN/A * All rights reserved. 41060SN/A * 51060SN/A * Redistribution and use in source and binary forms, with or without 61060SN/A * modification, are permitted provided that the following conditions are 71060SN/A * met: redistributions of source code must retain the above copyright 81060SN/A * notice, this list of conditions and the following disclaimer; 91060SN/A * redistributions in binary form must reproduce the above copyright 101060SN/A * notice, this list of conditions and the following disclaimer in the 111060SN/A * documentation and/or other materials provided with the distribution; 121060SN/A * neither the name of the copyright holders nor the names of its 131060SN/A * contributors may be used to endorse or promote products derived from 141060SN/A * this software without specific prior written permission. 151060SN/A * 161060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291060SN/A */ 301060SN/A 311464SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 321464SN/A#define __CPU_BASE_DYN_INST_HH__ 331060SN/A 342731Sktlim@umich.edu#include <bitset> 352292SN/A#include <list> 361464SN/A#include <string> 371060SN/A 382669Sktlim@umich.edu#include "arch/faults.hh" 391060SN/A#include "base/fast_alloc.hh" 401060SN/A#include "base/trace.hh" 411858SN/A#include "config/full_system.hh" 423770Sgblack@eecs.umich.edu#include "cpu/o3/comm.hh" 431464SN/A#include "cpu/exetrace.hh" 441464SN/A#include "cpu/inst_seq.hh" 452669Sktlim@umich.edu#include "cpu/op_class.hh" 461060SN/A#include "cpu/static_inst.hh" 472669Sktlim@umich.edu#include "mem/packet.hh" 482292SN/A#include "sim/system.hh" 491060SN/A 501060SN/A/** 511060SN/A * @file 521060SN/A * Defines a dynamic instruction context. 531060SN/A */ 541060SN/A 551061SN/A// Forward declaration. 561061SN/Aclass StaticInstPtr; 571060SN/A 581060SN/Atemplate <class Impl> 591061SN/Aclass BaseDynInst : public FastAlloc, public RefCounted 601060SN/A{ 611060SN/A public: 621060SN/A // Typedef for the CPU. 632733Sktlim@umich.edu typedef typename Impl::CPUType ImplCPU; 642733Sktlim@umich.edu typedef typename ImplCPU::ImplState ImplState; 651060SN/A 662292SN/A // Logical register index type. 672107SN/A typedef TheISA::RegIndex RegIndex; 682690Sktlim@umich.edu // Integer register type. 692107SN/A typedef TheISA::IntReg IntReg; 702690Sktlim@umich.edu // Floating point register type. 712690Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 721060SN/A 732292SN/A // The DynInstPtr type. 742292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 752292SN/A 762292SN/A // The list of instructions iterator type. 772292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 782292SN/A 791060SN/A enum { 802292SN/A MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 812292SN/A MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 821060SN/A }; 831060SN/A 842292SN/A /** The StaticInst used by this BaseDynInst. */ 852107SN/A StaticInstPtr staticInst; 861060SN/A 871060SN/A //////////////////////////////////////////// 881060SN/A // 891060SN/A // INSTRUCTION EXECUTION 901060SN/A // 911060SN/A //////////////////////////////////////////// 922292SN/A /** InstRecord that tracks this instructions. */ 931060SN/A Trace::InstRecord *traceData; 941060SN/A 952292SN/A /** 962292SN/A * Does a read to a given address. 972292SN/A * @param addr The address to read. 982292SN/A * @param data The read's data is written into this parameter. 992292SN/A * @param flags The request's flags. 1002292SN/A * @return Returns any fault due to the read. 1012292SN/A */ 1021060SN/A template <class T> 1032132SN/A Fault read(Addr addr, T &data, unsigned flags); 1041060SN/A 1052292SN/A /** 1062292SN/A * Does a write to a given address. 1072292SN/A * @param data The data to be written. 1082292SN/A * @param addr The address to write to. 1092292SN/A * @param flags The request's flags. 1102292SN/A * @param res The result of the write (for load locked/store conditionals). 1112292SN/A * @return Returns any fault due to the write. 1122292SN/A */ 1131060SN/A template <class T> 1142132SN/A Fault write(T data, Addr addr, unsigned flags, 1151060SN/A uint64_t *res); 1161060SN/A 1171060SN/A void prefetch(Addr addr, unsigned flags); 1181060SN/A void writeHint(Addr addr, int size, unsigned flags); 1192132SN/A Fault copySrcTranslate(Addr src); 1202132SN/A Fault copy(Addr dest); 1211060SN/A 1221684SN/A /** @todo: Consider making this private. */ 1231060SN/A public: 1241060SN/A /** The sequence number of the instruction. */ 1251060SN/A InstSeqNum seqNum; 1261060SN/A 1272731Sktlim@umich.edu enum Status { 1282731Sktlim@umich.edu IqEntry, /// Instruction is in the IQ 1292731Sktlim@umich.edu RobEntry, /// Instruction is in the ROB 1302731Sktlim@umich.edu LsqEntry, /// Instruction is in the LSQ 1312731Sktlim@umich.edu Completed, /// Instruction has completed 1322731Sktlim@umich.edu ResultReady, /// Instruction has its result 1332731Sktlim@umich.edu CanIssue, /// Instruction can issue and execute 1342731Sktlim@umich.edu Issued, /// Instruction has issued 1352731Sktlim@umich.edu Executed, /// Instruction has executed 1362731Sktlim@umich.edu CanCommit, /// Instruction can commit 1372731Sktlim@umich.edu AtCommit, /// Instruction has reached commit 1382731Sktlim@umich.edu Committed, /// Instruction has committed 1392731Sktlim@umich.edu Squashed, /// Instruction is squashed 1402731Sktlim@umich.edu SquashedInIQ, /// Instruction is squashed in the IQ 1412731Sktlim@umich.edu SquashedInLSQ, /// Instruction is squashed in the LSQ 1422731Sktlim@umich.edu SquashedInROB, /// Instruction is squashed in the ROB 1432731Sktlim@umich.edu RecoverInst, /// Is a recover instruction 1442731Sktlim@umich.edu BlockingInst, /// Is a blocking instruction 1452731Sktlim@umich.edu ThreadsyncWait, /// Is a thread synchronization instruction 1462731Sktlim@umich.edu SerializeBefore, /// Needs to serialize on 1472731Sktlim@umich.edu /// instructions ahead of it 1482731Sktlim@umich.edu SerializeAfter, /// Needs to serialize instructions behind it 1492731Sktlim@umich.edu SerializeHandled, /// Serialization has been handled 1502731Sktlim@umich.edu NumStatus 1512731Sktlim@umich.edu }; 1522292SN/A 1532731Sktlim@umich.edu /** The status of this BaseDynInst. Several bits can be set. */ 1542731Sktlim@umich.edu std::bitset<NumStatus> status; 1551060SN/A 1561060SN/A /** The thread this instruction is from. */ 1571060SN/A short threadNumber; 1581060SN/A 1591060SN/A /** data address space ID, for loads & stores. */ 1601060SN/A short asid; 1611060SN/A 1622292SN/A /** How many source registers are ready. */ 1632292SN/A unsigned readyRegs; 1642292SN/A 1652733Sktlim@umich.edu /** Pointer to the Impl's CPU object. */ 1662733Sktlim@umich.edu ImplCPU *cpu; 1671060SN/A 1682680Sktlim@umich.edu /** Pointer to the thread state. */ 1692292SN/A ImplState *thread; 1701060SN/A 1711060SN/A /** The kind of fault this instruction has generated. */ 1722132SN/A Fault fault; 1731060SN/A 1742292SN/A /** The memory request. */ 1752669Sktlim@umich.edu Request *req; 1762669Sktlim@umich.edu 1772702Sktlim@umich.edu /** Pointer to the data for the memory access. */ 1782669Sktlim@umich.edu uint8_t *memData; 1792292SN/A 1801060SN/A /** The effective virtual address (lds & stores only). */ 1811060SN/A Addr effAddr; 1821060SN/A 1831060SN/A /** The effective physical address. */ 1841060SN/A Addr physEffAddr; 1851060SN/A 1861060SN/A /** Effective virtual address for a copy source. */ 1871060SN/A Addr copySrcEffAddr; 1881060SN/A 1891060SN/A /** Effective physical address for a copy source. */ 1901060SN/A Addr copySrcPhysEffAddr; 1911060SN/A 1921060SN/A /** The memory request flags (from translation). */ 1931060SN/A unsigned memReqFlags; 1941060SN/A 1951464SN/A union Result { 1961464SN/A uint64_t integer; 1972356SN/A// float fp; 1981464SN/A double dbl; 1991464SN/A }; 2001060SN/A 2011464SN/A /** The result of the instruction; assumes for now that there's only one 2021464SN/A * destination register. 2031464SN/A */ 2041464SN/A Result instResult; 2051060SN/A 2063326Sktlim@umich.edu /** Records changes to result? */ 2073326Sktlim@umich.edu bool recordResult; 2083326Sktlim@umich.edu 2091060SN/A /** PC of this instruction. */ 2101060SN/A Addr PC; 2111060SN/A 2121060SN/A /** Next non-speculative PC. It is not filled in at fetch, but rather 2131060SN/A * once the target of the branch is truly known (either decode or 2141060SN/A * execute). 2151060SN/A */ 2161060SN/A Addr nextPC; 2171060SN/A 2182935Sksewell@umich.edu /** Next non-speculative NPC. Target PC for Mips or Sparc. */ 2192935Sksewell@umich.edu Addr nextNPC; 2202935Sksewell@umich.edu 2211060SN/A /** Predicted next PC. */ 2221060SN/A Addr predPC; 2231060SN/A 2243794Sgblack@eecs.umich.edu /** Predicted next NPC. */ 2253794Sgblack@eecs.umich.edu Addr predNPC; 2263794Sgblack@eecs.umich.edu 2273794Sgblack@eecs.umich.edu /** If this is a branch that was predicted taken */ 2283794Sgblack@eecs.umich.edu bool predTaken; 2293794Sgblack@eecs.umich.edu 2301060SN/A /** Count of total number of dynamic instructions. */ 2311060SN/A static int instcount; 2321060SN/A 2332292SN/A#ifdef DEBUG 2342292SN/A void dumpSNList(); 2352292SN/A#endif 2362292SN/A 2372292SN/A /** Whether or not the source register is ready. 2382292SN/A * @todo: Not sure this should be here vs the derived class. 2391060SN/A */ 2401060SN/A bool _readySrcRegIdx[MaxInstSrcRegs]; 2411060SN/A 2423770Sgblack@eecs.umich.edu protected: 2433770Sgblack@eecs.umich.edu /** Flattened register index of the destination registers of this 2443770Sgblack@eecs.umich.edu * instruction. 2453770Sgblack@eecs.umich.edu */ 2463770Sgblack@eecs.umich.edu TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 2473770Sgblack@eecs.umich.edu 2483770Sgblack@eecs.umich.edu /** Flattened register index of the source registers of this 2493770Sgblack@eecs.umich.edu * instruction. 2503770Sgblack@eecs.umich.edu */ 2513770Sgblack@eecs.umich.edu TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 2523770Sgblack@eecs.umich.edu 2533770Sgblack@eecs.umich.edu /** Physical register index of the destination registers of this 2543770Sgblack@eecs.umich.edu * instruction. 2553770Sgblack@eecs.umich.edu */ 2563770Sgblack@eecs.umich.edu PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 2573770Sgblack@eecs.umich.edu 2583770Sgblack@eecs.umich.edu /** Physical register index of the source registers of this 2593770Sgblack@eecs.umich.edu * instruction. 2603770Sgblack@eecs.umich.edu */ 2613770Sgblack@eecs.umich.edu PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 2623770Sgblack@eecs.umich.edu 2633770Sgblack@eecs.umich.edu /** Physical register index of the previous producers of the 2643770Sgblack@eecs.umich.edu * architected destinations. 2653770Sgblack@eecs.umich.edu */ 2663770Sgblack@eecs.umich.edu PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 2673770Sgblack@eecs.umich.edu 2681060SN/A public: 2693770Sgblack@eecs.umich.edu 2703770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th destination 2713770Sgblack@eecs.umich.edu * register. 2723770Sgblack@eecs.umich.edu */ 2733770Sgblack@eecs.umich.edu PhysRegIndex renamedDestRegIdx(int idx) const 2743770Sgblack@eecs.umich.edu { 2753770Sgblack@eecs.umich.edu return _destRegIdx[idx]; 2763770Sgblack@eecs.umich.edu } 2773770Sgblack@eecs.umich.edu 2783770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th source register. */ 2793770Sgblack@eecs.umich.edu PhysRegIndex renamedSrcRegIdx(int idx) const 2803770Sgblack@eecs.umich.edu { 2813770Sgblack@eecs.umich.edu return _srcRegIdx[idx]; 2823770Sgblack@eecs.umich.edu } 2833770Sgblack@eecs.umich.edu 2843770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th destination 2853770Sgblack@eecs.umich.edu * register. 2863770Sgblack@eecs.umich.edu */ 2873770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedDestRegIdx(int idx) const 2883770Sgblack@eecs.umich.edu { 2893770Sgblack@eecs.umich.edu return _flatDestRegIdx[idx]; 2903770Sgblack@eecs.umich.edu } 2913770Sgblack@eecs.umich.edu 2923770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th source register */ 2933770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedSrcRegIdx(int idx) const 2943770Sgblack@eecs.umich.edu { 2953770Sgblack@eecs.umich.edu return _flatSrcRegIdx[idx]; 2963770Sgblack@eecs.umich.edu } 2973770Sgblack@eecs.umich.edu 2983770Sgblack@eecs.umich.edu /** Returns the physical register index of the previous physical register 2993770Sgblack@eecs.umich.edu * that remapped to the same logical register index. 3003770Sgblack@eecs.umich.edu */ 3013770Sgblack@eecs.umich.edu PhysRegIndex prevDestRegIdx(int idx) const 3023770Sgblack@eecs.umich.edu { 3033770Sgblack@eecs.umich.edu return _prevDestRegIdx[idx]; 3043770Sgblack@eecs.umich.edu } 3053770Sgblack@eecs.umich.edu 3063770Sgblack@eecs.umich.edu /** Renames a destination register to a physical register. Also records 3073770Sgblack@eecs.umich.edu * the previous physical register that the logical register mapped to. 3083770Sgblack@eecs.umich.edu */ 3093770Sgblack@eecs.umich.edu void renameDestReg(int idx, 3103770Sgblack@eecs.umich.edu PhysRegIndex renamed_dest, 3113770Sgblack@eecs.umich.edu PhysRegIndex previous_rename) 3123770Sgblack@eecs.umich.edu { 3133770Sgblack@eecs.umich.edu _destRegIdx[idx] = renamed_dest; 3143770Sgblack@eecs.umich.edu _prevDestRegIdx[idx] = previous_rename; 3153770Sgblack@eecs.umich.edu } 3163770Sgblack@eecs.umich.edu 3173770Sgblack@eecs.umich.edu /** Renames a source logical register to the physical register which 3183770Sgblack@eecs.umich.edu * has/will produce that logical register's result. 3193770Sgblack@eecs.umich.edu * @todo: add in whether or not the source register is ready. 3203770Sgblack@eecs.umich.edu */ 3213770Sgblack@eecs.umich.edu void renameSrcReg(int idx, PhysRegIndex renamed_src) 3223770Sgblack@eecs.umich.edu { 3233770Sgblack@eecs.umich.edu _srcRegIdx[idx] = renamed_src; 3243770Sgblack@eecs.umich.edu } 3253770Sgblack@eecs.umich.edu 3263770Sgblack@eecs.umich.edu /** Flattens a source architectural register index into a logical index. 3273770Sgblack@eecs.umich.edu */ 3283770Sgblack@eecs.umich.edu void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 3293770Sgblack@eecs.umich.edu { 3303770Sgblack@eecs.umich.edu _flatSrcRegIdx[idx] = flattened_src; 3313770Sgblack@eecs.umich.edu } 3323770Sgblack@eecs.umich.edu 3333770Sgblack@eecs.umich.edu /** Flattens a destination architectural register index into a logical 3343770Sgblack@eecs.umich.edu * index. 3353770Sgblack@eecs.umich.edu */ 3363770Sgblack@eecs.umich.edu void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 3373770Sgblack@eecs.umich.edu { 3383770Sgblack@eecs.umich.edu _flatDestRegIdx[idx] = flattened_dest; 3393770Sgblack@eecs.umich.edu } 3403770Sgblack@eecs.umich.edu 3412292SN/A /** BaseDynInst constructor given a binary instruction. 3422292SN/A * @param inst The binary instruction. 3432292SN/A * @param PC The PC of the instruction. 3442292SN/A * @param pred_PC The predicted next PC. 3453794Sgblack@eecs.umich.edu * @param pred_NPC The predicted next NPC. 3462292SN/A * @param seq_num The sequence number of the instruction. 3472292SN/A * @param cpu Pointer to the instruction's CPU. 3482292SN/A */ 3493801Sgblack@eecs.umich.edu BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, 3503794Sgblack@eecs.umich.edu Addr pred_PC, Addr pred_NPC, 3513770Sgblack@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu); 3521060SN/A 3532292SN/A /** BaseDynInst constructor given a StaticInst pointer. 3542292SN/A * @param _staticInst The StaticInst for this BaseDynInst. 3552292SN/A */ 3562107SN/A BaseDynInst(StaticInstPtr &_staticInst); 3571060SN/A 3581060SN/A /** BaseDynInst destructor. */ 3591060SN/A ~BaseDynInst(); 3601060SN/A 3611464SN/A private: 3621684SN/A /** Function to initialize variables in the constructors. */ 3631464SN/A void initVars(); 3641060SN/A 3651464SN/A public: 3661060SN/A /** Dumps out contents of this BaseDynInst. */ 3671060SN/A void dump(); 3681060SN/A 3691060SN/A /** Dumps out contents of this BaseDynInst into given string. */ 3701060SN/A void dump(std::string &outstring); 3711060SN/A 3723326Sktlim@umich.edu /** Read this CPU's ID. */ 3733326Sktlim@umich.edu int readCpuId() { return cpu->readCpuId(); } 3743326Sktlim@umich.edu 3751060SN/A /** Returns the fault type. */ 3762132SN/A Fault getFault() { return fault; } 3771060SN/A 3781060SN/A /** Checks whether or not this instruction has had its branch target 3791060SN/A * calculated yet. For now it is not utilized and is hacked to be 3801060SN/A * always false. 3812292SN/A * @todo: Actually use this instruction. 3821060SN/A */ 3831060SN/A bool doneTargCalc() { return false; } 3841060SN/A 3851684SN/A /** Returns the next PC. This could be the speculative next PC if it is 3861684SN/A * called prior to the actual branch target being calculated. 3871684SN/A */ 3881060SN/A Addr readNextPC() { return nextPC; } 3891060SN/A 3902935Sksewell@umich.edu /** Returns the next NPC. This could be the speculative next NPC if it is 3912935Sksewell@umich.edu * called prior to the actual branch target being calculated. 3922935Sksewell@umich.edu */ 3932935Sksewell@umich.edu Addr readNextNPC() { return nextNPC; } 3942935Sksewell@umich.edu 3951060SN/A /** Set the predicted target of this current instruction. */ 3963794Sgblack@eecs.umich.edu void setPredTarg(Addr predicted_PC, Addr predicted_NPC) 3973794Sgblack@eecs.umich.edu { 3983794Sgblack@eecs.umich.edu predPC = predicted_PC; 3993794Sgblack@eecs.umich.edu predNPC = predicted_NPC; 4003794Sgblack@eecs.umich.edu } 4011060SN/A 4023794Sgblack@eecs.umich.edu /** Returns the predicted PC immediately after the branch. */ 4033794Sgblack@eecs.umich.edu Addr readPredPC() { return predPC; } 4043794Sgblack@eecs.umich.edu 4053794Sgblack@eecs.umich.edu /** Returns the predicted PC two instructions after the branch */ 4063794Sgblack@eecs.umich.edu Addr readPredNPC() { return predNPC; } 4071060SN/A 4081060SN/A /** Returns whether the instruction was predicted taken or not. */ 4093794Sgblack@eecs.umich.edu bool readPredTaken() 4103794Sgblack@eecs.umich.edu { 4113794Sgblack@eecs.umich.edu return predTaken; 4123794Sgblack@eecs.umich.edu } 4133794Sgblack@eecs.umich.edu 4143794Sgblack@eecs.umich.edu void setPredTaken(bool predicted_taken) 4153794Sgblack@eecs.umich.edu { 4163794Sgblack@eecs.umich.edu predTaken = predicted_taken; 4173794Sgblack@eecs.umich.edu } 4181060SN/A 4191060SN/A /** Returns whether the instruction mispredicted. */ 4202935Sksewell@umich.edu bool mispredicted() 4213794Sgblack@eecs.umich.edu { 4223794Sgblack@eecs.umich.edu return predPC != nextPC || predNPC != nextNPC; 4233794Sgblack@eecs.umich.edu } 4243794Sgblack@eecs.umich.edu 4251060SN/A // 4261060SN/A // Instruction types. Forward checks to StaticInst object. 4271060SN/A // 4281060SN/A bool isNop() const { return staticInst->isNop(); } 4291060SN/A bool isMemRef() const { return staticInst->isMemRef(); } 4301060SN/A bool isLoad() const { return staticInst->isLoad(); } 4311060SN/A bool isStore() const { return staticInst->isStore(); } 4322336SN/A bool isStoreConditional() const 4332336SN/A { return staticInst->isStoreConditional(); } 4341060SN/A bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 4351060SN/A bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 4361060SN/A bool isCopy() const { return staticInst->isCopy(); } 4371060SN/A bool isInteger() const { return staticInst->isInteger(); } 4381060SN/A bool isFloating() const { return staticInst->isFloating(); } 4391060SN/A bool isControl() const { return staticInst->isControl(); } 4401060SN/A bool isCall() const { return staticInst->isCall(); } 4411060SN/A bool isReturn() const { return staticInst->isReturn(); } 4421060SN/A bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 4431060SN/A bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 4441060SN/A bool isCondCtrl() const { return staticInst->isCondCtrl(); } 4451060SN/A bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 4462935Sksewell@umich.edu bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 4471060SN/A bool isThreadSync() const { return staticInst->isThreadSync(); } 4481060SN/A bool isSerializing() const { return staticInst->isSerializing(); } 4492292SN/A bool isSerializeBefore() const 4502731Sktlim@umich.edu { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 4512292SN/A bool isSerializeAfter() const 4522731Sktlim@umich.edu { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 4531060SN/A bool isMemBarrier() const { return staticInst->isMemBarrier(); } 4541060SN/A bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 4551060SN/A bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 4562292SN/A bool isQuiesce() const { return staticInst->isQuiesce(); } 4572336SN/A bool isIprAccess() const { return staticInst->isIprAccess(); } 4582308SN/A bool isUnverifiable() const { return staticInst->isUnverifiable(); } 4592292SN/A 4602292SN/A /** Temporarily sets this instruction as a serialize before instruction. */ 4612731Sktlim@umich.edu void setSerializeBefore() { status.set(SerializeBefore); } 4622292SN/A 4632292SN/A /** Clears the serializeBefore part of this instruction. */ 4642731Sktlim@umich.edu void clearSerializeBefore() { status.reset(SerializeBefore); } 4652292SN/A 4662292SN/A /** Checks if this serializeBefore is only temporarily set. */ 4672731Sktlim@umich.edu bool isTempSerializeBefore() { return status[SerializeBefore]; } 4682292SN/A 4692292SN/A /** Temporarily sets this instruction as a serialize after instruction. */ 4702731Sktlim@umich.edu void setSerializeAfter() { status.set(SerializeAfter); } 4712292SN/A 4722292SN/A /** Clears the serializeAfter part of this instruction.*/ 4732731Sktlim@umich.edu void clearSerializeAfter() { status.reset(SerializeAfter); } 4742292SN/A 4752292SN/A /** Checks if this serializeAfter is only temporarily set. */ 4762731Sktlim@umich.edu bool isTempSerializeAfter() { return status[SerializeAfter]; } 4772292SN/A 4782731Sktlim@umich.edu /** Sets the serialization part of this instruction as handled. */ 4792731Sktlim@umich.edu void setSerializeHandled() { status.set(SerializeHandled); } 4802292SN/A 4812292SN/A /** Checks if the serialization part of this instruction has been 4822292SN/A * handled. This does not apply to the temporary serializing 4832292SN/A * state; it only applies to this instruction's own permanent 4842292SN/A * serializing state. 4852292SN/A */ 4862731Sktlim@umich.edu bool isSerializeHandled() { return status[SerializeHandled]; } 4871060SN/A 4881464SN/A /** Returns the opclass of this instruction. */ 4891464SN/A OpClass opClass() const { return staticInst->opClass(); } 4901464SN/A 4911464SN/A /** Returns the branch target address. */ 4921464SN/A Addr branchTarget() const { return staticInst->branchTarget(PC); } 4931464SN/A 4942292SN/A /** Returns the number of source registers. */ 4952292SN/A int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 4961684SN/A 4972292SN/A /** Returns the number of destination registers. */ 4981060SN/A int8_t numDestRegs() const { return staticInst->numDestRegs(); } 4991060SN/A 5001060SN/A // the following are used to track physical register usage 5011060SN/A // for machines with separate int & FP reg files 5021060SN/A int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 5031060SN/A int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 5041060SN/A 5051060SN/A /** Returns the logical register index of the i'th destination register. */ 5062292SN/A RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 5071060SN/A 5081060SN/A /** Returns the logical register index of the i'th source register. */ 5092292SN/A RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 5101060SN/A 5111684SN/A /** Returns the result of an integer instruction. */ 5121464SN/A uint64_t readIntResult() { return instResult.integer; } 5131684SN/A 5141684SN/A /** Returns the result of a floating point instruction. */ 5152356SN/A float readFloatResult() { return (float)instResult.dbl; } 5161684SN/A 5171684SN/A /** Returns the result of a floating point (double) instruction. */ 5181464SN/A double readDoubleResult() { return instResult.dbl; } 5191060SN/A 5202702Sktlim@umich.edu /** Records an integer register being set to a value. */ 5213735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 5221060SN/A { 5233326Sktlim@umich.edu if (recordResult) 5243326Sktlim@umich.edu instResult.integer = val; 5251060SN/A } 5261060SN/A 5272702Sktlim@umich.edu /** Records an fp register being set to a value. */ 5283735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 5293735Sstever@eecs.umich.edu int width) 5302690Sktlim@umich.edu { 5313326Sktlim@umich.edu if (recordResult) { 5323326Sktlim@umich.edu if (width == 32) 5333326Sktlim@umich.edu instResult.dbl = (double)val; 5343326Sktlim@umich.edu else if (width == 64) 5353326Sktlim@umich.edu instResult.dbl = val; 5363326Sktlim@umich.edu else 5373326Sktlim@umich.edu panic("Unsupported width!"); 5383326Sktlim@umich.edu } 5392690Sktlim@umich.edu } 5402690Sktlim@umich.edu 5412702Sktlim@umich.edu /** Records an fp register being set to a value. */ 5423735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 5431060SN/A { 5443326Sktlim@umich.edu if (recordResult) 5453326Sktlim@umich.edu instResult.dbl = (double)val; 5462308SN/A } 5471060SN/A 5482702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 5493735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 5503735Sstever@eecs.umich.edu int width) 5512308SN/A { 5523326Sktlim@umich.edu if (recordResult) 5533326Sktlim@umich.edu instResult.integer = val; 5542308SN/A } 5551060SN/A 5562702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 5573735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 5582308SN/A { 5593326Sktlim@umich.edu if (recordResult) 5603326Sktlim@umich.edu instResult.integer = val; 5611060SN/A } 5621060SN/A 5632190SN/A /** Records that one of the source registers is ready. */ 5642292SN/A void markSrcRegReady(); 5652190SN/A 5662331SN/A /** Marks a specific register as ready. */ 5672292SN/A void markSrcRegReady(RegIndex src_idx); 5682190SN/A 5691684SN/A /** Returns if a source register is ready. */ 5701464SN/A bool isReadySrcRegIdx(int idx) const 5711464SN/A { 5721464SN/A return this->_readySrcRegIdx[idx]; 5731464SN/A } 5741464SN/A 5751684SN/A /** Sets this instruction as completed. */ 5762731Sktlim@umich.edu void setCompleted() { status.set(Completed); } 5771464SN/A 5782292SN/A /** Returns whether or not this instruction is completed. */ 5792731Sktlim@umich.edu bool isCompleted() const { return status[Completed]; } 5801464SN/A 5812731Sktlim@umich.edu /** Marks the result as ready. */ 5822731Sktlim@umich.edu void setResultReady() { status.set(ResultReady); } 5832308SN/A 5842731Sktlim@umich.edu /** Returns whether or not the result is ready. */ 5852731Sktlim@umich.edu bool isResultReady() const { return status[ResultReady]; } 5862308SN/A 5871060SN/A /** Sets this instruction as ready to issue. */ 5882731Sktlim@umich.edu void setCanIssue() { status.set(CanIssue); } 5891060SN/A 5901060SN/A /** Returns whether or not this instruction is ready to issue. */ 5912731Sktlim@umich.edu bool readyToIssue() const { return status[CanIssue]; } 5921060SN/A 5931060SN/A /** Sets this instruction as issued from the IQ. */ 5942731Sktlim@umich.edu void setIssued() { status.set(Issued); } 5951060SN/A 5961060SN/A /** Returns whether or not this instruction has issued. */ 5972731Sktlim@umich.edu bool isIssued() const { return status[Issued]; } 5981060SN/A 5991060SN/A /** Sets this instruction as executed. */ 6002731Sktlim@umich.edu void setExecuted() { status.set(Executed); } 6011060SN/A 6021060SN/A /** Returns whether or not this instruction has executed. */ 6032731Sktlim@umich.edu bool isExecuted() const { return status[Executed]; } 6041060SN/A 6051060SN/A /** Sets this instruction as ready to commit. */ 6062731Sktlim@umich.edu void setCanCommit() { status.set(CanCommit); } 6071060SN/A 6081061SN/A /** Clears this instruction as being ready to commit. */ 6092731Sktlim@umich.edu void clearCanCommit() { status.reset(CanCommit); } 6101061SN/A 6111060SN/A /** Returns whether or not this instruction is ready to commit. */ 6122731Sktlim@umich.edu bool readyToCommit() const { return status[CanCommit]; } 6132731Sktlim@umich.edu 6142731Sktlim@umich.edu void setAtCommit() { status.set(AtCommit); } 6152731Sktlim@umich.edu 6162731Sktlim@umich.edu bool isAtCommit() { return status[AtCommit]; } 6171060SN/A 6182292SN/A /** Sets this instruction as committed. */ 6192731Sktlim@umich.edu void setCommitted() { status.set(Committed); } 6202292SN/A 6212292SN/A /** Returns whether or not this instruction is committed. */ 6222731Sktlim@umich.edu bool isCommitted() const { return status[Committed]; } 6232292SN/A 6241060SN/A /** Sets this instruction as squashed. */ 6252731Sktlim@umich.edu void setSquashed() { status.set(Squashed); } 6261060SN/A 6271060SN/A /** Returns whether or not this instruction is squashed. */ 6282731Sktlim@umich.edu bool isSquashed() const { return status[Squashed]; } 6291060SN/A 6302292SN/A //Instruction Queue Entry 6312292SN/A //----------------------- 6322292SN/A /** Sets this instruction as a entry the IQ. */ 6332731Sktlim@umich.edu void setInIQ() { status.set(IqEntry); } 6342292SN/A 6352292SN/A /** Sets this instruction as a entry the IQ. */ 6362731Sktlim@umich.edu void clearInIQ() { status.reset(IqEntry); } 6372731Sktlim@umich.edu 6382731Sktlim@umich.edu /** Returns whether or not this instruction has issued. */ 6392731Sktlim@umich.edu bool isInIQ() const { return status[IqEntry]; } 6402292SN/A 6411060SN/A /** Sets this instruction as squashed in the IQ. */ 6422731Sktlim@umich.edu void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 6431060SN/A 6441060SN/A /** Returns whether or not this instruction is squashed in the IQ. */ 6452731Sktlim@umich.edu bool isSquashedInIQ() const { return status[SquashedInIQ]; } 6462292SN/A 6472292SN/A 6482292SN/A //Load / Store Queue Functions 6492292SN/A //----------------------- 6502292SN/A /** Sets this instruction as a entry the LSQ. */ 6512731Sktlim@umich.edu void setInLSQ() { status.set(LsqEntry); } 6522292SN/A 6532292SN/A /** Sets this instruction as a entry the LSQ. */ 6542731Sktlim@umich.edu void removeInLSQ() { status.reset(LsqEntry); } 6552731Sktlim@umich.edu 6562731Sktlim@umich.edu /** Returns whether or not this instruction is in the LSQ. */ 6572731Sktlim@umich.edu bool isInLSQ() const { return status[LsqEntry]; } 6582292SN/A 6592292SN/A /** Sets this instruction as squashed in the LSQ. */ 6602731Sktlim@umich.edu void setSquashedInLSQ() { status.set(SquashedInLSQ);} 6612292SN/A 6622292SN/A /** Returns whether or not this instruction is squashed in the LSQ. */ 6632731Sktlim@umich.edu bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 6642292SN/A 6652292SN/A 6662292SN/A //Reorder Buffer Functions 6672292SN/A //----------------------- 6682292SN/A /** Sets this instruction as a entry the ROB. */ 6692731Sktlim@umich.edu void setInROB() { status.set(RobEntry); } 6702292SN/A 6712292SN/A /** Sets this instruction as a entry the ROB. */ 6722731Sktlim@umich.edu void clearInROB() { status.reset(RobEntry); } 6732731Sktlim@umich.edu 6742731Sktlim@umich.edu /** Returns whether or not this instruction is in the ROB. */ 6752731Sktlim@umich.edu bool isInROB() const { return status[RobEntry]; } 6762292SN/A 6772292SN/A /** Sets this instruction as squashed in the ROB. */ 6782731Sktlim@umich.edu void setSquashedInROB() { status.set(SquashedInROB); } 6792292SN/A 6802292SN/A /** Returns whether or not this instruction is squashed in the ROB. */ 6812731Sktlim@umich.edu bool isSquashedInROB() const { return status[SquashedInROB]; } 6822292SN/A 6831060SN/A /** Read the PC of this instruction. */ 6841464SN/A const Addr readPC() const { return PC; } 6851060SN/A 6861060SN/A /** Set the next PC of this instruction (its actual target). */ 6872308SN/A void setNextPC(uint64_t val) 6882308SN/A { 6892308SN/A nextPC = val; 6902308SN/A } 6912190SN/A 6922935Sksewell@umich.edu /** Set the next NPC of this instruction (the target in Mips or Sparc).*/ 6932935Sksewell@umich.edu void setNextNPC(uint64_t val) 6942935Sksewell@umich.edu { 6952935Sksewell@umich.edu nextNPC = val; 6962935Sksewell@umich.edu } 6972935Sksewell@umich.edu 6982702Sktlim@umich.edu /** Sets the ASID. */ 6992292SN/A void setASID(short addr_space_id) { asid = addr_space_id; } 7002292SN/A 7012702Sktlim@umich.edu /** Sets the thread id. */ 7022702Sktlim@umich.edu void setTid(unsigned tid) { threadNumber = tid; } 7032292SN/A 7042731Sktlim@umich.edu /** Sets the pointer to the thread state. */ 7052702Sktlim@umich.edu void setThreadState(ImplState *state) { thread = state; } 7061060SN/A 7072731Sktlim@umich.edu /** Returns the thread context. */ 7082680Sktlim@umich.edu ThreadContext *tcBase() { return thread->getTC(); } 7091464SN/A 7101464SN/A private: 7111684SN/A /** Instruction effective address. 7121684SN/A * @todo: Consider if this is necessary or not. 7131684SN/A */ 7141464SN/A Addr instEffAddr; 7152292SN/A 7161684SN/A /** Whether or not the effective address calculation is completed. 7171684SN/A * @todo: Consider if this is necessary or not. 7181684SN/A */ 7191464SN/A bool eaCalcDone; 7201464SN/A 7211464SN/A public: 7221684SN/A /** Sets the effective address. */ 7231464SN/A void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 7241684SN/A 7251684SN/A /** Returns the effective address. */ 7261464SN/A const Addr &getEA() const { return instEffAddr; } 7271684SN/A 7281684SN/A /** Returns whether or not the eff. addr. calculation has been completed. */ 7291464SN/A bool doneEACalc() { return eaCalcDone; } 7301684SN/A 7311684SN/A /** Returns whether or not the eff. addr. source registers are ready. */ 7321464SN/A bool eaSrcsReady(); 7331681SN/A 7342292SN/A /** Whether or not the memory operation is done. */ 7352292SN/A bool memOpDone; 7362292SN/A 7371681SN/A public: 7381684SN/A /** Load queue index. */ 7391681SN/A int16_t lqIdx; 7401684SN/A 7411684SN/A /** Store queue index. */ 7421681SN/A int16_t sqIdx; 7432292SN/A 7442292SN/A /** Iterator pointing to this BaseDynInst in the list of all insts. */ 7452292SN/A ListIt instListIt; 7462292SN/A 7472292SN/A /** Returns iterator to this instruction in the list of all insts. */ 7482292SN/A ListIt &getInstListIt() { return instListIt; } 7492292SN/A 7502292SN/A /** Sets iterator for this instruction in the list of all insts. */ 7512292SN/A void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 7523326Sktlim@umich.edu 7533326Sktlim@umich.edu public: 7543326Sktlim@umich.edu /** Returns the number of consecutive store conditional failures. */ 7553326Sktlim@umich.edu unsigned readStCondFailures() 7563326Sktlim@umich.edu { return thread->storeCondFailures; } 7573326Sktlim@umich.edu 7583326Sktlim@umich.edu /** Sets the number of consecutive store conditional failures. */ 7593326Sktlim@umich.edu void setStCondFailures(unsigned sc_failures) 7603326Sktlim@umich.edu { thread->storeCondFailures = sc_failures; } 7611060SN/A}; 7621060SN/A 7631060SN/Atemplate<class Impl> 7641060SN/Atemplate<class T> 7652132SN/Ainline Fault 7661060SN/ABaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 7671060SN/A{ 7682695Sktlim@umich.edu // Sometimes reads will get retried, so they may come through here 7692695Sktlim@umich.edu // twice. 7702695Sktlim@umich.edu if (!req) { 7712695Sktlim@umich.edu req = new Request(); 7722695Sktlim@umich.edu req->setVirt(asid, addr, sizeof(T), flags, this->PC); 7732695Sktlim@umich.edu req->setThreadContext(thread->readCpuId(), threadNumber); 7742695Sktlim@umich.edu } else { 7752695Sktlim@umich.edu assert(addr == req->getVaddr()); 7762292SN/A } 7772292SN/A 7782669Sktlim@umich.edu if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() > 7792292SN/A TheISA::VMPageSize) { 7802292SN/A return TheISA::genAlignmentFault(); 7812292SN/A } 7821060SN/A 7832690Sktlim@umich.edu fault = cpu->translateDataReadReq(req, thread); 7841060SN/A 7852678Sktlim@umich.edu if (fault == NoFault) { 7862678Sktlim@umich.edu effAddr = req->getVaddr(); 7872678Sktlim@umich.edu physEffAddr = req->getPaddr(); 7882678Sktlim@umich.edu memReqFlags = req->getFlags(); 7891060SN/A 7902690Sktlim@umich.edu#if 0 7912292SN/A if (cpu->system->memctrl->badaddr(physEffAddr)) { 7922292SN/A fault = TheISA::genMachineCheckFault(); 7932292SN/A data = (T)-1; 7942292SN/A this->setExecuted(); 7952292SN/A } else { 7962292SN/A fault = cpu->read(req, data, lqIdx); 7972292SN/A } 7982292SN/A#else 7991681SN/A fault = cpu->read(req, data, lqIdx); 8002632Sstever@eecs.umich.edu#endif 8011684SN/A } else { 8021060SN/A // Return a fixed value to keep simulation deterministic even 8031060SN/A // along misspeculated paths. 8041060SN/A data = (T)-1; 8052292SN/A 8062292SN/A // Commit will have to clean up whatever happened. Set this 8072292SN/A // instruction as executed. 8082292SN/A this->setExecuted(); 8091060SN/A } 8101060SN/A 8111060SN/A if (traceData) { 8121060SN/A traceData->setAddr(addr); 8131060SN/A traceData->setData(data); 8141060SN/A } 8151060SN/A 8161060SN/A return fault; 8171060SN/A} 8181060SN/A 8191060SN/Atemplate<class Impl> 8201060SN/Atemplate<class T> 8212132SN/Ainline Fault 8221060SN/ABaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 8231060SN/A{ 8241060SN/A if (traceData) { 8251060SN/A traceData->setAddr(addr); 8261060SN/A traceData->setData(data); 8271060SN/A } 8281060SN/A 8292695Sktlim@umich.edu assert(req == NULL); 8302695Sktlim@umich.edu 8312669Sktlim@umich.edu req = new Request(); 8322669Sktlim@umich.edu req->setVirt(asid, addr, sizeof(T), flags, this->PC); 8332683Sktlim@umich.edu req->setThreadContext(thread->readCpuId(), threadNumber); 8341060SN/A 8352669Sktlim@umich.edu if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() > 8362292SN/A TheISA::VMPageSize) { 8372292SN/A return TheISA::genAlignmentFault(); 8382292SN/A } 8391060SN/A 8402690Sktlim@umich.edu fault = cpu->translateDataWriteReq(req, thread); 8411060SN/A 8422090SN/A if (fault == NoFault) { 8432678Sktlim@umich.edu effAddr = req->getVaddr(); 8442678Sktlim@umich.edu physEffAddr = req->getPaddr(); 8452678Sktlim@umich.edu memReqFlags = req->getFlags(); 8462690Sktlim@umich.edu#if 0 8472292SN/A if (cpu->system->memctrl->badaddr(physEffAddr)) { 8482292SN/A fault = TheISA::genMachineCheckFault(); 8492292SN/A } else { 8502292SN/A fault = cpu->write(req, data, sqIdx); 8512292SN/A } 8522292SN/A#else 8531681SN/A fault = cpu->write(req, data, sqIdx); 8542632Sstever@eecs.umich.edu#endif 8551060SN/A } 8561060SN/A 8571060SN/A if (res) { 8581060SN/A // always return some result to keep misspeculated paths 8591060SN/A // (which will ignore faults) deterministic 8602669Sktlim@umich.edu *res = (fault == NoFault) ? req->getScResult() : 0; 8611060SN/A } 8621060SN/A 8631060SN/A return fault; 8641060SN/A} 8651060SN/A 8661464SN/A#endif // __CPU_BASE_DYN_INST_HH__ 867