base_dyn_inst.hh revision 3735
11060SN/A/* 22702Sktlim@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 31060SN/A * All rights reserved. 41060SN/A * 51060SN/A * Redistribution and use in source and binary forms, with or without 61060SN/A * modification, are permitted provided that the following conditions are 71060SN/A * met: redistributions of source code must retain the above copyright 81060SN/A * notice, this list of conditions and the following disclaimer; 91060SN/A * redistributions in binary form must reproduce the above copyright 101060SN/A * notice, this list of conditions and the following disclaimer in the 111060SN/A * documentation and/or other materials provided with the distribution; 121060SN/A * neither the name of the copyright holders nor the names of its 131060SN/A * contributors may be used to endorse or promote products derived from 141060SN/A * this software without specific prior written permission. 151060SN/A * 161060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291060SN/A */ 301060SN/A 311464SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 321464SN/A#define __CPU_BASE_DYN_INST_HH__ 331060SN/A 342731Sktlim@umich.edu#include <bitset> 352292SN/A#include <list> 361464SN/A#include <string> 371060SN/A 382669Sktlim@umich.edu#include "arch/faults.hh" 391060SN/A#include "base/fast_alloc.hh" 401060SN/A#include "base/trace.hh" 411858SN/A#include "config/full_system.hh" 421464SN/A#include "cpu/exetrace.hh" 431464SN/A#include "cpu/inst_seq.hh" 442669Sktlim@umich.edu#include "cpu/op_class.hh" 451060SN/A#include "cpu/static_inst.hh" 462669Sktlim@umich.edu#include "mem/packet.hh" 472292SN/A#include "sim/system.hh" 481060SN/A 491060SN/A/** 501060SN/A * @file 511060SN/A * Defines a dynamic instruction context. 521060SN/A */ 531060SN/A 541061SN/A// Forward declaration. 551061SN/Aclass StaticInstPtr; 561060SN/A 571060SN/Atemplate <class Impl> 581061SN/Aclass BaseDynInst : public FastAlloc, public RefCounted 591060SN/A{ 601060SN/A public: 611060SN/A // Typedef for the CPU. 622733Sktlim@umich.edu typedef typename Impl::CPUType ImplCPU; 632733Sktlim@umich.edu typedef typename ImplCPU::ImplState ImplState; 641060SN/A 652292SN/A // Binary machine instruction type. 662107SN/A typedef TheISA::MachInst MachInst; 672292SN/A // Extended machine instruction type 682292SN/A typedef TheISA::ExtMachInst ExtMachInst; 692292SN/A // Logical register index type. 702107SN/A typedef TheISA::RegIndex RegIndex; 712690Sktlim@umich.edu // Integer register type. 722107SN/A typedef TheISA::IntReg IntReg; 732690Sktlim@umich.edu // Floating point register type. 742690Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 751060SN/A 762292SN/A // The DynInstPtr type. 772292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 782292SN/A 792292SN/A // The list of instructions iterator type. 802292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 812292SN/A 821060SN/A enum { 832292SN/A MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 842292SN/A MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 851060SN/A }; 861060SN/A 872292SN/A /** The StaticInst used by this BaseDynInst. */ 882107SN/A StaticInstPtr staticInst; 891060SN/A 901060SN/A //////////////////////////////////////////// 911060SN/A // 921060SN/A // INSTRUCTION EXECUTION 931060SN/A // 941060SN/A //////////////////////////////////////////// 952292SN/A /** InstRecord that tracks this instructions. */ 961060SN/A Trace::InstRecord *traceData; 971060SN/A 982292SN/A /** 992292SN/A * Does a read to a given address. 1002292SN/A * @param addr The address to read. 1012292SN/A * @param data The read's data is written into this parameter. 1022292SN/A * @param flags The request's flags. 1032292SN/A * @return Returns any fault due to the read. 1042292SN/A */ 1051060SN/A template <class T> 1062132SN/A Fault read(Addr addr, T &data, unsigned flags); 1071060SN/A 1082292SN/A /** 1092292SN/A * Does a write to a given address. 1102292SN/A * @param data The data to be written. 1112292SN/A * @param addr The address to write to. 1122292SN/A * @param flags The request's flags. 1132292SN/A * @param res The result of the write (for load locked/store conditionals). 1142292SN/A * @return Returns any fault due to the write. 1152292SN/A */ 1161060SN/A template <class T> 1172132SN/A Fault write(T data, Addr addr, unsigned flags, 1181060SN/A uint64_t *res); 1191060SN/A 1201060SN/A void prefetch(Addr addr, unsigned flags); 1211060SN/A void writeHint(Addr addr, int size, unsigned flags); 1222132SN/A Fault copySrcTranslate(Addr src); 1232132SN/A Fault copy(Addr dest); 1241060SN/A 1251684SN/A /** @todo: Consider making this private. */ 1261060SN/A public: 1271060SN/A /** The sequence number of the instruction. */ 1281060SN/A InstSeqNum seqNum; 1291060SN/A 1302731Sktlim@umich.edu enum Status { 1312731Sktlim@umich.edu IqEntry, /// Instruction is in the IQ 1322731Sktlim@umich.edu RobEntry, /// Instruction is in the ROB 1332731Sktlim@umich.edu LsqEntry, /// Instruction is in the LSQ 1342731Sktlim@umich.edu Completed, /// Instruction has completed 1352731Sktlim@umich.edu ResultReady, /// Instruction has its result 1362731Sktlim@umich.edu CanIssue, /// Instruction can issue and execute 1372731Sktlim@umich.edu Issued, /// Instruction has issued 1382731Sktlim@umich.edu Executed, /// Instruction has executed 1392731Sktlim@umich.edu CanCommit, /// Instruction can commit 1402731Sktlim@umich.edu AtCommit, /// Instruction has reached commit 1412731Sktlim@umich.edu Committed, /// Instruction has committed 1422731Sktlim@umich.edu Squashed, /// Instruction is squashed 1432731Sktlim@umich.edu SquashedInIQ, /// Instruction is squashed in the IQ 1442731Sktlim@umich.edu SquashedInLSQ, /// Instruction is squashed in the LSQ 1452731Sktlim@umich.edu SquashedInROB, /// Instruction is squashed in the ROB 1462731Sktlim@umich.edu RecoverInst, /// Is a recover instruction 1472731Sktlim@umich.edu BlockingInst, /// Is a blocking instruction 1482731Sktlim@umich.edu ThreadsyncWait, /// Is a thread synchronization instruction 1492731Sktlim@umich.edu SerializeBefore, /// Needs to serialize on 1502731Sktlim@umich.edu /// instructions ahead of it 1512731Sktlim@umich.edu SerializeAfter, /// Needs to serialize instructions behind it 1522731Sktlim@umich.edu SerializeHandled, /// Serialization has been handled 1532731Sktlim@umich.edu NumStatus 1542731Sktlim@umich.edu }; 1552292SN/A 1562731Sktlim@umich.edu /** The status of this BaseDynInst. Several bits can be set. */ 1572731Sktlim@umich.edu std::bitset<NumStatus> status; 1581060SN/A 1591060SN/A /** The thread this instruction is from. */ 1601060SN/A short threadNumber; 1611060SN/A 1621060SN/A /** data address space ID, for loads & stores. */ 1631060SN/A short asid; 1641060SN/A 1652292SN/A /** How many source registers are ready. */ 1662292SN/A unsigned readyRegs; 1672292SN/A 1682733Sktlim@umich.edu /** Pointer to the Impl's CPU object. */ 1692733Sktlim@umich.edu ImplCPU *cpu; 1701060SN/A 1712680Sktlim@umich.edu /** Pointer to the thread state. */ 1722292SN/A ImplState *thread; 1731060SN/A 1741060SN/A /** The kind of fault this instruction has generated. */ 1752132SN/A Fault fault; 1761060SN/A 1772292SN/A /** The memory request. */ 1782669Sktlim@umich.edu Request *req; 1792669Sktlim@umich.edu 1802702Sktlim@umich.edu /** Pointer to the data for the memory access. */ 1812669Sktlim@umich.edu uint8_t *memData; 1822292SN/A 1831060SN/A /** The effective virtual address (lds & stores only). */ 1841060SN/A Addr effAddr; 1851060SN/A 1861060SN/A /** The effective physical address. */ 1871060SN/A Addr physEffAddr; 1881060SN/A 1891060SN/A /** Effective virtual address for a copy source. */ 1901060SN/A Addr copySrcEffAddr; 1911060SN/A 1921060SN/A /** Effective physical address for a copy source. */ 1931060SN/A Addr copySrcPhysEffAddr; 1941060SN/A 1951060SN/A /** The memory request flags (from translation). */ 1961060SN/A unsigned memReqFlags; 1971060SN/A 1981464SN/A union Result { 1991464SN/A uint64_t integer; 2002356SN/A// float fp; 2011464SN/A double dbl; 2021464SN/A }; 2031060SN/A 2041464SN/A /** The result of the instruction; assumes for now that there's only one 2051464SN/A * destination register. 2061464SN/A */ 2071464SN/A Result instResult; 2081060SN/A 2093326Sktlim@umich.edu /** Records changes to result? */ 2103326Sktlim@umich.edu bool recordResult; 2113326Sktlim@umich.edu 2121060SN/A /** PC of this instruction. */ 2131060SN/A Addr PC; 2141060SN/A 2151060SN/A /** Next non-speculative PC. It is not filled in at fetch, but rather 2161060SN/A * once the target of the branch is truly known (either decode or 2171060SN/A * execute). 2181060SN/A */ 2191060SN/A Addr nextPC; 2201060SN/A 2212935Sksewell@umich.edu /** Next non-speculative NPC. Target PC for Mips or Sparc. */ 2222935Sksewell@umich.edu Addr nextNPC; 2232935Sksewell@umich.edu 2241060SN/A /** Predicted next PC. */ 2251060SN/A Addr predPC; 2261060SN/A 2271060SN/A /** Count of total number of dynamic instructions. */ 2281060SN/A static int instcount; 2291060SN/A 2302292SN/A#ifdef DEBUG 2312292SN/A void dumpSNList(); 2322292SN/A#endif 2332292SN/A 2342292SN/A /** Whether or not the source register is ready. 2352292SN/A * @todo: Not sure this should be here vs the derived class. 2361060SN/A */ 2371060SN/A bool _readySrcRegIdx[MaxInstSrcRegs]; 2381060SN/A 2391060SN/A public: 2402292SN/A /** BaseDynInst constructor given a binary instruction. 2412292SN/A * @param inst The binary instruction. 2422292SN/A * @param PC The PC of the instruction. 2432292SN/A * @param pred_PC The predicted next PC. 2442292SN/A * @param seq_num The sequence number of the instruction. 2452292SN/A * @param cpu Pointer to the instruction's CPU. 2462292SN/A */ 2472292SN/A BaseDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num, 2482733Sktlim@umich.edu ImplCPU *cpu); 2491060SN/A 2502292SN/A /** BaseDynInst constructor given a StaticInst pointer. 2512292SN/A * @param _staticInst The StaticInst for this BaseDynInst. 2522292SN/A */ 2532107SN/A BaseDynInst(StaticInstPtr &_staticInst); 2541060SN/A 2551060SN/A /** BaseDynInst destructor. */ 2561060SN/A ~BaseDynInst(); 2571060SN/A 2581464SN/A private: 2591684SN/A /** Function to initialize variables in the constructors. */ 2601464SN/A void initVars(); 2611060SN/A 2621464SN/A public: 2631060SN/A /** Dumps out contents of this BaseDynInst. */ 2641060SN/A void dump(); 2651060SN/A 2661060SN/A /** Dumps out contents of this BaseDynInst into given string. */ 2671060SN/A void dump(std::string &outstring); 2681060SN/A 2693326Sktlim@umich.edu /** Read this CPU's ID. */ 2703326Sktlim@umich.edu int readCpuId() { return cpu->readCpuId(); } 2713326Sktlim@umich.edu 2721060SN/A /** Returns the fault type. */ 2732132SN/A Fault getFault() { return fault; } 2741060SN/A 2751060SN/A /** Checks whether or not this instruction has had its branch target 2761060SN/A * calculated yet. For now it is not utilized and is hacked to be 2771060SN/A * always false. 2782292SN/A * @todo: Actually use this instruction. 2791060SN/A */ 2801060SN/A bool doneTargCalc() { return false; } 2811060SN/A 2821684SN/A /** Returns the next PC. This could be the speculative next PC if it is 2831684SN/A * called prior to the actual branch target being calculated. 2841684SN/A */ 2851060SN/A Addr readNextPC() { return nextPC; } 2861060SN/A 2872935Sksewell@umich.edu /** Returns the next NPC. This could be the speculative next NPC if it is 2882935Sksewell@umich.edu * called prior to the actual branch target being calculated. 2892935Sksewell@umich.edu */ 2902935Sksewell@umich.edu Addr readNextNPC() { return nextNPC; } 2912935Sksewell@umich.edu 2921060SN/A /** Set the predicted target of this current instruction. */ 2931060SN/A void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; } 2941060SN/A 2951060SN/A /** Returns the predicted target of the branch. */ 2961060SN/A Addr readPredTarg() { return predPC; } 2971060SN/A 2981060SN/A /** Returns whether the instruction was predicted taken or not. */ 2992935Sksewell@umich.edu bool predTaken() 3003093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 3013093Sksewell@umich.edu { return predPC != (nextPC + sizeof(MachInst)); } 3023093Sksewell@umich.edu#else 3032935Sksewell@umich.edu { return predPC != (PC + sizeof(MachInst)); } 3042935Sksewell@umich.edu#endif 3051060SN/A 3061060SN/A /** Returns whether the instruction mispredicted. */ 3072935Sksewell@umich.edu bool mispredicted() 3083093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 3093093Sksewell@umich.edu { return predPC != nextNPC; } 3103093Sksewell@umich.edu#else 3112935Sksewell@umich.edu { return predPC != nextPC; } 3122935Sksewell@umich.edu#endif 3131060SN/A // 3141060SN/A // Instruction types. Forward checks to StaticInst object. 3151060SN/A // 3161060SN/A bool isNop() const { return staticInst->isNop(); } 3171060SN/A bool isMemRef() const { return staticInst->isMemRef(); } 3181060SN/A bool isLoad() const { return staticInst->isLoad(); } 3191060SN/A bool isStore() const { return staticInst->isStore(); } 3202336SN/A bool isStoreConditional() const 3212336SN/A { return staticInst->isStoreConditional(); } 3221060SN/A bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 3231060SN/A bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 3241060SN/A bool isCopy() const { return staticInst->isCopy(); } 3251060SN/A bool isInteger() const { return staticInst->isInteger(); } 3261060SN/A bool isFloating() const { return staticInst->isFloating(); } 3271060SN/A bool isControl() const { return staticInst->isControl(); } 3281060SN/A bool isCall() const { return staticInst->isCall(); } 3291060SN/A bool isReturn() const { return staticInst->isReturn(); } 3301060SN/A bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 3311060SN/A bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 3321060SN/A bool isCondCtrl() const { return staticInst->isCondCtrl(); } 3331060SN/A bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 3342935Sksewell@umich.edu bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 3351060SN/A bool isThreadSync() const { return staticInst->isThreadSync(); } 3361060SN/A bool isSerializing() const { return staticInst->isSerializing(); } 3372292SN/A bool isSerializeBefore() const 3382731Sktlim@umich.edu { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 3392292SN/A bool isSerializeAfter() const 3402731Sktlim@umich.edu { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 3411060SN/A bool isMemBarrier() const { return staticInst->isMemBarrier(); } 3421060SN/A bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 3431060SN/A bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 3442292SN/A bool isQuiesce() const { return staticInst->isQuiesce(); } 3452336SN/A bool isIprAccess() const { return staticInst->isIprAccess(); } 3462308SN/A bool isUnverifiable() const { return staticInst->isUnverifiable(); } 3472292SN/A 3482292SN/A /** Temporarily sets this instruction as a serialize before instruction. */ 3492731Sktlim@umich.edu void setSerializeBefore() { status.set(SerializeBefore); } 3502292SN/A 3512292SN/A /** Clears the serializeBefore part of this instruction. */ 3522731Sktlim@umich.edu void clearSerializeBefore() { status.reset(SerializeBefore); } 3532292SN/A 3542292SN/A /** Checks if this serializeBefore is only temporarily set. */ 3552731Sktlim@umich.edu bool isTempSerializeBefore() { return status[SerializeBefore]; } 3562292SN/A 3572292SN/A /** Temporarily sets this instruction as a serialize after instruction. */ 3582731Sktlim@umich.edu void setSerializeAfter() { status.set(SerializeAfter); } 3592292SN/A 3602292SN/A /** Clears the serializeAfter part of this instruction.*/ 3612731Sktlim@umich.edu void clearSerializeAfter() { status.reset(SerializeAfter); } 3622292SN/A 3632292SN/A /** Checks if this serializeAfter is only temporarily set. */ 3642731Sktlim@umich.edu bool isTempSerializeAfter() { return status[SerializeAfter]; } 3652292SN/A 3662731Sktlim@umich.edu /** Sets the serialization part of this instruction as handled. */ 3672731Sktlim@umich.edu void setSerializeHandled() { status.set(SerializeHandled); } 3682292SN/A 3692292SN/A /** Checks if the serialization part of this instruction has been 3702292SN/A * handled. This does not apply to the temporary serializing 3712292SN/A * state; it only applies to this instruction's own permanent 3722292SN/A * serializing state. 3732292SN/A */ 3742731Sktlim@umich.edu bool isSerializeHandled() { return status[SerializeHandled]; } 3751060SN/A 3761464SN/A /** Returns the opclass of this instruction. */ 3771464SN/A OpClass opClass() const { return staticInst->opClass(); } 3781464SN/A 3791464SN/A /** Returns the branch target address. */ 3801464SN/A Addr branchTarget() const { return staticInst->branchTarget(PC); } 3811464SN/A 3822292SN/A /** Returns the number of source registers. */ 3832292SN/A int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 3841684SN/A 3852292SN/A /** Returns the number of destination registers. */ 3861060SN/A int8_t numDestRegs() const { return staticInst->numDestRegs(); } 3871060SN/A 3881060SN/A // the following are used to track physical register usage 3891060SN/A // for machines with separate int & FP reg files 3901060SN/A int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 3911060SN/A int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 3921060SN/A 3931060SN/A /** Returns the logical register index of the i'th destination register. */ 3942292SN/A RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 3951060SN/A 3961060SN/A /** Returns the logical register index of the i'th source register. */ 3972292SN/A RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 3981060SN/A 3991684SN/A /** Returns the result of an integer instruction. */ 4001464SN/A uint64_t readIntResult() { return instResult.integer; } 4011684SN/A 4021684SN/A /** Returns the result of a floating point instruction. */ 4032356SN/A float readFloatResult() { return (float)instResult.dbl; } 4041684SN/A 4051684SN/A /** Returns the result of a floating point (double) instruction. */ 4061464SN/A double readDoubleResult() { return instResult.dbl; } 4071060SN/A 4082702Sktlim@umich.edu /** Records an integer register being set to a value. */ 4093735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 4101060SN/A { 4113326Sktlim@umich.edu if (recordResult) 4123326Sktlim@umich.edu instResult.integer = val; 4131060SN/A } 4141060SN/A 4152702Sktlim@umich.edu /** Records an fp register being set to a value. */ 4163735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 4173735Sstever@eecs.umich.edu int width) 4182690Sktlim@umich.edu { 4193326Sktlim@umich.edu if (recordResult) { 4203326Sktlim@umich.edu if (width == 32) 4213326Sktlim@umich.edu instResult.dbl = (double)val; 4223326Sktlim@umich.edu else if (width == 64) 4233326Sktlim@umich.edu instResult.dbl = val; 4243326Sktlim@umich.edu else 4253326Sktlim@umich.edu panic("Unsupported width!"); 4263326Sktlim@umich.edu } 4272690Sktlim@umich.edu } 4282690Sktlim@umich.edu 4292702Sktlim@umich.edu /** Records an fp register being set to a value. */ 4303735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 4311060SN/A { 4323326Sktlim@umich.edu if (recordResult) 4333326Sktlim@umich.edu instResult.dbl = (double)val; 4342308SN/A } 4351060SN/A 4362702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 4373735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 4383735Sstever@eecs.umich.edu int width) 4392308SN/A { 4403326Sktlim@umich.edu if (recordResult) 4413326Sktlim@umich.edu instResult.integer = val; 4422308SN/A } 4431060SN/A 4442702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 4453735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 4462308SN/A { 4473326Sktlim@umich.edu if (recordResult) 4483326Sktlim@umich.edu instResult.integer = val; 4491060SN/A } 4501060SN/A 4512190SN/A /** Records that one of the source registers is ready. */ 4522292SN/A void markSrcRegReady(); 4532190SN/A 4542331SN/A /** Marks a specific register as ready. */ 4552292SN/A void markSrcRegReady(RegIndex src_idx); 4562190SN/A 4571684SN/A /** Returns if a source register is ready. */ 4581464SN/A bool isReadySrcRegIdx(int idx) const 4591464SN/A { 4601464SN/A return this->_readySrcRegIdx[idx]; 4611464SN/A } 4621464SN/A 4631684SN/A /** Sets this instruction as completed. */ 4642731Sktlim@umich.edu void setCompleted() { status.set(Completed); } 4651464SN/A 4662292SN/A /** Returns whether or not this instruction is completed. */ 4672731Sktlim@umich.edu bool isCompleted() const { return status[Completed]; } 4681464SN/A 4692731Sktlim@umich.edu /** Marks the result as ready. */ 4702731Sktlim@umich.edu void setResultReady() { status.set(ResultReady); } 4712308SN/A 4722731Sktlim@umich.edu /** Returns whether or not the result is ready. */ 4732731Sktlim@umich.edu bool isResultReady() const { return status[ResultReady]; } 4742308SN/A 4751060SN/A /** Sets this instruction as ready to issue. */ 4762731Sktlim@umich.edu void setCanIssue() { status.set(CanIssue); } 4771060SN/A 4781060SN/A /** Returns whether or not this instruction is ready to issue. */ 4792731Sktlim@umich.edu bool readyToIssue() const { return status[CanIssue]; } 4801060SN/A 4811060SN/A /** Sets this instruction as issued from the IQ. */ 4822731Sktlim@umich.edu void setIssued() { status.set(Issued); } 4831060SN/A 4841060SN/A /** Returns whether or not this instruction has issued. */ 4852731Sktlim@umich.edu bool isIssued() const { return status[Issued]; } 4861060SN/A 4871060SN/A /** Sets this instruction as executed. */ 4882731Sktlim@umich.edu void setExecuted() { status.set(Executed); } 4891060SN/A 4901060SN/A /** Returns whether or not this instruction has executed. */ 4912731Sktlim@umich.edu bool isExecuted() const { return status[Executed]; } 4921060SN/A 4931060SN/A /** Sets this instruction as ready to commit. */ 4942731Sktlim@umich.edu void setCanCommit() { status.set(CanCommit); } 4951060SN/A 4961061SN/A /** Clears this instruction as being ready to commit. */ 4972731Sktlim@umich.edu void clearCanCommit() { status.reset(CanCommit); } 4981061SN/A 4991060SN/A /** Returns whether or not this instruction is ready to commit. */ 5002731Sktlim@umich.edu bool readyToCommit() const { return status[CanCommit]; } 5012731Sktlim@umich.edu 5022731Sktlim@umich.edu void setAtCommit() { status.set(AtCommit); } 5032731Sktlim@umich.edu 5042731Sktlim@umich.edu bool isAtCommit() { return status[AtCommit]; } 5051060SN/A 5062292SN/A /** Sets this instruction as committed. */ 5072731Sktlim@umich.edu void setCommitted() { status.set(Committed); } 5082292SN/A 5092292SN/A /** Returns whether or not this instruction is committed. */ 5102731Sktlim@umich.edu bool isCommitted() const { return status[Committed]; } 5112292SN/A 5121060SN/A /** Sets this instruction as squashed. */ 5132731Sktlim@umich.edu void setSquashed() { status.set(Squashed); } 5141060SN/A 5151060SN/A /** Returns whether or not this instruction is squashed. */ 5162731Sktlim@umich.edu bool isSquashed() const { return status[Squashed]; } 5171060SN/A 5182292SN/A //Instruction Queue Entry 5192292SN/A //----------------------- 5202292SN/A /** Sets this instruction as a entry the IQ. */ 5212731Sktlim@umich.edu void setInIQ() { status.set(IqEntry); } 5222292SN/A 5232292SN/A /** Sets this instruction as a entry the IQ. */ 5242731Sktlim@umich.edu void clearInIQ() { status.reset(IqEntry); } 5252731Sktlim@umich.edu 5262731Sktlim@umich.edu /** Returns whether or not this instruction has issued. */ 5272731Sktlim@umich.edu bool isInIQ() const { return status[IqEntry]; } 5282292SN/A 5291060SN/A /** Sets this instruction as squashed in the IQ. */ 5302731Sktlim@umich.edu void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 5311060SN/A 5321060SN/A /** Returns whether or not this instruction is squashed in the IQ. */ 5332731Sktlim@umich.edu bool isSquashedInIQ() const { return status[SquashedInIQ]; } 5342292SN/A 5352292SN/A 5362292SN/A //Load / Store Queue Functions 5372292SN/A //----------------------- 5382292SN/A /** Sets this instruction as a entry the LSQ. */ 5392731Sktlim@umich.edu void setInLSQ() { status.set(LsqEntry); } 5402292SN/A 5412292SN/A /** Sets this instruction as a entry the LSQ. */ 5422731Sktlim@umich.edu void removeInLSQ() { status.reset(LsqEntry); } 5432731Sktlim@umich.edu 5442731Sktlim@umich.edu /** Returns whether or not this instruction is in the LSQ. */ 5452731Sktlim@umich.edu bool isInLSQ() const { return status[LsqEntry]; } 5462292SN/A 5472292SN/A /** Sets this instruction as squashed in the LSQ. */ 5482731Sktlim@umich.edu void setSquashedInLSQ() { status.set(SquashedInLSQ);} 5492292SN/A 5502292SN/A /** Returns whether or not this instruction is squashed in the LSQ. */ 5512731Sktlim@umich.edu bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 5522292SN/A 5532292SN/A 5542292SN/A //Reorder Buffer Functions 5552292SN/A //----------------------- 5562292SN/A /** Sets this instruction as a entry the ROB. */ 5572731Sktlim@umich.edu void setInROB() { status.set(RobEntry); } 5582292SN/A 5592292SN/A /** Sets this instruction as a entry the ROB. */ 5602731Sktlim@umich.edu void clearInROB() { status.reset(RobEntry); } 5612731Sktlim@umich.edu 5622731Sktlim@umich.edu /** Returns whether or not this instruction is in the ROB. */ 5632731Sktlim@umich.edu bool isInROB() const { return status[RobEntry]; } 5642292SN/A 5652292SN/A /** Sets this instruction as squashed in the ROB. */ 5662731Sktlim@umich.edu void setSquashedInROB() { status.set(SquashedInROB); } 5672292SN/A 5682292SN/A /** Returns whether or not this instruction is squashed in the ROB. */ 5692731Sktlim@umich.edu bool isSquashedInROB() const { return status[SquashedInROB]; } 5702292SN/A 5711060SN/A /** Read the PC of this instruction. */ 5721464SN/A const Addr readPC() const { return PC; } 5731060SN/A 5741060SN/A /** Set the next PC of this instruction (its actual target). */ 5752308SN/A void setNextPC(uint64_t val) 5762308SN/A { 5772308SN/A nextPC = val; 5782308SN/A } 5792190SN/A 5802935Sksewell@umich.edu /** Set the next NPC of this instruction (the target in Mips or Sparc).*/ 5812935Sksewell@umich.edu void setNextNPC(uint64_t val) 5822935Sksewell@umich.edu { 5832935Sksewell@umich.edu nextNPC = val; 5842935Sksewell@umich.edu } 5852935Sksewell@umich.edu 5862702Sktlim@umich.edu /** Sets the ASID. */ 5872292SN/A void setASID(short addr_space_id) { asid = addr_space_id; } 5882292SN/A 5892702Sktlim@umich.edu /** Sets the thread id. */ 5902702Sktlim@umich.edu void setTid(unsigned tid) { threadNumber = tid; } 5912292SN/A 5922731Sktlim@umich.edu /** Sets the pointer to the thread state. */ 5932702Sktlim@umich.edu void setThreadState(ImplState *state) { thread = state; } 5941060SN/A 5952731Sktlim@umich.edu /** Returns the thread context. */ 5962680Sktlim@umich.edu ThreadContext *tcBase() { return thread->getTC(); } 5971464SN/A 5981464SN/A private: 5991684SN/A /** Instruction effective address. 6001684SN/A * @todo: Consider if this is necessary or not. 6011684SN/A */ 6021464SN/A Addr instEffAddr; 6032292SN/A 6041684SN/A /** Whether or not the effective address calculation is completed. 6051684SN/A * @todo: Consider if this is necessary or not. 6061684SN/A */ 6071464SN/A bool eaCalcDone; 6081464SN/A 6091464SN/A public: 6101684SN/A /** Sets the effective address. */ 6111464SN/A void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 6121684SN/A 6131684SN/A /** Returns the effective address. */ 6141464SN/A const Addr &getEA() const { return instEffAddr; } 6151684SN/A 6161684SN/A /** Returns whether or not the eff. addr. calculation has been completed. */ 6171464SN/A bool doneEACalc() { return eaCalcDone; } 6181684SN/A 6191684SN/A /** Returns whether or not the eff. addr. source registers are ready. */ 6201464SN/A bool eaSrcsReady(); 6211681SN/A 6222292SN/A /** Whether or not the memory operation is done. */ 6232292SN/A bool memOpDone; 6242292SN/A 6251681SN/A public: 6261684SN/A /** Load queue index. */ 6271681SN/A int16_t lqIdx; 6281684SN/A 6291684SN/A /** Store queue index. */ 6301681SN/A int16_t sqIdx; 6312292SN/A 6322292SN/A /** Iterator pointing to this BaseDynInst in the list of all insts. */ 6332292SN/A ListIt instListIt; 6342292SN/A 6352292SN/A /** Returns iterator to this instruction in the list of all insts. */ 6362292SN/A ListIt &getInstListIt() { return instListIt; } 6372292SN/A 6382292SN/A /** Sets iterator for this instruction in the list of all insts. */ 6392292SN/A void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 6403326Sktlim@umich.edu 6413326Sktlim@umich.edu public: 6423326Sktlim@umich.edu /** Returns the number of consecutive store conditional failures. */ 6433326Sktlim@umich.edu unsigned readStCondFailures() 6443326Sktlim@umich.edu { return thread->storeCondFailures; } 6453326Sktlim@umich.edu 6463326Sktlim@umich.edu /** Sets the number of consecutive store conditional failures. */ 6473326Sktlim@umich.edu void setStCondFailures(unsigned sc_failures) 6483326Sktlim@umich.edu { thread->storeCondFailures = sc_failures; } 6491060SN/A}; 6501060SN/A 6511060SN/Atemplate<class Impl> 6521060SN/Atemplate<class T> 6532132SN/Ainline Fault 6541060SN/ABaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 6551060SN/A{ 6562695Sktlim@umich.edu // Sometimes reads will get retried, so they may come through here 6572695Sktlim@umich.edu // twice. 6582695Sktlim@umich.edu if (!req) { 6592695Sktlim@umich.edu req = new Request(); 6602695Sktlim@umich.edu req->setVirt(asid, addr, sizeof(T), flags, this->PC); 6612695Sktlim@umich.edu req->setThreadContext(thread->readCpuId(), threadNumber); 6622695Sktlim@umich.edu } else { 6632695Sktlim@umich.edu assert(addr == req->getVaddr()); 6642292SN/A } 6652292SN/A 6662669Sktlim@umich.edu if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() > 6672292SN/A TheISA::VMPageSize) { 6682292SN/A return TheISA::genAlignmentFault(); 6692292SN/A } 6701060SN/A 6712690Sktlim@umich.edu fault = cpu->translateDataReadReq(req, thread); 6721060SN/A 6732678Sktlim@umich.edu if (fault == NoFault) { 6742678Sktlim@umich.edu effAddr = req->getVaddr(); 6752678Sktlim@umich.edu physEffAddr = req->getPaddr(); 6762678Sktlim@umich.edu memReqFlags = req->getFlags(); 6771060SN/A 6782690Sktlim@umich.edu#if 0 6792292SN/A if (cpu->system->memctrl->badaddr(physEffAddr)) { 6802292SN/A fault = TheISA::genMachineCheckFault(); 6812292SN/A data = (T)-1; 6822292SN/A this->setExecuted(); 6832292SN/A } else { 6842292SN/A fault = cpu->read(req, data, lqIdx); 6852292SN/A } 6862292SN/A#else 6871681SN/A fault = cpu->read(req, data, lqIdx); 6882632Sstever@eecs.umich.edu#endif 6891684SN/A } else { 6901060SN/A // Return a fixed value to keep simulation deterministic even 6911060SN/A // along misspeculated paths. 6921060SN/A data = (T)-1; 6932292SN/A 6942292SN/A // Commit will have to clean up whatever happened. Set this 6952292SN/A // instruction as executed. 6962292SN/A this->setExecuted(); 6971060SN/A } 6981060SN/A 6991060SN/A if (traceData) { 7001060SN/A traceData->setAddr(addr); 7011060SN/A traceData->setData(data); 7021060SN/A } 7031060SN/A 7041060SN/A return fault; 7051060SN/A} 7061060SN/A 7071060SN/Atemplate<class Impl> 7081060SN/Atemplate<class T> 7092132SN/Ainline Fault 7101060SN/ABaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 7111060SN/A{ 7121060SN/A if (traceData) { 7131060SN/A traceData->setAddr(addr); 7141060SN/A traceData->setData(data); 7151060SN/A } 7161060SN/A 7172695Sktlim@umich.edu assert(req == NULL); 7182695Sktlim@umich.edu 7192669Sktlim@umich.edu req = new Request(); 7202669Sktlim@umich.edu req->setVirt(asid, addr, sizeof(T), flags, this->PC); 7212683Sktlim@umich.edu req->setThreadContext(thread->readCpuId(), threadNumber); 7221060SN/A 7232669Sktlim@umich.edu if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() > 7242292SN/A TheISA::VMPageSize) { 7252292SN/A return TheISA::genAlignmentFault(); 7262292SN/A } 7271060SN/A 7282690Sktlim@umich.edu fault = cpu->translateDataWriteReq(req, thread); 7291060SN/A 7302090SN/A if (fault == NoFault) { 7312678Sktlim@umich.edu effAddr = req->getVaddr(); 7322678Sktlim@umich.edu physEffAddr = req->getPaddr(); 7332678Sktlim@umich.edu memReqFlags = req->getFlags(); 7342690Sktlim@umich.edu#if 0 7352292SN/A if (cpu->system->memctrl->badaddr(physEffAddr)) { 7362292SN/A fault = TheISA::genMachineCheckFault(); 7372292SN/A } else { 7382292SN/A fault = cpu->write(req, data, sqIdx); 7392292SN/A } 7402292SN/A#else 7411681SN/A fault = cpu->write(req, data, sqIdx); 7422632Sstever@eecs.umich.edu#endif 7431060SN/A } 7441060SN/A 7451060SN/A if (res) { 7461060SN/A // always return some result to keep misspeculated paths 7471060SN/A // (which will ignore faults) deterministic 7482669Sktlim@umich.edu *res = (fault == NoFault) ? req->getScResult() : 0; 7491060SN/A } 7501060SN/A 7511060SN/A return fault; 7521060SN/A} 7531060SN/A 7541464SN/A#endif // __CPU_BASE_DYN_INST_HH__ 755