base.cc revision 9430:a113f27b68bd
1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * Copyright (c) 2011 Regents of the University of California 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 * Nathan Binkert 43 * Rick Strong 44 */ 45 46#include <iostream> 47#include <sstream> 48#include <string> 49 50#include "arch/tlb.hh" 51#include "base/loader/symtab.hh" 52#include "base/cprintf.hh" 53#include "base/misc.hh" 54#include "base/output.hh" 55#include "base/trace.hh" 56#include "cpu/base.hh" 57#include "cpu/checker/cpu.hh" 58#include "cpu/cpuevent.hh" 59#include "cpu/profile.hh" 60#include "cpu/thread_context.hh" 61#include "debug/SyscallVerbose.hh" 62#include "params/BaseCPU.hh" 63#include "sim/full_system.hh" 64#include "sim/process.hh" 65#include "sim/sim_events.hh" 66#include "sim/sim_exit.hh" 67#include "sim/system.hh" 68 69// Hack 70#include "sim/stat_control.hh" 71 72using namespace std; 73 74vector<BaseCPU *> BaseCPU::cpuList; 75 76// This variable reflects the max number of threads in any CPU. Be 77// careful to only use it once all the CPUs that you care about have 78// been initialized 79int maxThreadsPerCPU = 1; 80 81CPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 82 : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 83 cpu(_cpu), _repeatEvent(true) 84{ 85 if (_interval) 86 cpu->schedule(this, curTick() + _interval); 87} 88 89void 90CPUProgressEvent::process() 91{ 92 Counter temp = cpu->totalOps(); 93#ifndef NDEBUG 94 double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod()); 95 96 DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 97 "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 98 ipc); 99 ipc = 0.0; 100#else 101 cprintf("%lli: %s progress event, total committed:%i, progress insts " 102 "committed: %lli\n", curTick(), cpu->name(), temp, 103 temp - lastNumInst); 104#endif 105 lastNumInst = temp; 106 107 if (_repeatEvent) 108 cpu->schedule(this, curTick() + _interval); 109} 110 111const char * 112CPUProgressEvent::description() const 113{ 114 return "CPU Progress"; 115} 116 117BaseCPU::BaseCPU(Params *p, bool is_checker) 118 : MemObject(p), instCnt(0), _cpuId(p->cpu_id), 119 _instMasterId(p->system->getMasterId(name() + ".inst")), 120 _dataMasterId(p->system->getMasterId(name() + ".data")), 121 _taskId(ContextSwitchTaskId::Unknown), _pid(Request::invldPid), 122 _switchedOut(p->defer_registration), 123 interrupts(p->interrupts), profileEvent(NULL), 124 numThreads(p->numThreads), system(p->system) 125{ 126 // if Python did not provide a valid ID, do it here 127 if (_cpuId == -1 ) { 128 _cpuId = cpuList.size(); 129 } 130 131 // add self to global list of CPUs 132 cpuList.push_back(this); 133 134 DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId); 135 136 if (numThreads > maxThreadsPerCPU) 137 maxThreadsPerCPU = numThreads; 138 139 // allocate per-thread instruction-based event queues 140 comInstEventQueue = new EventQueue *[numThreads]; 141 for (ThreadID tid = 0; tid < numThreads; ++tid) 142 comInstEventQueue[tid] = 143 new EventQueue("instruction-based event queue"); 144 145 // 146 // set up instruction-count-based termination events, if any 147 // 148 if (p->max_insts_any_thread != 0) { 149 const char *cause = "a thread reached the max instruction count"; 150 for (ThreadID tid = 0; tid < numThreads; ++tid) { 151 Event *event = new SimLoopExitEvent(cause, 0); 152 comInstEventQueue[tid]->schedule(event, p->max_insts_any_thread); 153 } 154 } 155 156 if (p->max_insts_all_threads != 0) { 157 const char *cause = "all threads reached the max instruction count"; 158 159 // allocate & initialize shared downcounter: each event will 160 // decrement this when triggered; simulation will terminate 161 // when counter reaches 0 162 int *counter = new int; 163 *counter = numThreads; 164 for (ThreadID tid = 0; tid < numThreads; ++tid) { 165 Event *event = new CountedExitEvent(cause, *counter); 166 comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 167 } 168 } 169 170 // allocate per-thread load-based event queues 171 comLoadEventQueue = new EventQueue *[numThreads]; 172 for (ThreadID tid = 0; tid < numThreads; ++tid) 173 comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 174 175 // 176 // set up instruction-count-based termination events, if any 177 // 178 if (p->max_loads_any_thread != 0) { 179 const char *cause = "a thread reached the max load count"; 180 for (ThreadID tid = 0; tid < numThreads; ++tid) { 181 Event *event = new SimLoopExitEvent(cause, 0); 182 comLoadEventQueue[tid]->schedule(event, p->max_loads_any_thread); 183 } 184 } 185 186 if (p->max_loads_all_threads != 0) { 187 const char *cause = "all threads reached the max load count"; 188 // allocate & initialize shared downcounter: each event will 189 // decrement this when triggered; simulation will terminate 190 // when counter reaches 0 191 int *counter = new int; 192 *counter = numThreads; 193 for (ThreadID tid = 0; tid < numThreads; ++tid) { 194 Event *event = new CountedExitEvent(cause, *counter); 195 comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 196 } 197 } 198 199 functionTracingEnabled = false; 200 if (p->function_trace) { 201 const string fname = csprintf("ftrace.%s", name()); 202 functionTraceStream = simout.find(fname); 203 if (!functionTraceStream) 204 functionTraceStream = simout.create(fname); 205 206 currentFunctionStart = currentFunctionEnd = 0; 207 functionEntryTick = p->function_trace_start; 208 209 if (p->function_trace_start == 0) { 210 functionTracingEnabled = true; 211 } else { 212 typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap; 213 Event *event = new wrap(this, true); 214 schedule(event, p->function_trace_start); 215 } 216 } 217 218 // The interrupts should always be present unless this CPU is 219 // switched in later or in case it is a checker CPU 220 if (!params()->defer_registration && !is_checker) { 221 if (interrupts) { 222 interrupts->setCPU(this); 223 } else { 224 fatal("CPU %s has no interrupt controller.\n" 225 "Ensure createInterruptController() is called.\n", name()); 226 } 227 } 228 229 if (FullSystem) { 230 if (params()->profile) 231 profileEvent = new ProfileEvent(this, params()->profile); 232 } 233 tracer = params()->tracer; 234 235 if (params()->isa.size() != numThreads) { 236 fatal("Number of ISAs (%i) assigned to the CPU does not equal number " 237 "of threads (%i).\n", params()->isa.size(), numThreads); 238 } 239} 240 241void 242BaseCPU::enableFunctionTrace() 243{ 244 functionTracingEnabled = true; 245} 246 247BaseCPU::~BaseCPU() 248{ 249 delete profileEvent; 250 delete[] comLoadEventQueue; 251 delete[] comInstEventQueue; 252} 253 254void 255BaseCPU::init() 256{ 257 if (!params()->defer_registration) 258 registerThreadContexts(); 259} 260 261void 262BaseCPU::startup() 263{ 264 if (FullSystem) { 265 if (!params()->defer_registration && profileEvent) 266 schedule(profileEvent, curTick()); 267 } 268 269 if (params()->progress_interval) { 270 new CPUProgressEvent(this, params()->progress_interval); 271 } 272} 273 274 275void 276BaseCPU::regStats() 277{ 278 using namespace Stats; 279 280 numCycles 281 .name(name() + ".numCycles") 282 .desc("number of cpu cycles simulated") 283 ; 284 285 numWorkItemsStarted 286 .name(name() + ".numWorkItemsStarted") 287 .desc("number of work items this cpu started") 288 ; 289 290 numWorkItemsCompleted 291 .name(name() + ".numWorkItemsCompleted") 292 .desc("number of work items this cpu completed") 293 ; 294 295 int size = threadContexts.size(); 296 if (size > 1) { 297 for (int i = 0; i < size; ++i) { 298 stringstream namestr; 299 ccprintf(namestr, "%s.ctx%d", name(), i); 300 threadContexts[i]->regStats(namestr.str()); 301 } 302 } else if (size == 1) 303 threadContexts[0]->regStats(name()); 304} 305 306BaseMasterPort & 307BaseCPU::getMasterPort(const string &if_name, PortID idx) 308{ 309 // Get the right port based on name. This applies to all the 310 // subclasses of the base CPU and relies on their implementation 311 // of getDataPort and getInstPort. In all cases there methods 312 // return a CpuPort pointer. 313 if (if_name == "dcache_port") 314 return getDataPort(); 315 else if (if_name == "icache_port") 316 return getInstPort(); 317 else 318 return MemObject::getMasterPort(if_name, idx); 319} 320 321void 322BaseCPU::registerThreadContexts() 323{ 324 ThreadID size = threadContexts.size(); 325 for (ThreadID tid = 0; tid < size; ++tid) { 326 ThreadContext *tc = threadContexts[tid]; 327 328 /** This is so that contextId and cpuId match where there is a 329 * 1cpu:1context relationship. Otherwise, the order of registration 330 * could affect the assignment and cpu 1 could have context id 3, for 331 * example. We may even want to do something like this for SMT so that 332 * cpu 0 has the lowest thread contexts and cpu N has the highest, but 333 * I'll just do this for now 334 */ 335 if (numThreads == 1) 336 tc->setContextId(system->registerThreadContext(tc, _cpuId)); 337 else 338 tc->setContextId(system->registerThreadContext(tc)); 339 340 if (!FullSystem) 341 tc->getProcessPtr()->assignThreadContext(tc->contextId()); 342 } 343} 344 345 346int 347BaseCPU::findContext(ThreadContext *tc) 348{ 349 ThreadID size = threadContexts.size(); 350 for (ThreadID tid = 0; tid < size; ++tid) { 351 if (tc == threadContexts[tid]) 352 return tid; 353 } 354 return 0; 355} 356 357void 358BaseCPU::switchOut() 359{ 360 assert(!_switchedOut); 361 _switchedOut = true; 362 if (profileEvent && profileEvent->scheduled()) 363 deschedule(profileEvent); 364} 365 366void 367BaseCPU::takeOverFrom(BaseCPU *oldCPU) 368{ 369 assert(threadContexts.size() == oldCPU->threadContexts.size()); 370 assert(_cpuId == oldCPU->cpuId()); 371 assert(_switchedOut); 372 assert(oldCPU != this); 373 _pid = oldCPU->getPid(); 374 _taskId = oldCPU->taskId(); 375 _switchedOut = false; 376 377 ThreadID size = threadContexts.size(); 378 for (ThreadID i = 0; i < size; ++i) { 379 ThreadContext *newTC = threadContexts[i]; 380 ThreadContext *oldTC = oldCPU->threadContexts[i]; 381 382 newTC->takeOverFrom(oldTC); 383 384 CpuEvent::replaceThreadContext(oldTC, newTC); 385 386 assert(newTC->contextId() == oldTC->contextId()); 387 assert(newTC->threadId() == oldTC->threadId()); 388 system->replaceThreadContext(newTC, newTC->contextId()); 389 390 /* This code no longer works since the zero register (e.g., 391 * r31 on Alpha) doesn't necessarily contain zero at this 392 * point. 393 if (DTRACE(Context)) 394 ThreadContext::compare(oldTC, newTC); 395 */ 396 397 BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort(); 398 BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort(); 399 BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort(); 400 BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort(); 401 402 // Move over any table walker ports if they exist 403 if (new_itb_port) { 404 assert(!new_itb_port->isConnected()); 405 assert(old_itb_port); 406 assert(old_itb_port->isConnected()); 407 BaseSlavePort &slavePort = old_itb_port->getSlavePort(); 408 old_itb_port->unbind(); 409 new_itb_port->bind(slavePort); 410 } 411 if (new_dtb_port) { 412 assert(!new_dtb_port->isConnected()); 413 assert(old_dtb_port); 414 assert(old_dtb_port->isConnected()); 415 BaseSlavePort &slavePort = old_dtb_port->getSlavePort(); 416 old_dtb_port->unbind(); 417 new_dtb_port->bind(slavePort); 418 } 419 420 // Checker whether or not we have to transfer CheckerCPU 421 // objects over in the switch 422 CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr(); 423 CheckerCPU *newChecker = newTC->getCheckerCpuPtr(); 424 if (oldChecker && newChecker) { 425 BaseMasterPort *old_checker_itb_port = 426 oldChecker->getITBPtr()->getMasterPort(); 427 BaseMasterPort *old_checker_dtb_port = 428 oldChecker->getDTBPtr()->getMasterPort(); 429 BaseMasterPort *new_checker_itb_port = 430 newChecker->getITBPtr()->getMasterPort(); 431 BaseMasterPort *new_checker_dtb_port = 432 newChecker->getDTBPtr()->getMasterPort(); 433 434 // Move over any table walker ports if they exist for checker 435 if (new_checker_itb_port) { 436 assert(!new_checker_itb_port->isConnected()); 437 assert(old_checker_itb_port); 438 assert(old_checker_itb_port->isConnected()); 439 BaseSlavePort &slavePort = 440 old_checker_itb_port->getSlavePort(); 441 old_checker_itb_port->unbind(); 442 new_checker_itb_port->bind(slavePort); 443 } 444 if (new_checker_dtb_port) { 445 assert(!new_checker_dtb_port->isConnected()); 446 assert(old_checker_dtb_port); 447 assert(old_checker_dtb_port->isConnected()); 448 BaseSlavePort &slavePort = 449 old_checker_dtb_port->getSlavePort(); 450 old_checker_dtb_port->unbind(); 451 new_checker_dtb_port->bind(slavePort); 452 } 453 } 454 } 455 456 interrupts = oldCPU->interrupts; 457 interrupts->setCPU(this); 458 oldCPU->interrupts = NULL; 459 460 if (FullSystem) { 461 for (ThreadID i = 0; i < size; ++i) 462 threadContexts[i]->profileClear(); 463 464 if (profileEvent) 465 schedule(profileEvent, curTick()); 466 } 467 468 // All CPUs have an instruction and a data port, and the new CPU's 469 // ports are dangling while the old CPU has its ports connected 470 // already. Unbind the old CPU and then bind the ports of the one 471 // we are switching to. 472 assert(!getInstPort().isConnected()); 473 assert(oldCPU->getInstPort().isConnected()); 474 BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort(); 475 oldCPU->getInstPort().unbind(); 476 getInstPort().bind(inst_peer_port); 477 478 assert(!getDataPort().isConnected()); 479 assert(oldCPU->getDataPort().isConnected()); 480 BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort(); 481 oldCPU->getDataPort().unbind(); 482 getDataPort().bind(data_peer_port); 483} 484 485 486BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval) 487 : cpu(_cpu), interval(_interval) 488{ } 489 490void 491BaseCPU::ProfileEvent::process() 492{ 493 ThreadID size = cpu->threadContexts.size(); 494 for (ThreadID i = 0; i < size; ++i) { 495 ThreadContext *tc = cpu->threadContexts[i]; 496 tc->profileSample(); 497 } 498 499 cpu->schedule(this, curTick() + interval); 500} 501 502void 503BaseCPU::serialize(std::ostream &os) 504{ 505 SERIALIZE_SCALAR(instCnt); 506 507 /* Unlike _pid, _taskId is not serialized, as they are dynamically 508 * assigned unique ids that are only meaningful for the duration of 509 * a specific run. We will need to serialize the entire taskMap in 510 * system. */ 511 SERIALIZE_SCALAR(_pid); 512 513 interrupts->serialize(os); 514} 515 516void 517BaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 518{ 519 UNSERIALIZE_SCALAR(instCnt); 520 UNSERIALIZE_SCALAR(_pid); 521 interrupts->unserialize(cp, section); 522} 523 524void 525BaseCPU::traceFunctionsInternal(Addr pc) 526{ 527 if (!debugSymbolTable) 528 return; 529 530 // if pc enters different function, print new function symbol and 531 // update saved range. Otherwise do nothing. 532 if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 533 string sym_str; 534 bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 535 currentFunctionStart, 536 currentFunctionEnd); 537 538 if (!found) { 539 // no symbol found: use addr as label 540 sym_str = csprintf("0x%x", pc); 541 currentFunctionStart = pc; 542 currentFunctionEnd = pc + 1; 543 } 544 545 ccprintf(*functionTraceStream, " (%d)\n%d: %s", 546 curTick() - functionEntryTick, curTick(), sym_str); 547 functionEntryTick = curTick(); 548 } 549} 550 551bool 552BaseCPU::CpuPort::recvTimingResp(PacketPtr pkt) 553{ 554 panic("BaseCPU doesn't expect recvTiming!\n"); 555 return true; 556} 557 558void 559BaseCPU::CpuPort::recvRetry() 560{ 561 panic("BaseCPU doesn't expect recvRetry!\n"); 562} 563 564void 565BaseCPU::CpuPort::recvFunctionalSnoop(PacketPtr pkt) 566{ 567 // No internal storage to update (in the general case). A CPU with 568 // internal storage, e.g. an LSQ that should be part of the 569 // coherent memory has to check against stored data. 570} 571