base.cc revision 9384:877293183bdf
1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * Copyright (c) 2011 Regents of the University of California 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 * Nathan Binkert 43 * Rick Strong 44 */ 45 46#include <iostream> 47#include <sstream> 48#include <string> 49 50#include "arch/tlb.hh" 51#include "base/loader/symtab.hh" 52#include "base/cprintf.hh" 53#include "base/misc.hh" 54#include "base/output.hh" 55#include "base/trace.hh" 56#include "cpu/base.hh" 57#include "cpu/checker/cpu.hh" 58#include "cpu/cpuevent.hh" 59#include "cpu/profile.hh" 60#include "cpu/thread_context.hh" 61#include "debug/SyscallVerbose.hh" 62#include "params/BaseCPU.hh" 63#include "sim/full_system.hh" 64#include "sim/process.hh" 65#include "sim/sim_events.hh" 66#include "sim/sim_exit.hh" 67#include "sim/system.hh" 68 69// Hack 70#include "sim/stat_control.hh" 71 72using namespace std; 73 74vector<BaseCPU *> BaseCPU::cpuList; 75 76// This variable reflects the max number of threads in any CPU. Be 77// careful to only use it once all the CPUs that you care about have 78// been initialized 79int maxThreadsPerCPU = 1; 80 81CPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 82 : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 83 cpu(_cpu), _repeatEvent(true) 84{ 85 if (_interval) 86 cpu->schedule(this, curTick() + _interval); 87} 88 89void 90CPUProgressEvent::process() 91{ 92 Counter temp = cpu->totalOps(); 93#ifndef NDEBUG 94 double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod()); 95 96 DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 97 "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 98 ipc); 99 ipc = 0.0; 100#else 101 cprintf("%lli: %s progress event, total committed:%i, progress insts " 102 "committed: %lli\n", curTick(), cpu->name(), temp, 103 temp - lastNumInst); 104#endif 105 lastNumInst = temp; 106 107 if (_repeatEvent) 108 cpu->schedule(this, curTick() + _interval); 109} 110 111const char * 112CPUProgressEvent::description() const 113{ 114 return "CPU Progress"; 115} 116 117BaseCPU::BaseCPU(Params *p, bool is_checker) 118 : MemObject(p), instCnt(0), _cpuId(p->cpu_id), 119 _instMasterId(p->system->getMasterId(name() + ".inst")), 120 _dataMasterId(p->system->getMasterId(name() + ".data")), 121 _taskId(ContextSwitchTaskId::Unknown), _pid(Request::invldPid), 122 interrupts(p->interrupts), profileEvent(NULL), 123 numThreads(p->numThreads), system(p->system) 124{ 125 // if Python did not provide a valid ID, do it here 126 if (_cpuId == -1 ) { 127 _cpuId = cpuList.size(); 128 } 129 130 // add self to global list of CPUs 131 cpuList.push_back(this); 132 133 DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId); 134 135 if (numThreads > maxThreadsPerCPU) 136 maxThreadsPerCPU = numThreads; 137 138 // allocate per-thread instruction-based event queues 139 comInstEventQueue = new EventQueue *[numThreads]; 140 for (ThreadID tid = 0; tid < numThreads; ++tid) 141 comInstEventQueue[tid] = 142 new EventQueue("instruction-based event queue"); 143 144 // 145 // set up instruction-count-based termination events, if any 146 // 147 if (p->max_insts_any_thread != 0) { 148 const char *cause = "a thread reached the max instruction count"; 149 for (ThreadID tid = 0; tid < numThreads; ++tid) { 150 Event *event = new SimLoopExitEvent(cause, 0); 151 comInstEventQueue[tid]->schedule(event, p->max_insts_any_thread); 152 } 153 } 154 155 if (p->max_insts_all_threads != 0) { 156 const char *cause = "all threads reached the max instruction count"; 157 158 // allocate & initialize shared downcounter: each event will 159 // decrement this when triggered; simulation will terminate 160 // when counter reaches 0 161 int *counter = new int; 162 *counter = numThreads; 163 for (ThreadID tid = 0; tid < numThreads; ++tid) { 164 Event *event = new CountedExitEvent(cause, *counter); 165 comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 166 } 167 } 168 169 // allocate per-thread load-based event queues 170 comLoadEventQueue = new EventQueue *[numThreads]; 171 for (ThreadID tid = 0; tid < numThreads; ++tid) 172 comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 173 174 // 175 // set up instruction-count-based termination events, if any 176 // 177 if (p->max_loads_any_thread != 0) { 178 const char *cause = "a thread reached the max load count"; 179 for (ThreadID tid = 0; tid < numThreads; ++tid) { 180 Event *event = new SimLoopExitEvent(cause, 0); 181 comLoadEventQueue[tid]->schedule(event, p->max_loads_any_thread); 182 } 183 } 184 185 if (p->max_loads_all_threads != 0) { 186 const char *cause = "all threads reached the max load count"; 187 // allocate & initialize shared downcounter: each event will 188 // decrement this when triggered; simulation will terminate 189 // when counter reaches 0 190 int *counter = new int; 191 *counter = numThreads; 192 for (ThreadID tid = 0; tid < numThreads; ++tid) { 193 Event *event = new CountedExitEvent(cause, *counter); 194 comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 195 } 196 } 197 198 functionTracingEnabled = false; 199 if (p->function_trace) { 200 const string fname = csprintf("ftrace.%s", name()); 201 functionTraceStream = simout.find(fname); 202 if (!functionTraceStream) 203 functionTraceStream = simout.create(fname); 204 205 currentFunctionStart = currentFunctionEnd = 0; 206 functionEntryTick = p->function_trace_start; 207 208 if (p->function_trace_start == 0) { 209 functionTracingEnabled = true; 210 } else { 211 typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap; 212 Event *event = new wrap(this, true); 213 schedule(event, p->function_trace_start); 214 } 215 } 216 217 // The interrupts should always be present unless this CPU is 218 // switched in later or in case it is a checker CPU 219 if (!params()->defer_registration && !is_checker) { 220 if (interrupts) { 221 interrupts->setCPU(this); 222 } else { 223 fatal("CPU %s has no interrupt controller.\n" 224 "Ensure createInterruptController() is called.\n", name()); 225 } 226 } 227 228 if (FullSystem) { 229 if (params()->profile) 230 profileEvent = new ProfileEvent(this, params()->profile); 231 } 232 tracer = params()->tracer; 233 234 if (params()->isa.size() != numThreads) { 235 fatal("Number of ISAs (%i) assigned to the CPU does not equal number " 236 "of threads (%i).\n", params()->isa.size(), numThreads); 237 } 238} 239 240void 241BaseCPU::enableFunctionTrace() 242{ 243 functionTracingEnabled = true; 244} 245 246BaseCPU::~BaseCPU() 247{ 248 delete profileEvent; 249 delete[] comLoadEventQueue; 250 delete[] comInstEventQueue; 251} 252 253void 254BaseCPU::init() 255{ 256 if (!params()->defer_registration) 257 registerThreadContexts(); 258} 259 260void 261BaseCPU::startup() 262{ 263 if (FullSystem) { 264 if (!params()->defer_registration && profileEvent) 265 schedule(profileEvent, curTick()); 266 } 267 268 if (params()->progress_interval) { 269 new CPUProgressEvent(this, params()->progress_interval); 270 } 271} 272 273 274void 275BaseCPU::regStats() 276{ 277 using namespace Stats; 278 279 numCycles 280 .name(name() + ".numCycles") 281 .desc("number of cpu cycles simulated") 282 ; 283 284 numWorkItemsStarted 285 .name(name() + ".numWorkItemsStarted") 286 .desc("number of work items this cpu started") 287 ; 288 289 numWorkItemsCompleted 290 .name(name() + ".numWorkItemsCompleted") 291 .desc("number of work items this cpu completed") 292 ; 293 294 int size = threadContexts.size(); 295 if (size > 1) { 296 for (int i = 0; i < size; ++i) { 297 stringstream namestr; 298 ccprintf(namestr, "%s.ctx%d", name(), i); 299 threadContexts[i]->regStats(namestr.str()); 300 } 301 } else if (size == 1) 302 threadContexts[0]->regStats(name()); 303} 304 305BaseMasterPort & 306BaseCPU::getMasterPort(const string &if_name, PortID idx) 307{ 308 // Get the right port based on name. This applies to all the 309 // subclasses of the base CPU and relies on their implementation 310 // of getDataPort and getInstPort. In all cases there methods 311 // return a CpuPort pointer. 312 if (if_name == "dcache_port") 313 return getDataPort(); 314 else if (if_name == "icache_port") 315 return getInstPort(); 316 else 317 return MemObject::getMasterPort(if_name, idx); 318} 319 320void 321BaseCPU::registerThreadContexts() 322{ 323 ThreadID size = threadContexts.size(); 324 for (ThreadID tid = 0; tid < size; ++tid) { 325 ThreadContext *tc = threadContexts[tid]; 326 327 /** This is so that contextId and cpuId match where there is a 328 * 1cpu:1context relationship. Otherwise, the order of registration 329 * could affect the assignment and cpu 1 could have context id 3, for 330 * example. We may even want to do something like this for SMT so that 331 * cpu 0 has the lowest thread contexts and cpu N has the highest, but 332 * I'll just do this for now 333 */ 334 if (numThreads == 1) 335 tc->setContextId(system->registerThreadContext(tc, _cpuId)); 336 else 337 tc->setContextId(system->registerThreadContext(tc)); 338 339 if (!FullSystem) 340 tc->getProcessPtr()->assignThreadContext(tc->contextId()); 341 } 342} 343 344 345int 346BaseCPU::findContext(ThreadContext *tc) 347{ 348 ThreadID size = threadContexts.size(); 349 for (ThreadID tid = 0; tid < size; ++tid) { 350 if (tc == threadContexts[tid]) 351 return tid; 352 } 353 return 0; 354} 355 356void 357BaseCPU::switchOut() 358{ 359 if (profileEvent && profileEvent->scheduled()) 360 deschedule(profileEvent); 361} 362 363void 364BaseCPU::takeOverFrom(BaseCPU *oldCPU) 365{ 366 assert(threadContexts.size() == oldCPU->threadContexts.size()); 367 assert(_cpuId == oldCPU->cpuId()); 368 _pid = oldCPU->getPid(); 369 _taskId = oldCPU->taskId(); 370 371 ThreadID size = threadContexts.size(); 372 for (ThreadID i = 0; i < size; ++i) { 373 ThreadContext *newTC = threadContexts[i]; 374 ThreadContext *oldTC = oldCPU->threadContexts[i]; 375 376 newTC->takeOverFrom(oldTC); 377 378 CpuEvent::replaceThreadContext(oldTC, newTC); 379 380 assert(newTC->contextId() == oldTC->contextId()); 381 assert(newTC->threadId() == oldTC->threadId()); 382 system->replaceThreadContext(newTC, newTC->contextId()); 383 384 /* This code no longer works since the zero register (e.g., 385 * r31 on Alpha) doesn't necessarily contain zero at this 386 * point. 387 if (DTRACE(Context)) 388 ThreadContext::compare(oldTC, newTC); 389 */ 390 391 BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort(); 392 BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort(); 393 BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort(); 394 BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort(); 395 396 // Move over any table walker ports if they exist 397 if (new_itb_port) { 398 assert(!new_itb_port->isConnected()); 399 assert(old_itb_port); 400 assert(old_itb_port->isConnected()); 401 BaseSlavePort &slavePort = old_itb_port->getSlavePort(); 402 old_itb_port->unbind(); 403 new_itb_port->bind(slavePort); 404 } 405 if (new_dtb_port) { 406 assert(!new_dtb_port->isConnected()); 407 assert(old_dtb_port); 408 assert(old_dtb_port->isConnected()); 409 BaseSlavePort &slavePort = old_dtb_port->getSlavePort(); 410 old_dtb_port->unbind(); 411 new_dtb_port->bind(slavePort); 412 } 413 414 // Checker whether or not we have to transfer CheckerCPU 415 // objects over in the switch 416 CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr(); 417 CheckerCPU *newChecker = newTC->getCheckerCpuPtr(); 418 if (oldChecker && newChecker) { 419 BaseMasterPort *old_checker_itb_port = 420 oldChecker->getITBPtr()->getMasterPort(); 421 BaseMasterPort *old_checker_dtb_port = 422 oldChecker->getDTBPtr()->getMasterPort(); 423 BaseMasterPort *new_checker_itb_port = 424 newChecker->getITBPtr()->getMasterPort(); 425 BaseMasterPort *new_checker_dtb_port = 426 newChecker->getDTBPtr()->getMasterPort(); 427 428 // Move over any table walker ports if they exist for checker 429 if (new_checker_itb_port) { 430 assert(!new_checker_itb_port->isConnected()); 431 assert(old_checker_itb_port); 432 assert(old_checker_itb_port->isConnected()); 433 BaseSlavePort &slavePort = 434 old_checker_itb_port->getSlavePort(); 435 old_checker_itb_port->unbind(); 436 new_checker_itb_port->bind(slavePort); 437 } 438 if (new_checker_dtb_port) { 439 assert(!new_checker_dtb_port->isConnected()); 440 assert(old_checker_dtb_port); 441 assert(old_checker_dtb_port->isConnected()); 442 BaseSlavePort &slavePort = 443 old_checker_dtb_port->getSlavePort(); 444 old_checker_dtb_port->unbind(); 445 new_checker_dtb_port->bind(slavePort); 446 } 447 } 448 } 449 450 interrupts = oldCPU->interrupts; 451 interrupts->setCPU(this); 452 oldCPU->interrupts = NULL; 453 454 if (FullSystem) { 455 for (ThreadID i = 0; i < size; ++i) 456 threadContexts[i]->profileClear(); 457 458 if (profileEvent) 459 schedule(profileEvent, curTick()); 460 } 461 462 // All CPUs have an instruction and a data port, and the new CPU's 463 // ports are dangling while the old CPU has its ports connected 464 // already. Unbind the old CPU and then bind the ports of the one 465 // we are switching to. 466 assert(!getInstPort().isConnected()); 467 assert(oldCPU->getInstPort().isConnected()); 468 BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort(); 469 oldCPU->getInstPort().unbind(); 470 getInstPort().bind(inst_peer_port); 471 472 assert(!getDataPort().isConnected()); 473 assert(oldCPU->getDataPort().isConnected()); 474 BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort(); 475 oldCPU->getDataPort().unbind(); 476 getDataPort().bind(data_peer_port); 477} 478 479 480BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval) 481 : cpu(_cpu), interval(_interval) 482{ } 483 484void 485BaseCPU::ProfileEvent::process() 486{ 487 ThreadID size = cpu->threadContexts.size(); 488 for (ThreadID i = 0; i < size; ++i) { 489 ThreadContext *tc = cpu->threadContexts[i]; 490 tc->profileSample(); 491 } 492 493 cpu->schedule(this, curTick() + interval); 494} 495 496void 497BaseCPU::serialize(std::ostream &os) 498{ 499 SERIALIZE_SCALAR(instCnt); 500 501 /* Unlike _pid, _taskId is not serialized, as they are dynamically 502 * assigned unique ids that are only meaningful for the duration of 503 * a specific run. We will need to serialize the entire taskMap in 504 * system. */ 505 SERIALIZE_SCALAR(_pid); 506 507 interrupts->serialize(os); 508} 509 510void 511BaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 512{ 513 UNSERIALIZE_SCALAR(instCnt); 514 UNSERIALIZE_SCALAR(_pid); 515 interrupts->unserialize(cp, section); 516} 517 518void 519BaseCPU::traceFunctionsInternal(Addr pc) 520{ 521 if (!debugSymbolTable) 522 return; 523 524 // if pc enters different function, print new function symbol and 525 // update saved range. Otherwise do nothing. 526 if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 527 string sym_str; 528 bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 529 currentFunctionStart, 530 currentFunctionEnd); 531 532 if (!found) { 533 // no symbol found: use addr as label 534 sym_str = csprintf("0x%x", pc); 535 currentFunctionStart = pc; 536 currentFunctionEnd = pc + 1; 537 } 538 539 ccprintf(*functionTraceStream, " (%d)\n%d: %s", 540 curTick() - functionEntryTick, curTick(), sym_str); 541 functionEntryTick = curTick(); 542 } 543} 544 545bool 546BaseCPU::CpuPort::recvTimingResp(PacketPtr pkt) 547{ 548 panic("BaseCPU doesn't expect recvTiming!\n"); 549 return true; 550} 551 552void 553BaseCPU::CpuPort::recvRetry() 554{ 555 panic("BaseCPU doesn't expect recvRetry!\n"); 556} 557 558void 559BaseCPU::CpuPort::recvFunctionalSnoop(PacketPtr pkt) 560{ 561 // No internal storage to update (in the general case). A CPU with 562 // internal storage, e.g. an LSQ that should be part of the 563 // coherent memory has to check against stored data. 564} 565