base.cc revision 9332
1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * Copyright (c) 2011 Regents of the University of California 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 * Nathan Binkert 43 * Rick Strong 44 */ 45 46#include <iostream> 47#include <sstream> 48#include <string> 49 50#include "arch/tlb.hh" 51#include "base/loader/symtab.hh" 52#include "base/cprintf.hh" 53#include "base/misc.hh" 54#include "base/output.hh" 55#include "base/trace.hh" 56#include "cpu/base.hh" 57#include "cpu/checker/cpu.hh" 58#include "cpu/cpuevent.hh" 59#include "cpu/profile.hh" 60#include "cpu/thread_context.hh" 61#include "debug/SyscallVerbose.hh" 62#include "params/BaseCPU.hh" 63#include "sim/full_system.hh" 64#include "sim/process.hh" 65#include "sim/sim_events.hh" 66#include "sim/sim_exit.hh" 67#include "sim/system.hh" 68 69// Hack 70#include "sim/stat_control.hh" 71 72using namespace std; 73 74vector<BaseCPU *> BaseCPU::cpuList; 75 76// This variable reflects the max number of threads in any CPU. Be 77// careful to only use it once all the CPUs that you care about have 78// been initialized 79int maxThreadsPerCPU = 1; 80 81CPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 82 : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 83 cpu(_cpu), _repeatEvent(true) 84{ 85 if (_interval) 86 cpu->schedule(this, curTick() + _interval); 87} 88 89void 90CPUProgressEvent::process() 91{ 92 Counter temp = cpu->totalOps(); 93#ifndef NDEBUG 94 double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod()); 95 96 DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 97 "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 98 ipc); 99 ipc = 0.0; 100#else 101 cprintf("%lli: %s progress event, total committed:%i, progress insts " 102 "committed: %lli\n", curTick(), cpu->name(), temp, 103 temp - lastNumInst); 104#endif 105 lastNumInst = temp; 106 107 if (_repeatEvent) 108 cpu->schedule(this, curTick() + _interval); 109} 110 111const char * 112CPUProgressEvent::description() const 113{ 114 return "CPU Progress"; 115} 116 117BaseCPU::BaseCPU(Params *p, bool is_checker) 118 : MemObject(p), instCnt(0), _cpuId(p->cpu_id), 119 _instMasterId(p->system->getMasterId(name() + ".inst")), 120 _dataMasterId(p->system->getMasterId(name() + ".data")), 121 _taskId(ContextSwitchTaskId::Unknown), _pid(Request::invldPid), 122 interrupts(p->interrupts), profileEvent(NULL), 123 numThreads(p->numThreads), system(p->system) 124{ 125 // if Python did not provide a valid ID, do it here 126 if (_cpuId == -1 ) { 127 _cpuId = cpuList.size(); 128 } 129 130 // add self to global list of CPUs 131 cpuList.push_back(this); 132 133 DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId); 134 135 if (numThreads > maxThreadsPerCPU) 136 maxThreadsPerCPU = numThreads; 137 138 // allocate per-thread instruction-based event queues 139 comInstEventQueue = new EventQueue *[numThreads]; 140 for (ThreadID tid = 0; tid < numThreads; ++tid) 141 comInstEventQueue[tid] = 142 new EventQueue("instruction-based event queue"); 143 144 // 145 // set up instruction-count-based termination events, if any 146 // 147 if (p->max_insts_any_thread != 0) { 148 const char *cause = "a thread reached the max instruction count"; 149 for (ThreadID tid = 0; tid < numThreads; ++tid) { 150 Event *event = new SimLoopExitEvent(cause, 0); 151 comInstEventQueue[tid]->schedule(event, p->max_insts_any_thread); 152 } 153 } 154 155 if (p->max_insts_all_threads != 0) { 156 const char *cause = "all threads reached the max instruction count"; 157 158 // allocate & initialize shared downcounter: each event will 159 // decrement this when triggered; simulation will terminate 160 // when counter reaches 0 161 int *counter = new int; 162 *counter = numThreads; 163 for (ThreadID tid = 0; tid < numThreads; ++tid) { 164 Event *event = new CountedExitEvent(cause, *counter); 165 comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 166 } 167 } 168 169 // allocate per-thread load-based event queues 170 comLoadEventQueue = new EventQueue *[numThreads]; 171 for (ThreadID tid = 0; tid < numThreads; ++tid) 172 comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 173 174 // 175 // set up instruction-count-based termination events, if any 176 // 177 if (p->max_loads_any_thread != 0) { 178 const char *cause = "a thread reached the max load count"; 179 for (ThreadID tid = 0; tid < numThreads; ++tid) { 180 Event *event = new SimLoopExitEvent(cause, 0); 181 comLoadEventQueue[tid]->schedule(event, p->max_loads_any_thread); 182 } 183 } 184 185 if (p->max_loads_all_threads != 0) { 186 const char *cause = "all threads reached the max load count"; 187 // allocate & initialize shared downcounter: each event will 188 // decrement this when triggered; simulation will terminate 189 // when counter reaches 0 190 int *counter = new int; 191 *counter = numThreads; 192 for (ThreadID tid = 0; tid < numThreads; ++tid) { 193 Event *event = new CountedExitEvent(cause, *counter); 194 comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 195 } 196 } 197 198 functionTracingEnabled = false; 199 if (p->function_trace) { 200 const string fname = csprintf("ftrace.%s", name()); 201 functionTraceStream = simout.find(fname); 202 if (!functionTraceStream) 203 functionTraceStream = simout.create(fname); 204 205 currentFunctionStart = currentFunctionEnd = 0; 206 functionEntryTick = p->function_trace_start; 207 208 if (p->function_trace_start == 0) { 209 functionTracingEnabled = true; 210 } else { 211 typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap; 212 Event *event = new wrap(this, true); 213 schedule(event, p->function_trace_start); 214 } 215 } 216 217 // The interrupts should always be present unless this CPU is 218 // switched in later or in case it is a checker CPU 219 if (!params()->defer_registration && !is_checker) { 220 if (interrupts) { 221 interrupts->setCPU(this); 222 } else { 223 fatal("CPU %s has no interrupt controller.\n" 224 "Ensure createInterruptController() is called.\n", name()); 225 } 226 } 227 228 if (FullSystem) { 229 if (params()->profile) 230 profileEvent = new ProfileEvent(this, params()->profile); 231 } 232 tracer = params()->tracer; 233} 234 235void 236BaseCPU::enableFunctionTrace() 237{ 238 functionTracingEnabled = true; 239} 240 241BaseCPU::~BaseCPU() 242{ 243 delete profileEvent; 244 delete[] comLoadEventQueue; 245 delete[] comInstEventQueue; 246} 247 248void 249BaseCPU::init() 250{ 251 if (!params()->defer_registration) 252 registerThreadContexts(); 253} 254 255void 256BaseCPU::startup() 257{ 258 if (FullSystem) { 259 if (!params()->defer_registration && profileEvent) 260 schedule(profileEvent, curTick()); 261 } 262 263 if (params()->progress_interval) { 264 new CPUProgressEvent(this, params()->progress_interval); 265 } 266} 267 268 269void 270BaseCPU::regStats() 271{ 272 using namespace Stats; 273 274 numCycles 275 .name(name() + ".numCycles") 276 .desc("number of cpu cycles simulated") 277 ; 278 279 numWorkItemsStarted 280 .name(name() + ".numWorkItemsStarted") 281 .desc("number of work items this cpu started") 282 ; 283 284 numWorkItemsCompleted 285 .name(name() + ".numWorkItemsCompleted") 286 .desc("number of work items this cpu completed") 287 ; 288 289 int size = threadContexts.size(); 290 if (size > 1) { 291 for (int i = 0; i < size; ++i) { 292 stringstream namestr; 293 ccprintf(namestr, "%s.ctx%d", name(), i); 294 threadContexts[i]->regStats(namestr.str()); 295 } 296 } else if (size == 1) 297 threadContexts[0]->regStats(name()); 298} 299 300BaseMasterPort & 301BaseCPU::getMasterPort(const string &if_name, PortID idx) 302{ 303 // Get the right port based on name. This applies to all the 304 // subclasses of the base CPU and relies on their implementation 305 // of getDataPort and getInstPort. In all cases there methods 306 // return a CpuPort pointer. 307 if (if_name == "dcache_port") 308 return getDataPort(); 309 else if (if_name == "icache_port") 310 return getInstPort(); 311 else 312 return MemObject::getMasterPort(if_name, idx); 313} 314 315void 316BaseCPU::registerThreadContexts() 317{ 318 ThreadID size = threadContexts.size(); 319 for (ThreadID tid = 0; tid < size; ++tid) { 320 ThreadContext *tc = threadContexts[tid]; 321 322 /** This is so that contextId and cpuId match where there is a 323 * 1cpu:1context relationship. Otherwise, the order of registration 324 * could affect the assignment and cpu 1 could have context id 3, for 325 * example. We may even want to do something like this for SMT so that 326 * cpu 0 has the lowest thread contexts and cpu N has the highest, but 327 * I'll just do this for now 328 */ 329 if (numThreads == 1) 330 tc->setContextId(system->registerThreadContext(tc, _cpuId)); 331 else 332 tc->setContextId(system->registerThreadContext(tc)); 333 334 if (!FullSystem) 335 tc->getProcessPtr()->assignThreadContext(tc->contextId()); 336 } 337} 338 339 340int 341BaseCPU::findContext(ThreadContext *tc) 342{ 343 ThreadID size = threadContexts.size(); 344 for (ThreadID tid = 0; tid < size; ++tid) { 345 if (tc == threadContexts[tid]) 346 return tid; 347 } 348 return 0; 349} 350 351void 352BaseCPU::switchOut() 353{ 354 if (profileEvent && profileEvent->scheduled()) 355 deschedule(profileEvent); 356} 357 358void 359BaseCPU::takeOverFrom(BaseCPU *oldCPU) 360{ 361 assert(threadContexts.size() == oldCPU->threadContexts.size()); 362 assert(_cpuId == oldCPU->cpuId()); 363 _pid = oldCPU->getPid(); 364 _taskId = oldCPU->taskId(); 365 366 ThreadID size = threadContexts.size(); 367 for (ThreadID i = 0; i < size; ++i) { 368 ThreadContext *newTC = threadContexts[i]; 369 ThreadContext *oldTC = oldCPU->threadContexts[i]; 370 371 newTC->takeOverFrom(oldTC); 372 373 CpuEvent::replaceThreadContext(oldTC, newTC); 374 375 assert(newTC->contextId() == oldTC->contextId()); 376 assert(newTC->threadId() == oldTC->threadId()); 377 system->replaceThreadContext(newTC, newTC->contextId()); 378 379 /* This code no longer works since the zero register (e.g., 380 * r31 on Alpha) doesn't necessarily contain zero at this 381 * point. 382 if (DTRACE(Context)) 383 ThreadContext::compare(oldTC, newTC); 384 */ 385 386 BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort(); 387 BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort(); 388 BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort(); 389 BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort(); 390 391 // Move over any table walker ports if they exist 392 if (new_itb_port) { 393 assert(!new_itb_port->isConnected()); 394 assert(old_itb_port); 395 assert(old_itb_port->isConnected()); 396 BaseSlavePort &slavePort = old_itb_port->getSlavePort(); 397 old_itb_port->unbind(); 398 new_itb_port->bind(slavePort); 399 } 400 if (new_dtb_port) { 401 assert(!new_dtb_port->isConnected()); 402 assert(old_dtb_port); 403 assert(old_dtb_port->isConnected()); 404 BaseSlavePort &slavePort = old_dtb_port->getSlavePort(); 405 old_dtb_port->unbind(); 406 new_dtb_port->bind(slavePort); 407 } 408 409 // Checker whether or not we have to transfer CheckerCPU 410 // objects over in the switch 411 CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr(); 412 CheckerCPU *newChecker = newTC->getCheckerCpuPtr(); 413 if (oldChecker && newChecker) { 414 BaseMasterPort *old_checker_itb_port = 415 oldChecker->getITBPtr()->getMasterPort(); 416 BaseMasterPort *old_checker_dtb_port = 417 oldChecker->getDTBPtr()->getMasterPort(); 418 BaseMasterPort *new_checker_itb_port = 419 newChecker->getITBPtr()->getMasterPort(); 420 BaseMasterPort *new_checker_dtb_port = 421 newChecker->getDTBPtr()->getMasterPort(); 422 423 // Move over any table walker ports if they exist for checker 424 if (new_checker_itb_port) { 425 assert(!new_checker_itb_port->isConnected()); 426 assert(old_checker_itb_port); 427 assert(old_checker_itb_port->isConnected()); 428 BaseSlavePort &slavePort = 429 old_checker_itb_port->getSlavePort(); 430 old_checker_itb_port->unbind(); 431 new_checker_itb_port->bind(slavePort); 432 } 433 if (new_checker_dtb_port) { 434 assert(!new_checker_dtb_port->isConnected()); 435 assert(old_checker_dtb_port); 436 assert(old_checker_dtb_port->isConnected()); 437 BaseSlavePort &slavePort = 438 old_checker_dtb_port->getSlavePort(); 439 old_checker_dtb_port->unbind(); 440 new_checker_dtb_port->bind(slavePort); 441 } 442 } 443 } 444 445 interrupts = oldCPU->interrupts; 446 interrupts->setCPU(this); 447 oldCPU->interrupts = NULL; 448 449 if (FullSystem) { 450 for (ThreadID i = 0; i < size; ++i) 451 threadContexts[i]->profileClear(); 452 453 if (profileEvent) 454 schedule(profileEvent, curTick()); 455 } 456 457 // All CPUs have an instruction and a data port, and the new CPU's 458 // ports are dangling while the old CPU has its ports connected 459 // already. Unbind the old CPU and then bind the ports of the one 460 // we are switching to. 461 assert(!getInstPort().isConnected()); 462 assert(oldCPU->getInstPort().isConnected()); 463 BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort(); 464 oldCPU->getInstPort().unbind(); 465 getInstPort().bind(inst_peer_port); 466 467 assert(!getDataPort().isConnected()); 468 assert(oldCPU->getDataPort().isConnected()); 469 BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort(); 470 oldCPU->getDataPort().unbind(); 471 getDataPort().bind(data_peer_port); 472} 473 474 475BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval) 476 : cpu(_cpu), interval(_interval) 477{ } 478 479void 480BaseCPU::ProfileEvent::process() 481{ 482 ThreadID size = cpu->threadContexts.size(); 483 for (ThreadID i = 0; i < size; ++i) { 484 ThreadContext *tc = cpu->threadContexts[i]; 485 tc->profileSample(); 486 } 487 488 cpu->schedule(this, curTick() + interval); 489} 490 491void 492BaseCPU::serialize(std::ostream &os) 493{ 494 SERIALIZE_SCALAR(instCnt); 495 496 /* Unlike _pid, _taskId is not serialized, as they are dynamically 497 * assigned unique ids that are only meaningful for the duration of 498 * a specific run. We will need to serialize the entire taskMap in 499 * system. */ 500 SERIALIZE_SCALAR(_pid); 501 502 interrupts->serialize(os); 503} 504 505void 506BaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 507{ 508 UNSERIALIZE_SCALAR(instCnt); 509 UNSERIALIZE_SCALAR(_pid); 510 interrupts->unserialize(cp, section); 511} 512 513void 514BaseCPU::traceFunctionsInternal(Addr pc) 515{ 516 if (!debugSymbolTable) 517 return; 518 519 // if pc enters different function, print new function symbol and 520 // update saved range. Otherwise do nothing. 521 if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 522 string sym_str; 523 bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 524 currentFunctionStart, 525 currentFunctionEnd); 526 527 if (!found) { 528 // no symbol found: use addr as label 529 sym_str = csprintf("0x%x", pc); 530 currentFunctionStart = pc; 531 currentFunctionEnd = pc + 1; 532 } 533 534 ccprintf(*functionTraceStream, " (%d)\n%d: %s", 535 curTick() - functionEntryTick, curTick(), sym_str); 536 functionEntryTick = curTick(); 537 } 538} 539 540bool 541BaseCPU::CpuPort::recvTimingResp(PacketPtr pkt) 542{ 543 panic("BaseCPU doesn't expect recvTiming!\n"); 544 return true; 545} 546 547void 548BaseCPU::CpuPort::recvRetry() 549{ 550 panic("BaseCPU doesn't expect recvRetry!\n"); 551} 552 553void 554BaseCPU::CpuPort::recvFunctionalSnoop(PacketPtr pkt) 555{ 556 // No internal storage to update (in the general case). A CPU with 557 // internal storage, e.g. an LSQ that should be part of the 558 // coherent memory has to check against stored data. 559} 560