base.cc revision 8733:64a7bf8fa56c
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * Copyright (c) 2011 Regents of the University of California 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 * Nathan Binkert 43 * Rick Strong 44 */ 45 46#include <iostream> 47#include <sstream> 48#include <string> 49 50#include "arch/tlb.hh" 51#include "base/loader/symtab.hh" 52#include "base/cprintf.hh" 53#include "base/misc.hh" 54#include "base/output.hh" 55#include "base/trace.hh" 56#include "config/use_checker.hh" 57#include "cpu/base.hh" 58#include "cpu/cpuevent.hh" 59#include "cpu/profile.hh" 60#include "cpu/thread_context.hh" 61#include "debug/SyscallVerbose.hh" 62#include "params/BaseCPU.hh" 63#include "sim/process.hh" 64#include "sim/sim_events.hh" 65#include "sim/sim_exit.hh" 66#include "sim/system.hh" 67 68#if USE_CHECKER 69#include "cpu/checker/cpu.hh" 70#endif 71 72// Hack 73#include "sim/stat_control.hh" 74 75using namespace std; 76 77vector<BaseCPU *> BaseCPU::cpuList; 78 79// This variable reflects the max number of threads in any CPU. Be 80// careful to only use it once all the CPUs that you care about have 81// been initialized 82int maxThreadsPerCPU = 1; 83 84CPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 85 : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 86 cpu(_cpu), _repeatEvent(true) 87{ 88 if (_interval) 89 cpu->schedule(this, curTick() + _interval); 90} 91 92void 93CPUProgressEvent::process() 94{ 95 Counter temp = cpu->totalInstructions(); 96#ifndef NDEBUG 97 double ipc = double(temp - lastNumInst) / (_interval / cpu->ticks(1)); 98 99 DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 100 "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 101 ipc); 102 ipc = 0.0; 103#else 104 cprintf("%lli: %s progress event, total committed:%i, progress insts " 105 "committed: %lli\n", curTick(), cpu->name(), temp, 106 temp - lastNumInst); 107#endif 108 lastNumInst = temp; 109 110 if (_repeatEvent) 111 cpu->schedule(this, curTick() + _interval); 112} 113 114const char * 115CPUProgressEvent::description() const 116{ 117 return "CPU Progress"; 118} 119 120#if FULL_SYSTEM 121BaseCPU::BaseCPU(Params *p) 122 : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id), 123 interrupts(p->interrupts), 124 numThreads(p->numThreads), system(p->system), 125 phase(p->phase) 126#else 127BaseCPU::BaseCPU(Params *p) 128 : MemObject(p), clock(p->clock), _cpuId(p->cpu_id), 129 numThreads(p->numThreads), system(p->system), 130 phase(p->phase) 131#endif 132{ 133// currentTick = curTick(); 134 135 // if Python did not provide a valid ID, do it here 136 if (_cpuId == -1 ) { 137 _cpuId = cpuList.size(); 138 } 139 140 // add self to global list of CPUs 141 cpuList.push_back(this); 142 143 DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId); 144 145 if (numThreads > maxThreadsPerCPU) 146 maxThreadsPerCPU = numThreads; 147 148 // allocate per-thread instruction-based event queues 149 comInstEventQueue = new EventQueue *[numThreads]; 150 for (ThreadID tid = 0; tid < numThreads; ++tid) 151 comInstEventQueue[tid] = 152 new EventQueue("instruction-based event queue"); 153 154 // 155 // set up instruction-count-based termination events, if any 156 // 157 if (p->max_insts_any_thread != 0) { 158 const char *cause = "a thread reached the max instruction count"; 159 for (ThreadID tid = 0; tid < numThreads; ++tid) { 160 Event *event = new SimLoopExitEvent(cause, 0); 161 comInstEventQueue[tid]->schedule(event, p->max_insts_any_thread); 162 } 163 } 164 165 if (p->max_insts_all_threads != 0) { 166 const char *cause = "all threads reached the max instruction count"; 167 168 // allocate & initialize shared downcounter: each event will 169 // decrement this when triggered; simulation will terminate 170 // when counter reaches 0 171 int *counter = new int; 172 *counter = numThreads; 173 for (ThreadID tid = 0; tid < numThreads; ++tid) { 174 Event *event = new CountedExitEvent(cause, *counter); 175 comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 176 } 177 } 178 179 // allocate per-thread load-based event queues 180 comLoadEventQueue = new EventQueue *[numThreads]; 181 for (ThreadID tid = 0; tid < numThreads; ++tid) 182 comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 183 184 // 185 // set up instruction-count-based termination events, if any 186 // 187 if (p->max_loads_any_thread != 0) { 188 const char *cause = "a thread reached the max load count"; 189 for (ThreadID tid = 0; tid < numThreads; ++tid) { 190 Event *event = new SimLoopExitEvent(cause, 0); 191 comLoadEventQueue[tid]->schedule(event, p->max_loads_any_thread); 192 } 193 } 194 195 if (p->max_loads_all_threads != 0) { 196 const char *cause = "all threads reached the max load count"; 197 // allocate & initialize shared downcounter: each event will 198 // decrement this when triggered; simulation will terminate 199 // when counter reaches 0 200 int *counter = new int; 201 *counter = numThreads; 202 for (ThreadID tid = 0; tid < numThreads; ++tid) { 203 Event *event = new CountedExitEvent(cause, *counter); 204 comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 205 } 206 } 207 208 functionTracingEnabled = false; 209 if (p->function_trace) { 210 const string fname = csprintf("ftrace.%s", name()); 211 functionTraceStream = simout.find(fname); 212 if (!functionTraceStream) 213 functionTraceStream = simout.create(fname); 214 215 currentFunctionStart = currentFunctionEnd = 0; 216 functionEntryTick = p->function_trace_start; 217 218 if (p->function_trace_start == 0) { 219 functionTracingEnabled = true; 220 } else { 221 typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap; 222 Event *event = new wrap(this, true); 223 schedule(event, p->function_trace_start); 224 } 225 } 226#if FULL_SYSTEM 227 // Check if CPU model has interrupts connected. The CheckerCPU 228 // cannot take interrupts directly for example. 229 if (interrupts) 230 interrupts->setCPU(this); 231 232 profileEvent = NULL; 233 if (params()->profile) 234 profileEvent = new ProfileEvent(this, params()->profile); 235#endif 236 tracer = params()->tracer; 237} 238 239void 240BaseCPU::enableFunctionTrace() 241{ 242 functionTracingEnabled = true; 243} 244 245BaseCPU::~BaseCPU() 246{ 247} 248 249void 250BaseCPU::init() 251{ 252 if (!params()->defer_registration) 253 registerThreadContexts(); 254} 255 256void 257BaseCPU::startup() 258{ 259#if FULL_SYSTEM 260 if (!params()->defer_registration && profileEvent) 261 schedule(profileEvent, curTick()); 262#endif 263 264 if (params()->progress_interval) { 265 Tick num_ticks = ticks(params()->progress_interval); 266 267 new CPUProgressEvent(this, num_ticks); 268 } 269} 270 271 272void 273BaseCPU::regStats() 274{ 275 using namespace Stats; 276 277 numCycles 278 .name(name() + ".numCycles") 279 .desc("number of cpu cycles simulated") 280 ; 281 282 numWorkItemsStarted 283 .name(name() + ".numWorkItemsStarted") 284 .desc("number of work items this cpu started") 285 ; 286 287 numWorkItemsCompleted 288 .name(name() + ".numWorkItemsCompleted") 289 .desc("number of work items this cpu completed") 290 ; 291 292 int size = threadContexts.size(); 293 if (size > 1) { 294 for (int i = 0; i < size; ++i) { 295 stringstream namestr; 296 ccprintf(namestr, "%s.ctx%d", name(), i); 297 threadContexts[i]->regStats(namestr.str()); 298 } 299 } else if (size == 1) 300 threadContexts[0]->regStats(name()); 301 302#if FULL_SYSTEM 303#endif 304} 305 306Tick 307BaseCPU::nextCycle() 308{ 309 Tick next_tick = curTick() - phase + clock - 1; 310 next_tick -= (next_tick % clock); 311 next_tick += phase; 312 return next_tick; 313} 314 315Tick 316BaseCPU::nextCycle(Tick begin_tick) 317{ 318 Tick next_tick = begin_tick; 319 if (next_tick % clock != 0) 320 next_tick = next_tick - (next_tick % clock) + clock; 321 next_tick += phase; 322 323 assert(next_tick >= curTick()); 324 return next_tick; 325} 326 327void 328BaseCPU::registerThreadContexts() 329{ 330 ThreadID size = threadContexts.size(); 331 for (ThreadID tid = 0; tid < size; ++tid) { 332 ThreadContext *tc = threadContexts[tid]; 333 334 /** This is so that contextId and cpuId match where there is a 335 * 1cpu:1context relationship. Otherwise, the order of registration 336 * could affect the assignment and cpu 1 could have context id 3, for 337 * example. We may even want to do something like this for SMT so that 338 * cpu 0 has the lowest thread contexts and cpu N has the highest, but 339 * I'll just do this for now 340 */ 341 if (numThreads == 1) 342 tc->setContextId(system->registerThreadContext(tc, _cpuId)); 343 else 344 tc->setContextId(system->registerThreadContext(tc)); 345#if !FULL_SYSTEM 346 tc->getProcessPtr()->assignThreadContext(tc->contextId()); 347#endif 348 } 349} 350 351 352int 353BaseCPU::findContext(ThreadContext *tc) 354{ 355 ThreadID size = threadContexts.size(); 356 for (ThreadID tid = 0; tid < size; ++tid) { 357 if (tc == threadContexts[tid]) 358 return tid; 359 } 360 return 0; 361} 362 363void 364BaseCPU::switchOut() 365{ 366// panic("This CPU doesn't support sampling!"); 367#if FULL_SYSTEM 368 if (profileEvent && profileEvent->scheduled()) 369 deschedule(profileEvent); 370#endif 371} 372 373void 374BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc) 375{ 376 assert(threadContexts.size() == oldCPU->threadContexts.size()); 377 378 _cpuId = oldCPU->cpuId(); 379 380 ThreadID size = threadContexts.size(); 381 for (ThreadID i = 0; i < size; ++i) { 382 ThreadContext *newTC = threadContexts[i]; 383 ThreadContext *oldTC = oldCPU->threadContexts[i]; 384 385 newTC->takeOverFrom(oldTC); 386 387 CpuEvent::replaceThreadContext(oldTC, newTC); 388 389 assert(newTC->contextId() == oldTC->contextId()); 390 assert(newTC->threadId() == oldTC->threadId()); 391 system->replaceThreadContext(newTC, newTC->contextId()); 392 393 /* This code no longer works since the zero register (e.g., 394 * r31 on Alpha) doesn't necessarily contain zero at this 395 * point. 396 if (DTRACE(Context)) 397 ThreadContext::compare(oldTC, newTC); 398 */ 399 400 Port *old_itb_port, *old_dtb_port, *new_itb_port, *new_dtb_port; 401 old_itb_port = oldTC->getITBPtr()->getPort(); 402 old_dtb_port = oldTC->getDTBPtr()->getPort(); 403 new_itb_port = newTC->getITBPtr()->getPort(); 404 new_dtb_port = newTC->getDTBPtr()->getPort(); 405 406 // Move over any table walker ports if they exist 407 if (new_itb_port && !new_itb_port->isConnected()) { 408 assert(old_itb_port); 409 Port *peer = old_itb_port->getPeer();; 410 new_itb_port->setPeer(peer); 411 peer->setPeer(new_itb_port); 412 } 413 if (new_dtb_port && !new_dtb_port->isConnected()) { 414 assert(old_dtb_port); 415 Port *peer = old_dtb_port->getPeer();; 416 new_dtb_port->setPeer(peer); 417 peer->setPeer(new_dtb_port); 418 } 419 420#if USE_CHECKER 421 Port *old_checker_itb_port, *old_checker_dtb_port; 422 Port *new_checker_itb_port, *new_checker_dtb_port; 423 424 CheckerCPU *oldChecker = 425 dynamic_cast<CheckerCPU*>(oldTC->getCheckerCpuPtr()); 426 CheckerCPU *newChecker = 427 dynamic_cast<CheckerCPU*>(newTC->getCheckerCpuPtr()); 428 old_checker_itb_port = oldChecker->getITBPtr()->getPort(); 429 old_checker_dtb_port = oldChecker->getDTBPtr()->getPort(); 430 new_checker_itb_port = newChecker->getITBPtr()->getPort(); 431 new_checker_dtb_port = newChecker->getDTBPtr()->getPort(); 432 433 // Move over any table walker ports if they exist for checker 434 if (new_checker_itb_port && !new_checker_itb_port->isConnected()) { 435 assert(old_checker_itb_port); 436 Port *peer = old_checker_itb_port->getPeer();; 437 new_checker_itb_port->setPeer(peer); 438 peer->setPeer(new_checker_itb_port); 439 } 440 if (new_checker_dtb_port && !new_checker_dtb_port->isConnected()) { 441 assert(old_checker_dtb_port); 442 Port *peer = old_checker_dtb_port->getPeer();; 443 new_checker_dtb_port->setPeer(peer); 444 peer->setPeer(new_checker_dtb_port); 445 } 446#endif 447 448 } 449 450#if FULL_SYSTEM 451 interrupts = oldCPU->interrupts; 452 interrupts->setCPU(this); 453 454 for (ThreadID i = 0; i < size; ++i) 455 threadContexts[i]->profileClear(); 456 457 if (profileEvent) 458 schedule(profileEvent, curTick()); 459#endif 460 461 // Connect new CPU to old CPU's memory only if new CPU isn't 462 // connected to anything. Also connect old CPU's memory to new 463 // CPU. 464 if (!ic->isConnected()) { 465 Port *peer = oldCPU->getPort("icache_port")->getPeer(); 466 ic->setPeer(peer); 467 peer->setPeer(ic); 468 } 469 470 if (!dc->isConnected()) { 471 Port *peer = oldCPU->getPort("dcache_port")->getPeer(); 472 dc->setPeer(peer); 473 peer->setPeer(dc); 474 } 475} 476 477 478#if FULL_SYSTEM 479BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval) 480 : cpu(_cpu), interval(_interval) 481{ } 482 483void 484BaseCPU::ProfileEvent::process() 485{ 486 ThreadID size = cpu->threadContexts.size(); 487 for (ThreadID i = 0; i < size; ++i) { 488 ThreadContext *tc = cpu->threadContexts[i]; 489 tc->profileSample(); 490 } 491 492 cpu->schedule(this, curTick() + interval); 493} 494 495void 496BaseCPU::serialize(std::ostream &os) 497{ 498 SERIALIZE_SCALAR(instCnt); 499 interrupts->serialize(os); 500} 501 502void 503BaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 504{ 505 UNSERIALIZE_SCALAR(instCnt); 506 interrupts->unserialize(cp, section); 507} 508 509#endif // FULL_SYSTEM 510 511void 512BaseCPU::traceFunctionsInternal(Addr pc) 513{ 514 if (!debugSymbolTable) 515 return; 516 517 // if pc enters different function, print new function symbol and 518 // update saved range. Otherwise do nothing. 519 if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 520 string sym_str; 521 bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 522 currentFunctionStart, 523 currentFunctionEnd); 524 525 if (!found) { 526 // no symbol found: use addr as label 527 sym_str = csprintf("0x%x", pc); 528 currentFunctionStart = pc; 529 currentFunctionEnd = pc + 1; 530 } 531 532 ccprintf(*functionTraceStream, " (%d)\n%d: %s", 533 curTick() - functionEntryTick, curTick(), sym_str); 534 functionEntryTick = curTick(); 535 } 536} 537 538bool 539BaseCPU::CpuPort::recvTiming(PacketPtr pkt) 540{ 541 panic("BaseCPU doesn't expect recvTiming callback!"); 542 return true; 543} 544 545void 546BaseCPU::CpuPort::recvRetry() 547{ 548 panic("BaseCPU doesn't expect recvRetry callback!"); 549} 550 551Tick 552BaseCPU::CpuPort::recvAtomic(PacketPtr pkt) 553{ 554 panic("BaseCPU doesn't expect recvAtomic callback!"); 555 return curTick(); 556} 557 558void 559BaseCPU::CpuPort::recvFunctional(PacketPtr pkt) 560{ 561 // No internal storage to update (in the general case). In the 562 // long term this should never be called, but that assumed a split 563 // into master/slave and request/response. 564} 565 566void 567BaseCPU::CpuPort::recvRangeChange() 568{ 569} 570