base.cc revision 3661:efc80a01aeb6
16019Shines@cs.fsu.edu/* 214128Sgiacomo.travaglini@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 37093Sgblack@eecs.umich.edu * All rights reserved. 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 67093Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 77093Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 87093Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 97093Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 107093Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 117093Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 127093Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 137093Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 146019Shines@cs.fsu.edu * this software without specific prior written permission. 156019Shines@cs.fsu.edu * 166019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * Authors: Steve Reinhardt 296019Shines@cs.fsu.edu * Nathan Binkert 306019Shines@cs.fsu.edu */ 316019Shines@cs.fsu.edu 326019Shines@cs.fsu.edu#include <iostream> 336019Shines@cs.fsu.edu#include <string> 346019Shines@cs.fsu.edu#include <sstream> 356019Shines@cs.fsu.edu 366019Shines@cs.fsu.edu#include "base/cprintf.hh" 376019Shines@cs.fsu.edu#include "base/loader/symtab.hh" 386019Shines@cs.fsu.edu#include "base/misc.hh" 396019Shines@cs.fsu.edu#include "base/output.hh" 406019Shines@cs.fsu.edu#include "cpu/base.hh" 416735Sgblack@eecs.umich.edu#include "cpu/cpuevent.hh" 426735Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 4310037SARM gem5 Developers#include "cpu/profile.hh" 4410037SARM gem5 Developers#include "sim/sim_exit.hh" 456019Shines@cs.fsu.edu#include "sim/param.hh" 466019Shines@cs.fsu.edu#include "sim/process.hh" 476019Shines@cs.fsu.edu#include "sim/sim_events.hh" 4811793Sbrandon.potter@amd.com#include "sim/system.hh" 4911793Sbrandon.potter@amd.com 5010037SARM gem5 Developers#include "base/trace.hh" 5110037SARM gem5 Developers 5210037SARM gem5 Developers// Hack 538229Snate@binkert.org#include "sim/stat_control.hh" 548229Snate@binkert.org 556019Shines@cs.fsu.eduusing namespace std; 568232Snate@binkert.org 578782Sgblack@eecs.umich.eduvector<BaseCPU *> BaseCPU::cpuList; 586019Shines@cs.fsu.edu 596019Shines@cs.fsu.edu// This variable reflects the max number of threads in any CPU. Be 606019Shines@cs.fsu.edu// careful to only use it once all the CPUs that you care about have 616019Shines@cs.fsu.edu// been initialized 6210037SARM gem5 Developersint maxThreadsPerCPU = 1; 6310037SARM gem5 Developers 6410037SARM gem5 DevelopersCPUProgressEvent::CPUProgressEvent(EventQueue *q, Tick ival, 6510037SARM gem5 Developers BaseCPU *_cpu) 6610037SARM gem5 Developers : Event(q, Event::Stat_Event_Pri), interval(ival), 6710037SARM gem5 Developers lastNumInst(0), cpu(_cpu) 6810037SARM gem5 Developers{ 6910037SARM gem5 Developers if (interval) 7010037SARM gem5 Developers schedule(curTick + interval); 7110037SARM gem5 Developers} 7210037SARM gem5 Developers 7310037SARM gem5 Developersvoid 7410037SARM gem5 DevelopersCPUProgressEvent::process() 7510037SARM gem5 Developers{ 7610037SARM gem5 Developers Counter temp = cpu->totalInstructions(); 7710037SARM gem5 Developers#ifndef NDEBUG 7810037SARM gem5 Developers double ipc = double(temp - lastNumInst) / (interval / cpu->cycles(1)); 7910037SARM gem5 Developers 8010037SARM gem5 Developers DPRINTFN("%s progress event, instructions committed: %lli, IPC: %0.8d\n", 8110037SARM gem5 Developers cpu->name(), temp - lastNumInst, ipc); 8210037SARM gem5 Developers ipc = 0.0; 8310037SARM gem5 Developers#else 8410037SARM gem5 Developers cprintf("%lli: %s progress event, instructions committed: %lli\n", 8510037SARM gem5 Developers curTick, cpu->name(), temp - lastNumInst); 8610037SARM gem5 Developers#endif 8710037SARM gem5 Developers lastNumInst = temp; 8810037SARM gem5 Developers schedule(curTick + interval); 8910037SARM gem5 Developers} 9010037SARM gem5 Developers 9110037SARM gem5 Developersconst char * 9210037SARM gem5 DevelopersCPUProgressEvent::description() 9310037SARM gem5 Developers{ 9410037SARM gem5 Developers return "CPU Progress event"; 9510037SARM gem5 Developers} 9610037SARM gem5 Developers 9710037SARM gem5 Developers#if FULL_SYSTEM 9810037SARM gem5 DevelopersBaseCPU::BaseCPU(Params *p) 9910037SARM gem5 Developers : MemObject(p->name), clock(p->clock), checkInterrupts(true), 10010037SARM gem5 Developers params(p), number_of_threads(p->numberOfThreads), system(p->system), 10110037SARM gem5 Developers phase(p->phase) 1026019Shines@cs.fsu.edu#else 10310037SARM gem5 DevelopersBaseCPU::BaseCPU(Params *p) 10410037SARM gem5 Developers : MemObject(p->name), clock(p->clock), params(p), 10510037SARM gem5 Developers number_of_threads(p->numberOfThreads), system(p->system), 1066019Shines@cs.fsu.edu phase(p->phase) 10710037SARM gem5 Developers#endif 10810037SARM gem5 Developers{ 10910037SARM gem5 Developers// currentTick = curTick; 11010037SARM gem5 Developers DPRINTF(FullCPU, "BaseCPU: Creating object, mem address %#x.\n", this); 11110037SARM gem5 Developers 11210037SARM gem5 Developers // add self to global list of CPUs 11310037SARM gem5 Developers cpuList.push_back(this); 11410037SARM gem5 Developers 11510037SARM gem5 Developers DPRINTF(FullCPU, "BaseCPU: CPU added to cpuList, mem address %#x.\n", 11610037SARM gem5 Developers this); 11710037SARM gem5 Developers 11810037SARM gem5 Developers if (number_of_threads > maxThreadsPerCPU) 11910037SARM gem5 Developers maxThreadsPerCPU = number_of_threads; 12010037SARM gem5 Developers 12110037SARM gem5 Developers // allocate per-thread instruction-based event queues 12210037SARM gem5 Developers comInstEventQueue = new EventQueue *[number_of_threads]; 12310037SARM gem5 Developers for (int i = 0; i < number_of_threads; ++i) 12410037SARM gem5 Developers comInstEventQueue[i] = new EventQueue("instruction-based event queue"); 12510037SARM gem5 Developers 12610037SARM gem5 Developers // 12710037SARM gem5 Developers // set up instruction-count-based termination events, if any 12810037SARM gem5 Developers // 12910037SARM gem5 Developers if (p->max_insts_any_thread != 0) 13010037SARM gem5 Developers for (int i = 0; i < number_of_threads; ++i) 13110037SARM gem5 Developers schedExitSimLoop("a thread reached the max instruction count", 13210037SARM gem5 Developers p->max_insts_any_thread, 0, 13310037SARM gem5 Developers comInstEventQueue[i]); 13410037SARM gem5 Developers 13510037SARM gem5 Developers if (p->max_insts_all_threads != 0) { 13610037SARM gem5 Developers // allocate & initialize shared downcounter: each event will 13710037SARM gem5 Developers // decrement this when triggered; simulation will terminate 13810037SARM gem5 Developers // when counter reaches 0 13910037SARM gem5 Developers int *counter = new int; 14010037SARM gem5 Developers *counter = number_of_threads; 14110037SARM gem5 Developers for (int i = 0; i < number_of_threads; ++i) 14210037SARM gem5 Developers new CountedExitEvent(comInstEventQueue[i], 14310037SARM gem5 Developers "all threads reached the max instruction count", 14410037SARM gem5 Developers p->max_insts_all_threads, *counter); 14510037SARM gem5 Developers } 14610037SARM gem5 Developers 1476019Shines@cs.fsu.edu // allocate per-thread load-based event queues 14810037SARM gem5 Developers comLoadEventQueue = new EventQueue *[number_of_threads]; 14910037SARM gem5 Developers for (int i = 0; i < number_of_threads; ++i) 15010037SARM gem5 Developers comLoadEventQueue[i] = new EventQueue("load-based event queue"); 1516019Shines@cs.fsu.edu 15210037SARM gem5 Developers // 15310037SARM gem5 Developers // set up instruction-count-based termination events, if any 15410037SARM gem5 Developers // 15510037SARM gem5 Developers if (p->max_loads_any_thread != 0) 15610037SARM gem5 Developers for (int i = 0; i < number_of_threads; ++i) 15710037SARM gem5 Developers schedExitSimLoop("a thread reached the max load count", 15810037SARM gem5 Developers p->max_loads_any_thread, 0, 15910037SARM gem5 Developers comLoadEventQueue[i]); 16010037SARM gem5 Developers 16110037SARM gem5 Developers if (p->max_loads_all_threads != 0) { 16210037SARM gem5 Developers // allocate & initialize shared downcounter: each event will 16310037SARM gem5 Developers // decrement this when triggered; simulation will terminate 16410037SARM gem5 Developers // when counter reaches 0 16510037SARM gem5 Developers int *counter = new int; 16610037SARM gem5 Developers *counter = number_of_threads; 16710037SARM gem5 Developers for (int i = 0; i < number_of_threads; ++i) 16810037SARM gem5 Developers new CountedExitEvent(comLoadEventQueue[i], 16910037SARM gem5 Developers "all threads reached the max load count", 17010037SARM gem5 Developers p->max_loads_all_threads, *counter); 17110037SARM gem5 Developers } 17210037SARM gem5 Developers 17310037SARM gem5 Developers functionTracingEnabled = false; 17410037SARM gem5 Developers if (p->functionTrace) { 17510037SARM gem5 Developers functionTraceStream = simout.find(csprintf("ftrace.%s", name())); 17610037SARM gem5 Developers currentFunctionStart = currentFunctionEnd = 0; 17710037SARM gem5 Developers functionEntryTick = p->functionTraceStart; 17810037SARM gem5 Developers 17910037SARM gem5 Developers if (p->functionTraceStart == 0) { 18012571Sgiacomo.travaglini@arm.com functionTracingEnabled = true; 18110037SARM gem5 Developers } else { 18210037SARM gem5 Developers Event *e = 18310037SARM gem5 Developers new EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace>(this, 18410037SARM gem5 Developers true); 18510037SARM gem5 Developers e->schedule(p->functionTraceStart); 18610037SARM gem5 Developers } 18710037SARM gem5 Developers } 18810037SARM gem5 Developers#if FULL_SYSTEM 18910037SARM gem5 Developers profileEvent = NULL; 19010037SARM gem5 Developers if (params->profile) 19110037SARM gem5 Developers profileEvent = new ProfileEvent(this, params->profile); 19210037SARM gem5 Developers#endif 1936019Shines@cs.fsu.edu} 19410037SARM gem5 Developers 19510037SARM gem5 DevelopersBaseCPU::Params::Params() 19610037SARM gem5 Developers{ 1976019Shines@cs.fsu.edu#if FULL_SYSTEM 19810037SARM gem5 Developers profile = false; 19910037SARM gem5 Developers#endif 20010037SARM gem5 Developers checker = NULL; 20112517Srekai.gonzalezalberquilla@arm.com} 20210037SARM gem5 Developers 20310037SARM gem5 Developersvoid 20410037SARM gem5 DevelopersBaseCPU::enableFunctionTrace() 20512517Srekai.gonzalezalberquilla@arm.com{ 20612517Srekai.gonzalezalberquilla@arm.com functionTracingEnabled = true; 20712517Srekai.gonzalezalberquilla@arm.com} 20810037SARM gem5 Developers 20912517Srekai.gonzalezalberquilla@arm.comBaseCPU::~BaseCPU() 21012517Srekai.gonzalezalberquilla@arm.com{ 21112517Srekai.gonzalezalberquilla@arm.com} 21210037SARM gem5 Developers 21312517Srekai.gonzalezalberquilla@arm.comvoid 21412517Srekai.gonzalezalberquilla@arm.comBaseCPU::init() 21512517Srekai.gonzalezalberquilla@arm.com{ 21610037SARM gem5 Developers if (!params->deferRegistration) 21712517Srekai.gonzalezalberquilla@arm.com registerThreadContexts(); 21812517Srekai.gonzalezalberquilla@arm.com} 21912517Srekai.gonzalezalberquilla@arm.com 22010037SARM gem5 Developersvoid 22112517Srekai.gonzalezalberquilla@arm.comBaseCPU::startup() 22212517Srekai.gonzalezalberquilla@arm.com{ 22312517Srekai.gonzalezalberquilla@arm.com#if FULL_SYSTEM 22410037SARM gem5 Developers if (!params->deferRegistration && profileEvent) 22512517Srekai.gonzalezalberquilla@arm.com profileEvent->schedule(curTick); 22612517Srekai.gonzalezalberquilla@arm.com#endif 22712517Srekai.gonzalezalberquilla@arm.com 22810037SARM gem5 Developers if (params->progress_interval) { 22912517Srekai.gonzalezalberquilla@arm.com new CPUProgressEvent(&mainEventQueue, params->progress_interval, 23012517Srekai.gonzalezalberquilla@arm.com this); 23112517Srekai.gonzalezalberquilla@arm.com } 23210037SARM gem5 Developers} 23312517Srekai.gonzalezalberquilla@arm.com 23412517Srekai.gonzalezalberquilla@arm.com 23512517Srekai.gonzalezalberquilla@arm.comvoid 23610037SARM gem5 DevelopersBaseCPU::regStats() 23710037SARM gem5 Developers{ 23812517Srekai.gonzalezalberquilla@arm.com using namespace Stats; 23912517Srekai.gonzalezalberquilla@arm.com 24012517Srekai.gonzalezalberquilla@arm.com numCycles 24112512Sgiacomo.travaglini@arm.com .name(name() + ".numCycles") 24212517Srekai.gonzalezalberquilla@arm.com .desc("number of cpu cycles simulated") 24312517Srekai.gonzalezalberquilla@arm.com ; 24412517Srekai.gonzalezalberquilla@arm.com 24510037SARM gem5 Developers int size = threadContexts.size(); 24612517Srekai.gonzalezalberquilla@arm.com if (size > 1) { 24712517Srekai.gonzalezalberquilla@arm.com for (int i = 0; i < size; ++i) { 24812517Srekai.gonzalezalberquilla@arm.com stringstream namestr; 24910037SARM gem5 Developers ccprintf(namestr, "%s.ctx%d", name(), i); 25012517Srekai.gonzalezalberquilla@arm.com threadContexts[i]->regStats(namestr.str()); 25112517Srekai.gonzalezalberquilla@arm.com } 25212517Srekai.gonzalezalberquilla@arm.com } else if (size == 1) 25310037SARM gem5 Developers threadContexts[0]->regStats(name()); 25412517Srekai.gonzalezalberquilla@arm.com 25512517Srekai.gonzalezalberquilla@arm.com#if FULL_SYSTEM 25612517Srekai.gonzalezalberquilla@arm.com#endif 25710037SARM gem5 Developers} 25812517Srekai.gonzalezalberquilla@arm.com 25912517Srekai.gonzalezalberquilla@arm.comTick 26012764Sgiacomo.travaglini@arm.comBaseCPU::nextCycle() 26112764Sgiacomo.travaglini@arm.com{ 26212764Sgiacomo.travaglini@arm.com Tick next_tick = curTick - phase + clock - 1; 26312764Sgiacomo.travaglini@arm.com next_tick -= (next_tick % clock); 26412517Srekai.gonzalezalberquilla@arm.com next_tick += phase; 26510037SARM gem5 Developers return next_tick; 26610037SARM gem5 Developers} 26712517Srekai.gonzalezalberquilla@arm.com 26812517Srekai.gonzalezalberquilla@arm.comTick 26912517Srekai.gonzalezalberquilla@arm.comBaseCPU::nextCycle(Tick begin_tick) 27010037SARM gem5 Developers{ 27110037SARM gem5 Developers Tick next_tick = begin_tick; 27212517Srekai.gonzalezalberquilla@arm.com next_tick -= (next_tick % clock); 27312517Srekai.gonzalezalberquilla@arm.com next_tick += phase; 27412517Srekai.gonzalezalberquilla@arm.com 27510037SARM gem5 Developers while (next_tick < curTick) 27610037SARM gem5 Developers next_tick += clock; 27712517Srekai.gonzalezalberquilla@arm.com 27812517Srekai.gonzalezalberquilla@arm.com assert(next_tick >= curTick); 27912517Srekai.gonzalezalberquilla@arm.com return next_tick; 28010037SARM gem5 Developers} 28110037SARM gem5 Developers 28212517Srekai.gonzalezalberquilla@arm.comvoid 28312517Srekai.gonzalezalberquilla@arm.comBaseCPU::registerThreadContexts() 28412517Srekai.gonzalezalberquilla@arm.com{ 28512299Sandreas.sandberg@arm.com for (int i = 0; i < threadContexts.size(); ++i) { 28612299Sandreas.sandberg@arm.com ThreadContext *tc = threadContexts[i]; 28712517Srekai.gonzalezalberquilla@arm.com 28812517Srekai.gonzalezalberquilla@arm.com#if FULL_SYSTEM 28912517Srekai.gonzalezalberquilla@arm.com int id = params->cpu_id; 29010037SARM gem5 Developers if (id != -1) 29110037SARM gem5 Developers id += i; 29212517Srekai.gonzalezalberquilla@arm.com 29312517Srekai.gonzalezalberquilla@arm.com tc->setCpuId(system->registerThreadContext(tc, id)); 2946019Shines@cs.fsu.edu#else 29510037SARM gem5 Developers tc->setCpuId(tc->getProcessPtr()->registerThreadContext(tc)); 2967362Sgblack@eecs.umich.edu#endif 2976735Sgblack@eecs.umich.edu } 29810037SARM gem5 Developers} 2996019Shines@cs.fsu.edu 30010037SARM gem5 Developers 30110037SARM gem5 Developersvoid 30213396Sgiacomo.travaglini@arm.comBaseCPU::switchOut() 30310037SARM gem5 Developers{ 3047400SAli.Saidi@ARM.com// panic("This CPU doesn't support sampling!"); 30510037SARM gem5 Developers#if FULL_SYSTEM 30610037SARM gem5 Developers if (profileEvent && profileEvent->scheduled()) 30710037SARM gem5 Developers profileEvent->deschedule(); 30810037SARM gem5 Developers#endif 30910037SARM gem5 Developers} 31010037SARM gem5 Developers 31110037SARM gem5 Developersvoid 31210037SARM gem5 DevelopersBaseCPU::takeOverFrom(BaseCPU *oldCPU) 31310037SARM gem5 Developers{ 31413394Sgiacomo.travaglini@arm.com assert(threadContexts.size() == oldCPU->threadContexts.size()); 31510037SARM gem5 Developers 31610037SARM gem5 Developers for (int i = 0; i < threadContexts.size(); ++i) { 31710037SARM gem5 Developers ThreadContext *newTC = threadContexts[i]; 31813396Sgiacomo.travaglini@arm.com ThreadContext *oldTC = oldCPU->threadContexts[i]; 31913396Sgiacomo.travaglini@arm.com 32010037SARM gem5 Developers newTC->takeOverFrom(oldTC); 32110037SARM gem5 Developers 32210037SARM gem5 Developers CpuEvent::replaceThreadContext(oldTC, newTC); 32313396Sgiacomo.travaglini@arm.com 32410037SARM gem5 Developers assert(newTC->readCpuId() == oldTC->readCpuId()); 3256019Shines@cs.fsu.edu#if FULL_SYSTEM 3266019Shines@cs.fsu.edu system->replaceThreadContext(newTC, newTC->readCpuId()); 32710037SARM gem5 Developers#else 32810037SARM gem5 Developers assert(newTC->getProcessPtr() == oldTC->getProcessPtr()); 32910037SARM gem5 Developers newTC->getProcessPtr()->replaceThreadContext(newTC, newTC->readCpuId()); 33010037SARM gem5 Developers#endif 33110037SARM gem5 Developers 33210037SARM gem5 Developers// TheISA::compareXCs(oldXC, newXC); 33310037SARM gem5 Developers } 33410037SARM gem5 Developers 33510037SARM gem5 Developers#if FULL_SYSTEM 33611574SCurtis.Dunham@arm.com interrupts = oldCPU->interrupts; 33711574SCurtis.Dunham@arm.com checkInterrupts = oldCPU->checkInterrupts; 33811574SCurtis.Dunham@arm.com 33911574SCurtis.Dunham@arm.com for (int i = 0; i < threadContexts.size(); ++i) 34010037SARM gem5 Developers threadContexts[i]->profileClear(); 34110037SARM gem5 Developers 34210037SARM gem5 Developers // The Sampler must take care of this! 34310037SARM gem5 Developers// if (profileEvent) 34410037SARM gem5 Developers// profileEvent->schedule(curTick); 34510037SARM gem5 Developers#endif 34610037SARM gem5 Developers} 34712511Schuan.zhu@arm.com 34810037SARM gem5 Developers 34910037SARM gem5 Developers#if FULL_SYSTEM 35010037SARM gem5 DevelopersBaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, int _interval) 35110037SARM gem5 Developers : Event(&mainEventQueue), cpu(_cpu), interval(_interval) 35210037SARM gem5 Developers{ } 35310037SARM gem5 Developers 35410037SARM gem5 Developersvoid 35510037SARM gem5 DevelopersBaseCPU::ProfileEvent::process() 35610037SARM gem5 Developers{ 35710037SARM gem5 Developers for (int i = 0, size = cpu->threadContexts.size(); i < size; ++i) { 35810037SARM gem5 Developers ThreadContext *tc = cpu->threadContexts[i]; 35910037SARM gem5 Developers tc->profileSample(); 36010037SARM gem5 Developers } 36110037SARM gem5 Developers 36210037SARM gem5 Developers schedule(curTick + interval); 36310037SARM gem5 Developers} 36410037SARM gem5 Developers 36510037SARM gem5 Developersvoid 36610037SARM gem5 DevelopersBaseCPU::post_interrupt(int int_num, int index) 36710037SARM gem5 Developers{ 36810037SARM gem5 Developers checkInterrupts = true; 36910037SARM gem5 Developers interrupts.post(int_num, index); 37010037SARM gem5 Developers} 37110037SARM gem5 Developers 37210037SARM gem5 Developersvoid 37310037SARM gem5 DevelopersBaseCPU::clear_interrupt(int int_num, int index) 37410037SARM gem5 Developers{ 37510037SARM gem5 Developers interrupts.clear(int_num, index); 37610037SARM gem5 Developers} 37710037SARM gem5 Developers 37810037SARM gem5 Developersvoid 37910037SARM gem5 DevelopersBaseCPU::clear_interrupts() 38010037SARM gem5 Developers{ 38110037SARM gem5 Developers interrupts.clear_all(); 38210037SARM gem5 Developers} 38310037SARM gem5 Developers 38410037SARM gem5 Developers 38510037SARM gem5 Developersvoid 38610037SARM gem5 DevelopersBaseCPU::serialize(std::ostream &os) 38710037SARM gem5 Developers{ 38812402Sgiacomo.travaglini@arm.com interrupts.serialize(os); 38910037SARM gem5 Developers} 39010037SARM gem5 Developers 39110037SARM gem5 Developersvoid 39210037SARM gem5 DevelopersBaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 39310037SARM gem5 Developers{ 39410037SARM gem5 Developers interrupts.unserialize(cp, section); 39510037SARM gem5 Developers} 39610037SARM gem5 Developers 39710037SARM gem5 Developers#endif // FULL_SYSTEM 39810037SARM gem5 Developers 39910037SARM gem5 Developersvoid 40010037SARM gem5 DevelopersBaseCPU::traceFunctionsInternal(Addr pc) 40110037SARM gem5 Developers{ 40210037SARM gem5 Developers if (!debugSymbolTable) 40310037SARM gem5 Developers return; 40410037SARM gem5 Developers 40510037SARM gem5 Developers // if pc enters different function, print new function symbol and 40610037SARM gem5 Developers // update saved range. Otherwise do nothing. 40710037SARM gem5 Developers if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 40810037SARM gem5 Developers string sym_str; 40910037SARM gem5 Developers bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 41010037SARM gem5 Developers currentFunctionStart, 41110037SARM gem5 Developers currentFunctionEnd); 41210037SARM gem5 Developers 41310037SARM gem5 Developers if (!found) { 41410037SARM gem5 Developers // no symbol found: use addr as label 41510037SARM gem5 Developers sym_str = csprintf("0x%x", pc); 41610037SARM gem5 Developers currentFunctionStart = pc; 41710037SARM gem5 Developers currentFunctionEnd = pc + 1; 41810037SARM gem5 Developers } 41910037SARM gem5 Developers 42010037SARM gem5 Developers ccprintf(*functionTraceStream, " (%d)\n%d: %s", 42110037SARM gem5 Developers curTick - functionEntryTick, curTick, sym_str); 42210037SARM gem5 Developers functionEntryTick = curTick; 42310037SARM gem5 Developers } 42412569Sgiacomo.travaglini@arm.com} 4256019Shines@cs.fsu.edu 42610037SARM gem5 Developers 42710037SARM gem5 DevelopersDEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU) 42812569Sgiacomo.travaglini@arm.com