base.cc revision 2
1/* 2 * Copyright (c) 2003 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <string> 30#include <sstream> 31#include <iostream> 32 33#include "base_cpu.hh" 34#include "cprintf.hh" 35#include "stats.hh" 36#include "exec_context.hh" 37#include "misc.hh" 38#include "sim_events.hh" 39 40using namespace std; 41 42vector<BaseCPU *> BaseCPU::cpuList; 43 44// This variable reflects the max number of threads in any CPU. Be 45// careful to only use it once all the CPUs that you care about have 46// been initialized 47int maxThreadsPerCPU = 1; 48 49#ifdef FULL_SYSTEM 50BaseCPU::BaseCPU(const string &_name, int _number_of_threads, 51 Counter max_insts_any_thread, 52 Counter max_insts_all_threads, 53 System *_system, int num, Tick freq) 54 : SimObject(_name), number(num), frequency(freq), 55 number_of_threads(_number_of_threads), system(_system) 56#else 57BaseCPU::BaseCPU(const string &_name, int _number_of_threads, 58 Counter max_insts_any_thread, 59 Counter max_insts_all_threads) 60 : SimObject(_name), number_of_threads(_number_of_threads) 61#endif 62{ 63 // add self to global list of CPUs 64 cpuList.push_back(this); 65 66 if (number_of_threads > maxThreadsPerCPU) 67 maxThreadsPerCPU = number_of_threads; 68 69 // allocate per-thread instruction-based event queues 70 comInsnEventQueue = new (EventQueue *)[number_of_threads]; 71 for (int i = 0; i < number_of_threads; ++i) 72 comInsnEventQueue[i] = new EventQueue("instruction-based event queue"); 73 74 // 75 // set up instruction-count-based termination events, if any 76 // 77 if (max_insts_any_thread != 0) 78 for (int i = 0; i < number_of_threads; ++i) 79 new SimExitEvent(comInsnEventQueue[i], max_insts_any_thread, 80 "a thread reached the max instruction count"); 81 82 if (max_insts_all_threads != 0) { 83 // allocate & initialize shared downcounter: each event will 84 // decrement this when triggered; simulation will terminate 85 // when counter reaches 0 86 int *counter = new int; 87 *counter = number_of_threads; 88 for (int i = 0; i < number_of_threads; ++i) 89 new CountedExitEvent(comInsnEventQueue[i], 90 "all threads reached the max instruction count", 91 max_insts_all_threads, *counter); 92 } 93 94#ifdef FULL_SYSTEM 95 memset(interrupts, 0, sizeof(interrupts)); 96 intstatus = 0; 97#endif 98} 99 100void 101BaseCPU::regStats() 102{ 103 int size = contexts.size(); 104 if (size > 1) { 105 for (int i = 0; i < size; ++i) { 106 stringstream namestr; 107 ccprintf(namestr, "%s.ctx%d", name(), i); 108 contexts[i]->regStats(namestr.str()); 109 } 110 } else if (size == 1) 111 contexts[0]->regStats(name()); 112} 113 114#ifdef FULL_SYSTEM 115void 116BaseCPU::post_interrupt(int int_num, int index) 117{ 118 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 119 120 if (int_num < 0 || int_num >= NumInterruptLevels) 121 panic("int_num out of bounds\n"); 122 123 if (index < 0 || index >= sizeof(uint8_t) * 8) 124 panic("int_num out of bounds\n"); 125 126 AlphaISA::check_interrupts = 1; 127 interrupts[int_num] |= 1 << index; 128 intstatus |= (ULL(1) << int_num); 129} 130 131void 132BaseCPU::clear_interrupt(int int_num, int index) 133{ 134 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 135 136 if (int_num < 0 || int_num >= NumInterruptLevels) 137 panic("int_num out of bounds\n"); 138 139 if (index < 0 || index >= sizeof(uint8_t) * 8) 140 panic("int_num out of bounds\n"); 141 142 interrupts[int_num] &= ~(1 << index); 143 if (interrupts[int_num] == 0) 144 intstatus &= ~(ULL(1) << int_num); 145} 146 147void 148BaseCPU::clear_interrupts() 149{ 150 DPRINTF(Interrupt, "Interrupts all cleared\n"); 151 152 memset(interrupts, 0, sizeof(interrupts)); 153 intstatus = 0; 154} 155 156#endif // FULL_SYSTEM 157 158DEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU) 159