base.cc revision 11150:a8a64cca231b
1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * Copyright (c) 2011 Regents of the University of California 16 * Copyright (c) 2013 Advanced Micro Devices, Inc. 17 * Copyright (c) 2013 Mark D. Hill and David A. Wood 18 * All rights reserved. 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions are 22 * met: redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer; 24 * redistributions in binary form must reproduce the above copyright 25 * notice, this list of conditions and the following disclaimer in the 26 * documentation and/or other materials provided with the distribution; 27 * neither the name of the copyright holders nor the names of its 28 * contributors may be used to endorse or promote products derived from 29 * this software without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 * 43 * Authors: Steve Reinhardt 44 * Nathan Binkert 45 * Rick Strong 46 */ 47 48#include <iostream> 49#include <sstream> 50#include <string> 51 52#include "arch/tlb.hh" 53#include "base/loader/symtab.hh" 54#include "base/cprintf.hh" 55#include "base/misc.hh" 56#include "base/output.hh" 57#include "base/trace.hh" 58#include "cpu/checker/cpu.hh" 59#include "cpu/base.hh" 60#include "cpu/cpuevent.hh" 61#include "cpu/profile.hh" 62#include "cpu/thread_context.hh" 63#include "debug/Mwait.hh" 64#include "debug/SyscallVerbose.hh" 65#include "mem/page_table.hh" 66#include "params/BaseCPU.hh" 67#include "sim/full_system.hh" 68#include "sim/process.hh" 69#include "sim/sim_events.hh" 70#include "sim/sim_exit.hh" 71#include "sim/system.hh" 72 73// Hack 74#include "sim/stat_control.hh" 75 76using namespace std; 77 78vector<BaseCPU *> BaseCPU::cpuList; 79 80// This variable reflects the max number of threads in any CPU. Be 81// careful to only use it once all the CPUs that you care about have 82// been initialized 83int maxThreadsPerCPU = 1; 84 85CPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 86 : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 87 cpu(_cpu), _repeatEvent(true) 88{ 89 if (_interval) 90 cpu->schedule(this, curTick() + _interval); 91} 92 93void 94CPUProgressEvent::process() 95{ 96 Counter temp = cpu->totalOps(); 97 98 if (_repeatEvent) 99 cpu->schedule(this, curTick() + _interval); 100 101 if(cpu->switchedOut()) { 102 return; 103 } 104 105#ifndef NDEBUG 106 double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod()); 107 108 DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 109 "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 110 ipc); 111 ipc = 0.0; 112#else 113 cprintf("%lli: %s progress event, total committed:%i, progress insts " 114 "committed: %lli\n", curTick(), cpu->name(), temp, 115 temp - lastNumInst); 116#endif 117 lastNumInst = temp; 118} 119 120const char * 121CPUProgressEvent::description() const 122{ 123 return "CPU Progress"; 124} 125 126BaseCPU::BaseCPU(Params *p, bool is_checker) 127 : MemObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id), 128 _instMasterId(p->system->getMasterId(name() + ".inst")), 129 _dataMasterId(p->system->getMasterId(name() + ".data")), 130 _taskId(ContextSwitchTaskId::Unknown), _pid(invldPid), 131 _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()), 132 interrupts(p->interrupts), profileEvent(NULL), 133 numThreads(p->numThreads), system(p->system), 134 functionTraceStream(nullptr), currentFunctionStart(0), 135 currentFunctionEnd(0), functionEntryTick(0), 136 addressMonitor(p->numThreads) 137{ 138 // if Python did not provide a valid ID, do it here 139 if (_cpuId == -1 ) { 140 _cpuId = cpuList.size(); 141 } 142 143 // add self to global list of CPUs 144 cpuList.push_back(this); 145 146 DPRINTF(SyscallVerbose, "Constructing CPU with id %d, socket id %d\n", 147 _cpuId, _socketId); 148 149 if (numThreads > maxThreadsPerCPU) 150 maxThreadsPerCPU = numThreads; 151 152 // allocate per-thread instruction-based event queues 153 comInstEventQueue = new EventQueue *[numThreads]; 154 for (ThreadID tid = 0; tid < numThreads; ++tid) 155 comInstEventQueue[tid] = 156 new EventQueue("instruction-based event queue"); 157 158 // 159 // set up instruction-count-based termination events, if any 160 // 161 if (p->max_insts_any_thread != 0) { 162 const char *cause = "a thread reached the max instruction count"; 163 for (ThreadID tid = 0; tid < numThreads; ++tid) 164 scheduleInstStop(tid, p->max_insts_any_thread, cause); 165 } 166 167 // Set up instruction-count-based termination events for SimPoints 168 // Typically, there are more than one action points. 169 // Simulation.py is responsible to take the necessary actions upon 170 // exitting the simulation loop. 171 if (!p->simpoint_start_insts.empty()) { 172 const char *cause = "simpoint starting point found"; 173 for (size_t i = 0; i < p->simpoint_start_insts.size(); ++i) 174 scheduleInstStop(0, p->simpoint_start_insts[i], cause); 175 } 176 177 if (p->max_insts_all_threads != 0) { 178 const char *cause = "all threads reached the max instruction count"; 179 180 // allocate & initialize shared downcounter: each event will 181 // decrement this when triggered; simulation will terminate 182 // when counter reaches 0 183 int *counter = new int; 184 *counter = numThreads; 185 for (ThreadID tid = 0; tid < numThreads; ++tid) { 186 Event *event = new CountedExitEvent(cause, *counter); 187 comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 188 } 189 } 190 191 // allocate per-thread load-based event queues 192 comLoadEventQueue = new EventQueue *[numThreads]; 193 for (ThreadID tid = 0; tid < numThreads; ++tid) 194 comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 195 196 // 197 // set up instruction-count-based termination events, if any 198 // 199 if (p->max_loads_any_thread != 0) { 200 const char *cause = "a thread reached the max load count"; 201 for (ThreadID tid = 0; tid < numThreads; ++tid) 202 scheduleLoadStop(tid, p->max_loads_any_thread, cause); 203 } 204 205 if (p->max_loads_all_threads != 0) { 206 const char *cause = "all threads reached the max load count"; 207 // allocate & initialize shared downcounter: each event will 208 // decrement this when triggered; simulation will terminate 209 // when counter reaches 0 210 int *counter = new int; 211 *counter = numThreads; 212 for (ThreadID tid = 0; tid < numThreads; ++tid) { 213 Event *event = new CountedExitEvent(cause, *counter); 214 comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 215 } 216 } 217 218 functionTracingEnabled = false; 219 if (p->function_trace) { 220 const string fname = csprintf("ftrace.%s", name()); 221 functionTraceStream = simout.find(fname); 222 if (!functionTraceStream) 223 functionTraceStream = simout.create(fname); 224 225 currentFunctionStart = currentFunctionEnd = 0; 226 functionEntryTick = p->function_trace_start; 227 228 if (p->function_trace_start == 0) { 229 functionTracingEnabled = true; 230 } else { 231 typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap; 232 Event *event = new wrap(this, true); 233 schedule(event, p->function_trace_start); 234 } 235 } 236 237 // The interrupts should always be present unless this CPU is 238 // switched in later or in case it is a checker CPU 239 if (!params()->switched_out && !is_checker) { 240 if (!interrupts.empty()) { 241 for (ThreadID tid = 0; tid < numThreads; tid++) { 242 interrupts[tid]->setCPU(this); 243 } 244 } else { 245 fatal("CPU %s has no interrupt controller.\n" 246 "Ensure createInterruptController() is called.\n", name()); 247 } 248 } 249 250 if (FullSystem) { 251 if (params()->profile) 252 profileEvent = new ProfileEvent(this, params()->profile); 253 } 254 tracer = params()->tracer; 255 256 if (params()->isa.size() != numThreads) { 257 fatal("Number of ISAs (%i) assigned to the CPU does not equal number " 258 "of threads (%i).\n", params()->isa.size(), numThreads); 259 } 260} 261 262void 263BaseCPU::enableFunctionTrace() 264{ 265 functionTracingEnabled = true; 266} 267 268BaseCPU::~BaseCPU() 269{ 270 delete profileEvent; 271 delete[] comLoadEventQueue; 272 delete[] comInstEventQueue; 273} 274 275void 276BaseCPU::armMonitor(ThreadID tid, Addr address) 277{ 278 assert(tid < numThreads); 279 AddressMonitor &monitor = addressMonitor[tid]; 280 281 monitor.armed = true; 282 monitor.vAddr = address; 283 monitor.pAddr = 0x0; 284 DPRINTF(Mwait,"[tid:%d] Armed monitor (vAddr=0x%lx)\n", tid, address); 285} 286 287bool 288BaseCPU::mwait(ThreadID tid, PacketPtr pkt) 289{ 290 assert(tid < numThreads); 291 AddressMonitor &monitor = addressMonitor[tid]; 292 293 if(monitor.gotWakeup == false) { 294 int block_size = cacheLineSize(); 295 uint64_t mask = ~((uint64_t)(block_size - 1)); 296 297 assert(pkt->req->hasPaddr()); 298 monitor.pAddr = pkt->getAddr() & mask; 299 monitor.waiting = true; 300 301 DPRINTF(Mwait,"[tid:%d] mwait called (vAddr=0x%lx, " 302 "line's paddr=0x%lx)\n", tid, monitor.vAddr, monitor.pAddr); 303 return true; 304 } else { 305 monitor.gotWakeup = false; 306 return false; 307 } 308} 309 310void 311BaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, TheISA::TLB *dtb) 312{ 313 assert(tid < numThreads); 314 AddressMonitor &monitor = addressMonitor[tid]; 315 316 Request req; 317 Addr addr = monitor.vAddr; 318 int block_size = cacheLineSize(); 319 uint64_t mask = ~((uint64_t)(block_size - 1)); 320 int size = block_size; 321 322 //The address of the next line if it crosses a cache line boundary. 323 Addr secondAddr = roundDown(addr + size - 1, block_size); 324 325 if (secondAddr > addr) 326 size = secondAddr - addr; 327 328 req.setVirt(0, addr, size, 0x0, dataMasterId(), tc->instAddr()); 329 330 // translate to physical address 331 Fault fault = dtb->translateAtomic(&req, tc, BaseTLB::Read); 332 assert(fault == NoFault); 333 334 monitor.pAddr = req.getPaddr() & mask; 335 monitor.waiting = true; 336 337 DPRINTF(Mwait,"[tid:%d] mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n", 338 tid, monitor.vAddr, monitor.pAddr); 339} 340 341void 342BaseCPU::init() 343{ 344 if (!params()->switched_out) { 345 registerThreadContexts(); 346 347 verifyMemoryMode(); 348 } 349} 350 351void 352BaseCPU::startup() 353{ 354 if (FullSystem) { 355 if (!params()->switched_out && profileEvent) 356 schedule(profileEvent, curTick()); 357 } 358 359 if (params()->progress_interval) { 360 new CPUProgressEvent(this, params()->progress_interval); 361 } 362} 363 364ProbePoints::PMUUPtr 365BaseCPU::pmuProbePoint(const char *name) 366{ 367 ProbePoints::PMUUPtr ptr; 368 ptr.reset(new ProbePoints::PMU(getProbeManager(), name)); 369 370 return ptr; 371} 372 373void 374BaseCPU::regProbePoints() 375{ 376 ppCycles = pmuProbePoint("Cycles"); 377 378 ppRetiredInsts = pmuProbePoint("RetiredInsts"); 379 ppRetiredLoads = pmuProbePoint("RetiredLoads"); 380 ppRetiredStores = pmuProbePoint("RetiredStores"); 381 ppRetiredBranches = pmuProbePoint("RetiredBranches"); 382} 383 384void 385BaseCPU::probeInstCommit(const StaticInstPtr &inst) 386{ 387 if (!inst->isMicroop() || inst->isLastMicroop()) 388 ppRetiredInsts->notify(1); 389 390 391 if (inst->isLoad()) 392 ppRetiredLoads->notify(1); 393 394 if (inst->isStore()) 395 ppRetiredStores->notify(1); 396 397 if (inst->isControl()) 398 ppRetiredBranches->notify(1); 399} 400 401void 402BaseCPU::regStats() 403{ 404 using namespace Stats; 405 406 numCycles 407 .name(name() + ".numCycles") 408 .desc("number of cpu cycles simulated") 409 ; 410 411 numWorkItemsStarted 412 .name(name() + ".numWorkItemsStarted") 413 .desc("number of work items this cpu started") 414 ; 415 416 numWorkItemsCompleted 417 .name(name() + ".numWorkItemsCompleted") 418 .desc("number of work items this cpu completed") 419 ; 420 421 int size = threadContexts.size(); 422 if (size > 1) { 423 for (int i = 0; i < size; ++i) { 424 stringstream namestr; 425 ccprintf(namestr, "%s.ctx%d", name(), i); 426 threadContexts[i]->regStats(namestr.str()); 427 } 428 } else if (size == 1) 429 threadContexts[0]->regStats(name()); 430} 431 432BaseMasterPort & 433BaseCPU::getMasterPort(const string &if_name, PortID idx) 434{ 435 // Get the right port based on name. This applies to all the 436 // subclasses of the base CPU and relies on their implementation 437 // of getDataPort and getInstPort. In all cases there methods 438 // return a MasterPort pointer. 439 if (if_name == "dcache_port") 440 return getDataPort(); 441 else if (if_name == "icache_port") 442 return getInstPort(); 443 else 444 return MemObject::getMasterPort(if_name, idx); 445} 446 447void 448BaseCPU::registerThreadContexts() 449{ 450 assert(system->multiThread || numThreads == 1); 451 452 ThreadID size = threadContexts.size(); 453 for (ThreadID tid = 0; tid < size; ++tid) { 454 ThreadContext *tc = threadContexts[tid]; 455 456 if (system->multiThread) { 457 tc->setContextId(system->registerThreadContext(tc)); 458 } else { 459 tc->setContextId(system->registerThreadContext(tc, _cpuId)); 460 } 461 462 if (!FullSystem) 463 tc->getProcessPtr()->assignThreadContext(tc->contextId()); 464 } 465} 466 467 468int 469BaseCPU::findContext(ThreadContext *tc) 470{ 471 ThreadID size = threadContexts.size(); 472 for (ThreadID tid = 0; tid < size; ++tid) { 473 if (tc == threadContexts[tid]) 474 return tid; 475 } 476 return 0; 477} 478 479void 480BaseCPU::switchOut() 481{ 482 assert(!_switchedOut); 483 _switchedOut = true; 484 if (profileEvent && profileEvent->scheduled()) 485 deschedule(profileEvent); 486 487 // Flush all TLBs in the CPU to avoid having stale translations if 488 // it gets switched in later. 489 flushTLBs(); 490} 491 492void 493BaseCPU::takeOverFrom(BaseCPU *oldCPU) 494{ 495 assert(threadContexts.size() == oldCPU->threadContexts.size()); 496 assert(_cpuId == oldCPU->cpuId()); 497 assert(_switchedOut); 498 assert(oldCPU != this); 499 _pid = oldCPU->getPid(); 500 _taskId = oldCPU->taskId(); 501 _switchedOut = false; 502 503 ThreadID size = threadContexts.size(); 504 for (ThreadID i = 0; i < size; ++i) { 505 ThreadContext *newTC = threadContexts[i]; 506 ThreadContext *oldTC = oldCPU->threadContexts[i]; 507 508 newTC->takeOverFrom(oldTC); 509 510 CpuEvent::replaceThreadContext(oldTC, newTC); 511 512 assert(newTC->contextId() == oldTC->contextId()); 513 assert(newTC->threadId() == oldTC->threadId()); 514 system->replaceThreadContext(newTC, newTC->contextId()); 515 516 /* This code no longer works since the zero register (e.g., 517 * r31 on Alpha) doesn't necessarily contain zero at this 518 * point. 519 if (DTRACE(Context)) 520 ThreadContext::compare(oldTC, newTC); 521 */ 522 523 BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort(); 524 BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort(); 525 BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort(); 526 BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort(); 527 528 // Move over any table walker ports if they exist 529 if (new_itb_port) { 530 assert(!new_itb_port->isConnected()); 531 assert(old_itb_port); 532 assert(old_itb_port->isConnected()); 533 BaseSlavePort &slavePort = old_itb_port->getSlavePort(); 534 old_itb_port->unbind(); 535 new_itb_port->bind(slavePort); 536 } 537 if (new_dtb_port) { 538 assert(!new_dtb_port->isConnected()); 539 assert(old_dtb_port); 540 assert(old_dtb_port->isConnected()); 541 BaseSlavePort &slavePort = old_dtb_port->getSlavePort(); 542 old_dtb_port->unbind(); 543 new_dtb_port->bind(slavePort); 544 } 545 newTC->getITBPtr()->takeOverFrom(oldTC->getITBPtr()); 546 newTC->getDTBPtr()->takeOverFrom(oldTC->getDTBPtr()); 547 548 // Checker whether or not we have to transfer CheckerCPU 549 // objects over in the switch 550 CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr(); 551 CheckerCPU *newChecker = newTC->getCheckerCpuPtr(); 552 if (oldChecker && newChecker) { 553 BaseMasterPort *old_checker_itb_port = 554 oldChecker->getITBPtr()->getMasterPort(); 555 BaseMasterPort *old_checker_dtb_port = 556 oldChecker->getDTBPtr()->getMasterPort(); 557 BaseMasterPort *new_checker_itb_port = 558 newChecker->getITBPtr()->getMasterPort(); 559 BaseMasterPort *new_checker_dtb_port = 560 newChecker->getDTBPtr()->getMasterPort(); 561 562 newChecker->getITBPtr()->takeOverFrom(oldChecker->getITBPtr()); 563 newChecker->getDTBPtr()->takeOverFrom(oldChecker->getDTBPtr()); 564 565 // Move over any table walker ports if they exist for checker 566 if (new_checker_itb_port) { 567 assert(!new_checker_itb_port->isConnected()); 568 assert(old_checker_itb_port); 569 assert(old_checker_itb_port->isConnected()); 570 BaseSlavePort &slavePort = 571 old_checker_itb_port->getSlavePort(); 572 old_checker_itb_port->unbind(); 573 new_checker_itb_port->bind(slavePort); 574 } 575 if (new_checker_dtb_port) { 576 assert(!new_checker_dtb_port->isConnected()); 577 assert(old_checker_dtb_port); 578 assert(old_checker_dtb_port->isConnected()); 579 BaseSlavePort &slavePort = 580 old_checker_dtb_port->getSlavePort(); 581 old_checker_dtb_port->unbind(); 582 new_checker_dtb_port->bind(slavePort); 583 } 584 } 585 } 586 587 interrupts = oldCPU->interrupts; 588 for (ThreadID tid = 0; tid < numThreads; tid++) { 589 interrupts[tid]->setCPU(this); 590 } 591 oldCPU->interrupts.clear(); 592 593 if (FullSystem) { 594 for (ThreadID i = 0; i < size; ++i) 595 threadContexts[i]->profileClear(); 596 597 if (profileEvent) 598 schedule(profileEvent, curTick()); 599 } 600 601 // All CPUs have an instruction and a data port, and the new CPU's 602 // ports are dangling while the old CPU has its ports connected 603 // already. Unbind the old CPU and then bind the ports of the one 604 // we are switching to. 605 assert(!getInstPort().isConnected()); 606 assert(oldCPU->getInstPort().isConnected()); 607 BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort(); 608 oldCPU->getInstPort().unbind(); 609 getInstPort().bind(inst_peer_port); 610 611 assert(!getDataPort().isConnected()); 612 assert(oldCPU->getDataPort().isConnected()); 613 BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort(); 614 oldCPU->getDataPort().unbind(); 615 getDataPort().bind(data_peer_port); 616} 617 618void 619BaseCPU::flushTLBs() 620{ 621 for (ThreadID i = 0; i < threadContexts.size(); ++i) { 622 ThreadContext &tc(*threadContexts[i]); 623 CheckerCPU *checker(tc.getCheckerCpuPtr()); 624 625 tc.getITBPtr()->flushAll(); 626 tc.getDTBPtr()->flushAll(); 627 if (checker) { 628 checker->getITBPtr()->flushAll(); 629 checker->getDTBPtr()->flushAll(); 630 } 631 } 632} 633 634 635BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval) 636 : cpu(_cpu), interval(_interval) 637{ } 638 639void 640BaseCPU::ProfileEvent::process() 641{ 642 ThreadID size = cpu->threadContexts.size(); 643 for (ThreadID i = 0; i < size; ++i) { 644 ThreadContext *tc = cpu->threadContexts[i]; 645 tc->profileSample(); 646 } 647 648 cpu->schedule(this, curTick() + interval); 649} 650 651void 652BaseCPU::serialize(CheckpointOut &cp) const 653{ 654 SERIALIZE_SCALAR(instCnt); 655 656 if (!_switchedOut) { 657 /* Unlike _pid, _taskId is not serialized, as they are dynamically 658 * assigned unique ids that are only meaningful for the duration of 659 * a specific run. We will need to serialize the entire taskMap in 660 * system. */ 661 SERIALIZE_SCALAR(_pid); 662 663 // Serialize the threads, this is done by the CPU implementation. 664 for (ThreadID i = 0; i < numThreads; ++i) { 665 ScopedCheckpointSection sec(cp, csprintf("xc.%i", i)); 666 interrupts[i]->serialize(cp); 667 serializeThread(cp, i); 668 } 669 } 670} 671 672void 673BaseCPU::unserialize(CheckpointIn &cp) 674{ 675 UNSERIALIZE_SCALAR(instCnt); 676 677 if (!_switchedOut) { 678 UNSERIALIZE_SCALAR(_pid); 679 680 // Unserialize the threads, this is done by the CPU implementation. 681 for (ThreadID i = 0; i < numThreads; ++i) { 682 ScopedCheckpointSection sec(cp, csprintf("xc.%i", i)); 683 interrupts[i]->unserialize(cp); 684 unserializeThread(cp, i); 685 } 686 } 687} 688 689void 690BaseCPU::scheduleInstStop(ThreadID tid, Counter insts, const char *cause) 691{ 692 const Tick now(comInstEventQueue[tid]->getCurTick()); 693 Event *event(new LocalSimLoopExitEvent(cause, 0)); 694 695 comInstEventQueue[tid]->schedule(event, now + insts); 696} 697 698AddressMonitor::AddressMonitor() { 699 armed = false; 700 waiting = false; 701 gotWakeup = false; 702} 703 704bool AddressMonitor::doMonitor(PacketPtr pkt) { 705 assert(pkt->req->hasPaddr()); 706 if(armed && waiting) { 707 if(pAddr == pkt->getAddr()) { 708 DPRINTF(Mwait,"pAddr=0x%lx invalidated: waking up core\n", 709 pkt->getAddr()); 710 waiting = false; 711 return true; 712 } 713 } 714 return false; 715} 716 717void 718BaseCPU::scheduleLoadStop(ThreadID tid, Counter loads, const char *cause) 719{ 720 const Tick now(comLoadEventQueue[tid]->getCurTick()); 721 Event *event(new LocalSimLoopExitEvent(cause, 0)); 722 723 comLoadEventQueue[tid]->schedule(event, now + loads); 724} 725 726 727void 728BaseCPU::traceFunctionsInternal(Addr pc) 729{ 730 if (!debugSymbolTable) 731 return; 732 733 // if pc enters different function, print new function symbol and 734 // update saved range. Otherwise do nothing. 735 if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 736 string sym_str; 737 bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 738 currentFunctionStart, 739 currentFunctionEnd); 740 741 if (!found) { 742 // no symbol found: use addr as label 743 sym_str = csprintf("0x%x", pc); 744 currentFunctionStart = pc; 745 currentFunctionEnd = pc + 1; 746 } 747 748 ccprintf(*functionTraceStream, " (%d)\n%d: %s", 749 curTick() - functionEntryTick, curTick(), sym_str); 750 functionEntryTick = curTick(); 751 } 752} 753