base.cc revision 11146 
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * Copyright (c) 2013 Advanced Micro Devices, Inc.
17 * Copyright (c) 2013 Mark D. Hill and David A. Wood
18 * All rights reserved.
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions are
22 * met: redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer;
24 * redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution;
27 * neither the name of the copyright holders nor the names of its
28 * contributors may be used to endorse or promote products derived from
29 * this software without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 * Authors: Steve Reinhardt
44 *          Nathan Binkert
45 *          Rick Strong
46 */
47
48#include <iostream>
49#include <sstream>
50#include <string>
51
52#include "arch/tlb.hh"
53#include "base/loader/symtab.hh"
54#include "base/cprintf.hh"
55#include "base/misc.hh"
56#include "base/output.hh"
57#include "base/trace.hh"
58#include "cpu/checker/cpu.hh"
59#include "cpu/base.hh"
60#include "cpu/cpuevent.hh"
61#include "cpu/profile.hh"
62#include "cpu/thread_context.hh"
63#include "debug/Mwait.hh"
64#include "debug/SyscallVerbose.hh"
65#include "mem/page_table.hh"
66#include "params/BaseCPU.hh"
67#include "sim/full_system.hh"
68#include "sim/process.hh"
69#include "sim/sim_events.hh"
70#include "sim/sim_exit.hh"
71#include "sim/system.hh"
72
73// Hack
74#include "sim/stat_control.hh"
75
76using namespace std;
77
78vector<BaseCPU *> BaseCPU::cpuList;
79
80// This variable reflects the max number of threads in any CPU.  Be
81// careful to only use it once all the CPUs that you care about have
82// been initialized
83int maxThreadsPerCPU = 1;
84
85CPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival)
86    : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0),
87      cpu(_cpu), _repeatEvent(true)
88{
89    if (_interval)
90        cpu->schedule(this, curTick() + _interval);
91}
92
93void
94CPUProgressEvent::process()
95{
96    Counter temp = cpu->totalOps();
97
98    if (_repeatEvent)
99      cpu->schedule(this, curTick() + _interval);
100
101    if(cpu->switchedOut()) {
102      return;
103    }
104
105#ifndef NDEBUG
106    double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod());
107
108    DPRINTFN("%s progress event, total committed:%i, progress insts committed: "
109             "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst,
110             ipc);
111    ipc = 0.0;
112#else
113    cprintf("%lli: %s progress event, total committed:%i, progress insts "
114            "committed: %lli\n", curTick(), cpu->name(), temp,
115            temp - lastNumInst);
116#endif
117    lastNumInst = temp;
118}
119
120const char *
121CPUProgressEvent::description() const
122{
123    return "CPU Progress";
124}
125
126BaseCPU::BaseCPU(Params *p, bool is_checker)
127    : MemObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id),
128      _instMasterId(p->system->getMasterId(name() + ".inst")),
129      _dataMasterId(p->system->getMasterId(name() + ".data")),
130      _taskId(ContextSwitchTaskId::Unknown), _pid(invldPid),
131      _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()),
132      interrupts(p->interrupts), profileEvent(NULL),
133      numThreads(p->numThreads), system(p->system),
134      functionTraceStream(nullptr), currentFunctionStart(0),
135      currentFunctionEnd(0), functionEntryTick(0),
136      addressMonitor()
137{
138    // if Python did not provide a valid ID, do it here
139    if (_cpuId == -1 ) {
140        _cpuId = cpuList.size();
141    }
142
143    // add self to global list of CPUs
144    cpuList.push_back(this);
145
146    DPRINTF(SyscallVerbose, "Constructing CPU with id %d, socket id %d\n",
147                _cpuId, _socketId);
148
149    if (numThreads > maxThreadsPerCPU)
150        maxThreadsPerCPU = numThreads;
151
152    // allocate per-thread instruction-based event queues
153    comInstEventQueue = new EventQueue *[numThreads];
154    for (ThreadID tid = 0; tid < numThreads; ++tid)
155        comInstEventQueue[tid] =
156            new EventQueue("instruction-based event queue");
157
158    //
159    // set up instruction-count-based termination events, if any
160    //
161    if (p->max_insts_any_thread != 0) {
162        const char *cause = "a thread reached the max instruction count";
163        for (ThreadID tid = 0; tid < numThreads; ++tid)
164            scheduleInstStop(tid, p->max_insts_any_thread, cause);
165    }
166
167    // Set up instruction-count-based termination events for SimPoints
168    // Typically, there are more than one action points.
169    // Simulation.py is responsible to take the necessary actions upon
170    // exitting the simulation loop.
171    if (!p->simpoint_start_insts.empty()) {
172        const char *cause = "simpoint starting point found";
173        for (size_t i = 0; i < p->simpoint_start_insts.size(); ++i)
174            scheduleInstStop(0, p->simpoint_start_insts[i], cause);
175    }
176
177    if (p->max_insts_all_threads != 0) {
178        const char *cause = "all threads reached the max instruction count";
179
180        // allocate & initialize shared downcounter: each event will
181        // decrement this when triggered; simulation will terminate
182        // when counter reaches 0
183        int *counter = new int;
184        *counter = numThreads;
185        for (ThreadID tid = 0; tid < numThreads; ++tid) {
186            Event *event = new CountedExitEvent(cause, *counter);
187            comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads);
188        }
189    }
190
191    // allocate per-thread load-based event queues
192    comLoadEventQueue = new EventQueue *[numThreads];
193    for (ThreadID tid = 0; tid < numThreads; ++tid)
194        comLoadEventQueue[tid] = new EventQueue("load-based event queue");
195
196    //
197    // set up instruction-count-based termination events, if any
198    //
199    if (p->max_loads_any_thread != 0) {
200        const char *cause = "a thread reached the max load count";
201        for (ThreadID tid = 0; tid < numThreads; ++tid)
202            scheduleLoadStop(tid, p->max_loads_any_thread, cause);
203    }
204
205    if (p->max_loads_all_threads != 0) {
206        const char *cause = "all threads reached the max load count";
207        // allocate & initialize shared downcounter: each event will
208        // decrement this when triggered; simulation will terminate
209        // when counter reaches 0
210        int *counter = new int;
211        *counter = numThreads;
212        for (ThreadID tid = 0; tid < numThreads; ++tid) {
213            Event *event = new CountedExitEvent(cause, *counter);
214            comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads);
215        }
216    }
217
218    functionTracingEnabled = false;
219    if (p->function_trace) {
220        const string fname = csprintf("ftrace.%s", name());
221        functionTraceStream = simout.find(fname);
222        if (!functionTraceStream)
223            functionTraceStream = simout.create(fname);
224
225        currentFunctionStart = currentFunctionEnd = 0;
226        functionEntryTick = p->function_trace_start;
227
228        if (p->function_trace_start == 0) {
229            functionTracingEnabled = true;
230        } else {
231            typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap;
232            Event *event = new wrap(this, true);
233            schedule(event, p->function_trace_start);
234        }
235    }
236
237    // The interrupts should always be present unless this CPU is
238    // switched in later or in case it is a checker CPU
239    if (!params()->switched_out && !is_checker) {
240        if (interrupts) {
241            interrupts->setCPU(this);
242        } else {
243            fatal("CPU %s has no interrupt controller.\n"
244                  "Ensure createInterruptController() is called.\n", name());
245        }
246    }
247
248    if (FullSystem) {
249        if (params()->profile)
250            profileEvent = new ProfileEvent(this, params()->profile);
251    }
252    tracer = params()->tracer;
253
254    if (params()->isa.size() != numThreads) {
255        fatal("Number of ISAs (%i) assigned to the CPU does not equal number "
256              "of threads (%i).\n", params()->isa.size(), numThreads);
257    }
258}
259
260void
261BaseCPU::enableFunctionTrace()
262{
263    functionTracingEnabled = true;
264}
265
266BaseCPU::~BaseCPU()
267{
268    delete profileEvent;
269    delete[] comLoadEventQueue;
270    delete[] comInstEventQueue;
271}
272
273void
274BaseCPU::armMonitor(Addr address)
275{
276    addressMonitor.armed = true;
277    addressMonitor.vAddr = address;
278    addressMonitor.pAddr = 0x0;
279    DPRINTF(Mwait,"Armed monitor (vAddr=0x%lx)\n", address);
280}
281
282bool
283BaseCPU::mwait(PacketPtr pkt)
284{
285    if(addressMonitor.gotWakeup == false) {
286        int block_size = cacheLineSize();
287        uint64_t mask = ~((uint64_t)(block_size - 1));
288
289        assert(pkt->req->hasPaddr());
290        addressMonitor.pAddr = pkt->getAddr() & mask;
291        addressMonitor.waiting = true;
292
293        DPRINTF(Mwait,"mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n",
294                addressMonitor.vAddr, addressMonitor.pAddr);
295        return true;
296    } else {
297        addressMonitor.gotWakeup = false;
298        return false;
299    }
300}
301
302void
303BaseCPU::mwaitAtomic(ThreadContext *tc, TheISA::TLB *dtb)
304{
305    Request req;
306    Addr addr = addressMonitor.vAddr;
307    int block_size = cacheLineSize();
308    uint64_t mask = ~((uint64_t)(block_size - 1));
309    int size = block_size;
310
311    //The address of the next line if it crosses a cache line boundary.
312    Addr secondAddr = roundDown(addr + size - 1, block_size);
313
314    if (secondAddr > addr)
315        size = secondAddr - addr;
316
317    req.setVirt(0, addr, size, 0x0, dataMasterId(), tc->instAddr());
318
319    // translate to physical address
320    Fault fault = dtb->translateAtomic(&req, tc, BaseTLB::Read);
321    assert(fault == NoFault);
322
323    addressMonitor.pAddr = req.getPaddr() & mask;
324    addressMonitor.waiting = true;
325
326    DPRINTF(Mwait,"mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n",
327            addressMonitor.vAddr, addressMonitor.pAddr);
328}
329
330void
331BaseCPU::init()
332{
333    if (!params()->switched_out) {
334        registerThreadContexts();
335
336        verifyMemoryMode();
337    }
338}
339
340void
341BaseCPU::startup()
342{
343    if (FullSystem) {
344        if (!params()->switched_out && profileEvent)
345            schedule(profileEvent, curTick());
346    }
347
348    if (params()->progress_interval) {
349        new CPUProgressEvent(this, params()->progress_interval);
350    }
351}
352
353ProbePoints::PMUUPtr
354BaseCPU::pmuProbePoint(const char *name)
355{
356    ProbePoints::PMUUPtr ptr;
357    ptr.reset(new ProbePoints::PMU(getProbeManager(), name));
358
359    return ptr;
360}
361
362void
363BaseCPU::regProbePoints()
364{
365    ppCycles = pmuProbePoint("Cycles");
366
367    ppRetiredInsts = pmuProbePoint("RetiredInsts");
368    ppRetiredLoads = pmuProbePoint("RetiredLoads");
369    ppRetiredStores = pmuProbePoint("RetiredStores");
370    ppRetiredBranches = pmuProbePoint("RetiredBranches");
371}
372
373void
374BaseCPU::probeInstCommit(const StaticInstPtr &inst)
375{
376    if (!inst->isMicroop() || inst->isLastMicroop())
377        ppRetiredInsts->notify(1);
378
379
380    if (inst->isLoad())
381        ppRetiredLoads->notify(1);
382
383    if (inst->isStore())
384        ppRetiredStores->notify(1);
385
386    if (inst->isControl())
387        ppRetiredBranches->notify(1);
388}
389
390void
391BaseCPU::regStats()
392{
393    using namespace Stats;
394
395    numCycles
396        .name(name() + ".numCycles")
397        .desc("number of cpu cycles simulated")
398        ;
399
400    numWorkItemsStarted
401        .name(name() + ".numWorkItemsStarted")
402        .desc("number of work items this cpu started")
403        ;
404
405    numWorkItemsCompleted
406        .name(name() + ".numWorkItemsCompleted")
407        .desc("number of work items this cpu completed")
408        ;
409
410    int size = threadContexts.size();
411    if (size > 1) {
412        for (int i = 0; i < size; ++i) {
413            stringstream namestr;
414            ccprintf(namestr, "%s.ctx%d", name(), i);
415            threadContexts[i]->regStats(namestr.str());
416        }
417    } else if (size == 1)
418        threadContexts[0]->regStats(name());
419}
420
421BaseMasterPort &
422BaseCPU::getMasterPort(const string &if_name, PortID idx)
423{
424    // Get the right port based on name. This applies to all the
425    // subclasses of the base CPU and relies on their implementation
426    // of getDataPort and getInstPort. In all cases there methods
427    // return a MasterPort pointer.
428    if (if_name == "dcache_port")
429        return getDataPort();
430    else if (if_name == "icache_port")
431        return getInstPort();
432    else
433        return MemObject::getMasterPort(if_name, idx);
434}
435
436void
437BaseCPU::registerThreadContexts()
438{
439    assert(system->multiThread || numThreads == 1);
440
441    ThreadID size = threadContexts.size();
442    for (ThreadID tid = 0; tid < size; ++tid) {
443        ThreadContext *tc = threadContexts[tid];
444
445        if (system->multiThread) {
446            tc->setContextId(system->registerThreadContext(tc));
447        } else {
448            tc->setContextId(system->registerThreadContext(tc, _cpuId));
449        }
450
451        if (!FullSystem)
452            tc->getProcessPtr()->assignThreadContext(tc->contextId());
453    }
454}
455
456
457int
458BaseCPU::findContext(ThreadContext *tc)
459{
460    ThreadID size = threadContexts.size();
461    for (ThreadID tid = 0; tid < size; ++tid) {
462        if (tc == threadContexts[tid])
463            return tid;
464    }
465    return 0;
466}
467
468void
469BaseCPU::switchOut()
470{
471    assert(!_switchedOut);
472    _switchedOut = true;
473    if (profileEvent && profileEvent->scheduled())
474        deschedule(profileEvent);
475
476    // Flush all TLBs in the CPU to avoid having stale translations if
477    // it gets switched in later.
478    flushTLBs();
479}
480
481void
482BaseCPU::takeOverFrom(BaseCPU *oldCPU)
483{
484    assert(threadContexts.size() == oldCPU->threadContexts.size());
485    assert(_cpuId == oldCPU->cpuId());
486    assert(_switchedOut);
487    assert(oldCPU != this);
488    _pid = oldCPU->getPid();
489    _taskId = oldCPU->taskId();
490    _switchedOut = false;
491
492    ThreadID size = threadContexts.size();
493    for (ThreadID i = 0; i < size; ++i) {
494        ThreadContext *newTC = threadContexts[i];
495        ThreadContext *oldTC = oldCPU->threadContexts[i];
496
497        newTC->takeOverFrom(oldTC);
498
499        CpuEvent::replaceThreadContext(oldTC, newTC);
500
501        assert(newTC->contextId() == oldTC->contextId());
502        assert(newTC->threadId() == oldTC->threadId());
503        system->replaceThreadContext(newTC, newTC->contextId());
504
505        /* This code no longer works since the zero register (e.g.,
506         * r31 on Alpha) doesn't necessarily contain zero at this
507         * point.
508           if (DTRACE(Context))
509            ThreadContext::compare(oldTC, newTC);
510        */
511
512        BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort();
513        BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort();
514        BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort();
515        BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort();
516
517        // Move over any table walker ports if they exist
518        if (new_itb_port) {
519            assert(!new_itb_port->isConnected());
520            assert(old_itb_port);
521            assert(old_itb_port->isConnected());
522            BaseSlavePort &slavePort = old_itb_port->getSlavePort();
523            old_itb_port->unbind();
524            new_itb_port->bind(slavePort);
525        }
526        if (new_dtb_port) {
527            assert(!new_dtb_port->isConnected());
528            assert(old_dtb_port);
529            assert(old_dtb_port->isConnected());
530            BaseSlavePort &slavePort = old_dtb_port->getSlavePort();
531            old_dtb_port->unbind();
532            new_dtb_port->bind(slavePort);
533        }
534        newTC->getITBPtr()->takeOverFrom(oldTC->getITBPtr());
535        newTC->getDTBPtr()->takeOverFrom(oldTC->getDTBPtr());
536
537        // Checker whether or not we have to transfer CheckerCPU
538        // objects over in the switch
539        CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr();
540        CheckerCPU *newChecker = newTC->getCheckerCpuPtr();
541        if (oldChecker && newChecker) {
542            BaseMasterPort *old_checker_itb_port =
543                oldChecker->getITBPtr()->getMasterPort();
544            BaseMasterPort *old_checker_dtb_port =
545                oldChecker->getDTBPtr()->getMasterPort();
546            BaseMasterPort *new_checker_itb_port =
547                newChecker->getITBPtr()->getMasterPort();
548            BaseMasterPort *new_checker_dtb_port =
549                newChecker->getDTBPtr()->getMasterPort();
550
551            newChecker->getITBPtr()->takeOverFrom(oldChecker->getITBPtr());
552            newChecker->getDTBPtr()->takeOverFrom(oldChecker->getDTBPtr());
553
554            // Move over any table walker ports if they exist for checker
555            if (new_checker_itb_port) {
556                assert(!new_checker_itb_port->isConnected());
557                assert(old_checker_itb_port);
558                assert(old_checker_itb_port->isConnected());
559                BaseSlavePort &slavePort =
560                    old_checker_itb_port->getSlavePort();
561                old_checker_itb_port->unbind();
562                new_checker_itb_port->bind(slavePort);
563            }
564            if (new_checker_dtb_port) {
565                assert(!new_checker_dtb_port->isConnected());
566                assert(old_checker_dtb_port);
567                assert(old_checker_dtb_port->isConnected());
568                BaseSlavePort &slavePort =
569                    old_checker_dtb_port->getSlavePort();
570                old_checker_dtb_port->unbind();
571                new_checker_dtb_port->bind(slavePort);
572            }
573        }
574    }
575
576    interrupts = oldCPU->interrupts;
577    interrupts->setCPU(this);
578    oldCPU->interrupts = NULL;
579
580    if (FullSystem) {
581        for (ThreadID i = 0; i < size; ++i)
582            threadContexts[i]->profileClear();
583
584        if (profileEvent)
585            schedule(profileEvent, curTick());
586    }
587
588    // All CPUs have an instruction and a data port, and the new CPU's
589    // ports are dangling while the old CPU has its ports connected
590    // already. Unbind the old CPU and then bind the ports of the one
591    // we are switching to.
592    assert(!getInstPort().isConnected());
593    assert(oldCPU->getInstPort().isConnected());
594    BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort();
595    oldCPU->getInstPort().unbind();
596    getInstPort().bind(inst_peer_port);
597
598    assert(!getDataPort().isConnected());
599    assert(oldCPU->getDataPort().isConnected());
600    BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort();
601    oldCPU->getDataPort().unbind();
602    getDataPort().bind(data_peer_port);
603}
604
605void
606BaseCPU::flushTLBs()
607{
608    for (ThreadID i = 0; i < threadContexts.size(); ++i) {
609        ThreadContext &tc(*threadContexts[i]);
610        CheckerCPU *checker(tc.getCheckerCpuPtr());
611
612        tc.getITBPtr()->flushAll();
613        tc.getDTBPtr()->flushAll();
614        if (checker) {
615            checker->getITBPtr()->flushAll();
616            checker->getDTBPtr()->flushAll();
617        }
618    }
619}
620
621
622BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval)
623    : cpu(_cpu), interval(_interval)
624{ }
625
626void
627BaseCPU::ProfileEvent::process()
628{
629    ThreadID size = cpu->threadContexts.size();
630    for (ThreadID i = 0; i < size; ++i) {
631        ThreadContext *tc = cpu->threadContexts[i];
632        tc->profileSample();
633    }
634
635    cpu->schedule(this, curTick() + interval);
636}
637
638void
639BaseCPU::serialize(CheckpointOut &cp) const
640{
641    SERIALIZE_SCALAR(instCnt);
642
643    if (!_switchedOut) {
644        /* Unlike _pid, _taskId is not serialized, as they are dynamically
645         * assigned unique ids that are only meaningful for the duration of
646         * a specific run. We will need to serialize the entire taskMap in
647         * system. */
648        SERIALIZE_SCALAR(_pid);
649
650        interrupts->serialize(cp);
651
652        // Serialize the threads, this is done by the CPU implementation.
653        for (ThreadID i = 0; i < numThreads; ++i) {
654            ScopedCheckpointSection sec(cp, csprintf("xc.%i", i));
655            serializeThread(cp, i);
656        }
657    }
658}
659
660void
661BaseCPU::unserialize(CheckpointIn &cp)
662{
663    UNSERIALIZE_SCALAR(instCnt);
664
665    if (!_switchedOut) {
666        UNSERIALIZE_SCALAR(_pid);
667        interrupts->unserialize(cp);
668
669        // Unserialize the threads, this is done by the CPU implementation.
670        for (ThreadID i = 0; i < numThreads; ++i) {
671            ScopedCheckpointSection sec(cp, csprintf("xc.%i", i));
672            unserializeThread(cp, i);
673        }
674    }
675}
676
677void
678BaseCPU::scheduleInstStop(ThreadID tid, Counter insts, const char *cause)
679{
680    const Tick now(comInstEventQueue[tid]->getCurTick());
681    Event *event(new LocalSimLoopExitEvent(cause, 0));
682
683    comInstEventQueue[tid]->schedule(event, now + insts);
684}
685
686AddressMonitor::AddressMonitor() {
687    armed = false;
688    waiting = false;
689    gotWakeup = false;
690}
691
692bool AddressMonitor::doMonitor(PacketPtr pkt) {
693    assert(pkt->req->hasPaddr());
694    if(armed && waiting) {
695        if(pAddr == pkt->getAddr()) {
696            DPRINTF(Mwait,"pAddr=0x%lx invalidated: waking up core\n",
697                    pkt->getAddr());
698            waiting = false;
699            return true;
700        }
701    }
702    return false;
703}
704
705void
706BaseCPU::scheduleLoadStop(ThreadID tid, Counter loads, const char *cause)
707{
708    const Tick now(comLoadEventQueue[tid]->getCurTick());
709    Event *event(new LocalSimLoopExitEvent(cause, 0));
710
711    comLoadEventQueue[tid]->schedule(event, now + loads);
712}
713
714
715void
716BaseCPU::traceFunctionsInternal(Addr pc)
717{
718    if (!debugSymbolTable)
719        return;
720
721    // if pc enters different function, print new function symbol and
722    // update saved range.  Otherwise do nothing.
723    if (pc < currentFunctionStart || pc >= currentFunctionEnd) {
724        string sym_str;
725        bool found = debugSymbolTable->findNearestSymbol(pc, sym_str,
726                                                         currentFunctionStart,
727                                                         currentFunctionEnd);
728
729        if (!found) {
730            // no symbol found: use addr as label
731            sym_str = csprintf("0x%x", pc);
732            currentFunctionStart = pc;
733            currentFunctionEnd = pc + 1;
734        }
735
736        ccprintf(*functionTraceStream, " (%d)\n%d: %s",
737                 curTick() - functionEntryTick, curTick(), sym_str);
738        functionEntryTick = curTick();
739    }
740}
741