base.cc revision 11050:65fc1db5d795 
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * Copyright (c) 2013 Advanced Micro Devices, Inc.
17 * Copyright (c) 2013 Mark D. Hill and David A. Wood
18 * All rights reserved.
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions are
22 * met: redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer;
24 * redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution;
27 * neither the name of the copyright holders nor the names of its
28 * contributors may be used to endorse or promote products derived from
29 * this software without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 * Authors: Steve Reinhardt
44 *          Nathan Binkert
45 *          Rick Strong
46 */
47
48#include <iostream>
49#include <sstream>
50#include <string>
51
52#include "arch/tlb.hh"
53#include "base/loader/symtab.hh"
54#include "base/cprintf.hh"
55#include "base/misc.hh"
56#include "base/output.hh"
57#include "base/trace.hh"
58#include "cpu/checker/cpu.hh"
59#include "cpu/base.hh"
60#include "cpu/cpuevent.hh"
61#include "cpu/profile.hh"
62#include "cpu/thread_context.hh"
63#include "debug/Mwait.hh"
64#include "debug/SyscallVerbose.hh"
65#include "mem/page_table.hh"
66#include "params/BaseCPU.hh"
67#include "sim/full_system.hh"
68#include "sim/process.hh"
69#include "sim/sim_events.hh"
70#include "sim/sim_exit.hh"
71#include "sim/system.hh"
72
73// Hack
74#include "sim/stat_control.hh"
75
76using namespace std;
77
78vector<BaseCPU *> BaseCPU::cpuList;
79
80// This variable reflects the max number of threads in any CPU.  Be
81// careful to only use it once all the CPUs that you care about have
82// been initialized
83int maxThreadsPerCPU = 1;
84
85CPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival)
86    : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0),
87      cpu(_cpu), _repeatEvent(true)
88{
89    if (_interval)
90        cpu->schedule(this, curTick() + _interval);
91}
92
93void
94CPUProgressEvent::process()
95{
96    Counter temp = cpu->totalOps();
97
98    if (_repeatEvent)
99      cpu->schedule(this, curTick() + _interval);
100
101    if(cpu->switchedOut()) {
102      return;
103    }
104
105#ifndef NDEBUG
106    double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod());
107
108    DPRINTFN("%s progress event, total committed:%i, progress insts committed: "
109             "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst,
110             ipc);
111    ipc = 0.0;
112#else
113    cprintf("%lli: %s progress event, total committed:%i, progress insts "
114            "committed: %lli\n", curTick(), cpu->name(), temp,
115            temp - lastNumInst);
116#endif
117    lastNumInst = temp;
118}
119
120const char *
121CPUProgressEvent::description() const
122{
123    return "CPU Progress";
124}
125
126BaseCPU::BaseCPU(Params *p, bool is_checker)
127    : MemObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id),
128      _instMasterId(p->system->getMasterId(name() + ".inst")),
129      _dataMasterId(p->system->getMasterId(name() + ".data")),
130      _taskId(ContextSwitchTaskId::Unknown), _pid(invldPid),
131      _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()),
132      interrupts(p->interrupts), profileEvent(NULL),
133      numThreads(p->numThreads), system(p->system),
134      functionTraceStream(nullptr), currentFunctionStart(0),
135      currentFunctionEnd(0), functionEntryTick(0),
136      addressMonitor()
137{
138    // if Python did not provide a valid ID, do it here
139    if (_cpuId == -1 ) {
140        _cpuId = cpuList.size();
141    }
142
143    // add self to global list of CPUs
144    cpuList.push_back(this);
145
146    DPRINTF(SyscallVerbose, "Constructing CPU with id %d, socket id %d\n",
147                _cpuId, _socketId);
148
149    if (numThreads > maxThreadsPerCPU)
150        maxThreadsPerCPU = numThreads;
151
152    // allocate per-thread instruction-based event queues
153    comInstEventQueue = new EventQueue *[numThreads];
154    for (ThreadID tid = 0; tid < numThreads; ++tid)
155        comInstEventQueue[tid] =
156            new EventQueue("instruction-based event queue");
157
158    //
159    // set up instruction-count-based termination events, if any
160    //
161    if (p->max_insts_any_thread != 0) {
162        const char *cause = "a thread reached the max instruction count";
163        for (ThreadID tid = 0; tid < numThreads; ++tid)
164            scheduleInstStop(tid, p->max_insts_any_thread, cause);
165    }
166
167    // Set up instruction-count-based termination events for SimPoints
168    // Typically, there are more than one action points.
169    // Simulation.py is responsible to take the necessary actions upon
170    // exitting the simulation loop.
171    if (!p->simpoint_start_insts.empty()) {
172        const char *cause = "simpoint starting point found";
173        for (size_t i = 0; i < p->simpoint_start_insts.size(); ++i)
174            scheduleInstStop(0, p->simpoint_start_insts[i], cause);
175    }
176
177    if (p->max_insts_all_threads != 0) {
178        const char *cause = "all threads reached the max instruction count";
179
180        // allocate & initialize shared downcounter: each event will
181        // decrement this when triggered; simulation will terminate
182        // when counter reaches 0
183        int *counter = new int;
184        *counter = numThreads;
185        for (ThreadID tid = 0; tid < numThreads; ++tid) {
186            Event *event = new CountedExitEvent(cause, *counter);
187            comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads);
188        }
189    }
190
191    // allocate per-thread load-based event queues
192    comLoadEventQueue = new EventQueue *[numThreads];
193    for (ThreadID tid = 0; tid < numThreads; ++tid)
194        comLoadEventQueue[tid] = new EventQueue("load-based event queue");
195
196    //
197    // set up instruction-count-based termination events, if any
198    //
199    if (p->max_loads_any_thread != 0) {
200        const char *cause = "a thread reached the max load count";
201        for (ThreadID tid = 0; tid < numThreads; ++tid)
202            scheduleLoadStop(tid, p->max_loads_any_thread, cause);
203    }
204
205    if (p->max_loads_all_threads != 0) {
206        const char *cause = "all threads reached the max load count";
207        // allocate & initialize shared downcounter: each event will
208        // decrement this when triggered; simulation will terminate
209        // when counter reaches 0
210        int *counter = new int;
211        *counter = numThreads;
212        for (ThreadID tid = 0; tid < numThreads; ++tid) {
213            Event *event = new CountedExitEvent(cause, *counter);
214            comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads);
215        }
216    }
217
218    functionTracingEnabled = false;
219    if (p->function_trace) {
220        const string fname = csprintf("ftrace.%s", name());
221        functionTraceStream = simout.find(fname);
222        if (!functionTraceStream)
223            functionTraceStream = simout.create(fname);
224
225        currentFunctionStart = currentFunctionEnd = 0;
226        functionEntryTick = p->function_trace_start;
227
228        if (p->function_trace_start == 0) {
229            functionTracingEnabled = true;
230        } else {
231            typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap;
232            Event *event = new wrap(this, true);
233            schedule(event, p->function_trace_start);
234        }
235    }
236
237    // The interrupts should always be present unless this CPU is
238    // switched in later or in case it is a checker CPU
239    if (!params()->switched_out && !is_checker) {
240        if (interrupts) {
241            interrupts->setCPU(this);
242        } else {
243            fatal("CPU %s has no interrupt controller.\n"
244                  "Ensure createInterruptController() is called.\n", name());
245        }
246    }
247
248    if (FullSystem) {
249        if (params()->profile)
250            profileEvent = new ProfileEvent(this, params()->profile);
251    }
252    tracer = params()->tracer;
253
254    if (params()->isa.size() != numThreads) {
255        fatal("Number of ISAs (%i) assigned to the CPU does not equal number "
256              "of threads (%i).\n", params()->isa.size(), numThreads);
257    }
258}
259
260void
261BaseCPU::enableFunctionTrace()
262{
263    functionTracingEnabled = true;
264}
265
266BaseCPU::~BaseCPU()
267{
268    delete profileEvent;
269    delete[] comLoadEventQueue;
270    delete[] comInstEventQueue;
271}
272
273void
274BaseCPU::armMonitor(Addr address)
275{
276    addressMonitor.armed = true;
277    addressMonitor.vAddr = address;
278    addressMonitor.pAddr = 0x0;
279    DPRINTF(Mwait,"Armed monitor (vAddr=0x%lx)\n", address);
280}
281
282bool
283BaseCPU::mwait(PacketPtr pkt)
284{
285    if(addressMonitor.gotWakeup == false) {
286        int block_size = cacheLineSize();
287        uint64_t mask = ~((uint64_t)(block_size - 1));
288
289        assert(pkt->req->hasPaddr());
290        addressMonitor.pAddr = pkt->getAddr() & mask;
291        addressMonitor.waiting = true;
292
293        DPRINTF(Mwait,"mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n",
294                addressMonitor.vAddr, addressMonitor.pAddr);
295        return true;
296    } else {
297        addressMonitor.gotWakeup = false;
298        return false;
299    }
300}
301
302void
303BaseCPU::mwaitAtomic(ThreadContext *tc, TheISA::TLB *dtb)
304{
305    Request req;
306    Addr addr = addressMonitor.vAddr;
307    int block_size = cacheLineSize();
308    uint64_t mask = ~((uint64_t)(block_size - 1));
309    int size = block_size;
310
311    //The address of the next line if it crosses a cache line boundary.
312    Addr secondAddr = roundDown(addr + size - 1, block_size);
313
314    if (secondAddr > addr)
315        size = secondAddr - addr;
316
317    req.setVirt(0, addr, size, 0x0, dataMasterId(), tc->instAddr());
318
319    // translate to physical address
320    Fault fault = dtb->translateAtomic(&req, tc, BaseTLB::Read);
321    assert(fault == NoFault);
322
323    addressMonitor.pAddr = req.getPaddr() & mask;
324    addressMonitor.waiting = true;
325
326    DPRINTF(Mwait,"mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n",
327            addressMonitor.vAddr, addressMonitor.pAddr);
328}
329
330void
331BaseCPU::init()
332{
333    if (!params()->switched_out) {
334        registerThreadContexts();
335
336        verifyMemoryMode();
337    }
338}
339
340void
341BaseCPU::startup()
342{
343    if (FullSystem) {
344        if (!params()->switched_out && profileEvent)
345            schedule(profileEvent, curTick());
346    }
347
348    if (params()->progress_interval) {
349        new CPUProgressEvent(this, params()->progress_interval);
350    }
351}
352
353ProbePoints::PMUUPtr
354BaseCPU::pmuProbePoint(const char *name)
355{
356    ProbePoints::PMUUPtr ptr;
357    ptr.reset(new ProbePoints::PMU(getProbeManager(), name));
358
359    return ptr;
360}
361
362void
363BaseCPU::regProbePoints()
364{
365    ppCycles = pmuProbePoint("Cycles");
366
367    ppRetiredInsts = pmuProbePoint("RetiredInsts");
368    ppRetiredLoads = pmuProbePoint("RetiredLoads");
369    ppRetiredStores = pmuProbePoint("RetiredStores");
370    ppRetiredBranches = pmuProbePoint("RetiredBranches");
371}
372
373void
374BaseCPU::probeInstCommit(const StaticInstPtr &inst)
375{
376    if (!inst->isMicroop() || inst->isLastMicroop())
377        ppRetiredInsts->notify(1);
378
379
380    if (inst->isLoad())
381        ppRetiredLoads->notify(1);
382
383    if (inst->isStore())
384        ppRetiredStores->notify(1);
385
386    if (inst->isControl())
387        ppRetiredBranches->notify(1);
388}
389
390void
391BaseCPU::regStats()
392{
393    using namespace Stats;
394
395    numCycles
396        .name(name() + ".numCycles")
397        .desc("number of cpu cycles simulated")
398        ;
399
400    numWorkItemsStarted
401        .name(name() + ".numWorkItemsStarted")
402        .desc("number of work items this cpu started")
403        ;
404
405    numWorkItemsCompleted
406        .name(name() + ".numWorkItemsCompleted")
407        .desc("number of work items this cpu completed")
408        ;
409
410    int size = threadContexts.size();
411    if (size > 1) {
412        for (int i = 0; i < size; ++i) {
413            stringstream namestr;
414            ccprintf(namestr, "%s.ctx%d", name(), i);
415            threadContexts[i]->regStats(namestr.str());
416        }
417    } else if (size == 1)
418        threadContexts[0]->regStats(name());
419}
420
421BaseMasterPort &
422BaseCPU::getMasterPort(const string &if_name, PortID idx)
423{
424    // Get the right port based on name. This applies to all the
425    // subclasses of the base CPU and relies on their implementation
426    // of getDataPort and getInstPort. In all cases there methods
427    // return a MasterPort pointer.
428    if (if_name == "dcache_port")
429        return getDataPort();
430    else if (if_name == "icache_port")
431        return getInstPort();
432    else
433        return MemObject::getMasterPort(if_name, idx);
434}
435
436void
437BaseCPU::registerThreadContexts()
438{
439    ThreadID size = threadContexts.size();
440    for (ThreadID tid = 0; tid < size; ++tid) {
441        ThreadContext *tc = threadContexts[tid];
442
443        /** This is so that contextId and cpuId match where there is a
444         * 1cpu:1context relationship.  Otherwise, the order of registration
445         * could affect the assignment and cpu 1 could have context id 3, for
446         * example.  We may even want to do something like this for SMT so that
447         * cpu 0 has the lowest thread contexts and cpu N has the highest, but
448         * I'll just do this for now
449         */
450        if (numThreads == 1)
451            tc->setContextId(system->registerThreadContext(tc, _cpuId));
452        else
453            tc->setContextId(system->registerThreadContext(tc));
454
455        if (!FullSystem)
456            tc->getProcessPtr()->assignThreadContext(tc->contextId());
457    }
458}
459
460
461int
462BaseCPU::findContext(ThreadContext *tc)
463{
464    ThreadID size = threadContexts.size();
465    for (ThreadID tid = 0; tid < size; ++tid) {
466        if (tc == threadContexts[tid])
467            return tid;
468    }
469    return 0;
470}
471
472void
473BaseCPU::switchOut()
474{
475    assert(!_switchedOut);
476    _switchedOut = true;
477    if (profileEvent && profileEvent->scheduled())
478        deschedule(profileEvent);
479
480    // Flush all TLBs in the CPU to avoid having stale translations if
481    // it gets switched in later.
482    flushTLBs();
483}
484
485void
486BaseCPU::takeOverFrom(BaseCPU *oldCPU)
487{
488    assert(threadContexts.size() == oldCPU->threadContexts.size());
489    assert(_cpuId == oldCPU->cpuId());
490    assert(_switchedOut);
491    assert(oldCPU != this);
492    _pid = oldCPU->getPid();
493    _taskId = oldCPU->taskId();
494    _switchedOut = false;
495
496    ThreadID size = threadContexts.size();
497    for (ThreadID i = 0; i < size; ++i) {
498        ThreadContext *newTC = threadContexts[i];
499        ThreadContext *oldTC = oldCPU->threadContexts[i];
500
501        newTC->takeOverFrom(oldTC);
502
503        CpuEvent::replaceThreadContext(oldTC, newTC);
504
505        assert(newTC->contextId() == oldTC->contextId());
506        assert(newTC->threadId() == oldTC->threadId());
507        system->replaceThreadContext(newTC, newTC->contextId());
508
509        /* This code no longer works since the zero register (e.g.,
510         * r31 on Alpha) doesn't necessarily contain zero at this
511         * point.
512           if (DTRACE(Context))
513            ThreadContext::compare(oldTC, newTC);
514        */
515
516        BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort();
517        BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort();
518        BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort();
519        BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort();
520
521        // Move over any table walker ports if they exist
522        if (new_itb_port) {
523            assert(!new_itb_port->isConnected());
524            assert(old_itb_port);
525            assert(old_itb_port->isConnected());
526            BaseSlavePort &slavePort = old_itb_port->getSlavePort();
527            old_itb_port->unbind();
528            new_itb_port->bind(slavePort);
529        }
530        if (new_dtb_port) {
531            assert(!new_dtb_port->isConnected());
532            assert(old_dtb_port);
533            assert(old_dtb_port->isConnected());
534            BaseSlavePort &slavePort = old_dtb_port->getSlavePort();
535            old_dtb_port->unbind();
536            new_dtb_port->bind(slavePort);
537        }
538        newTC->getITBPtr()->takeOverFrom(oldTC->getITBPtr());
539        newTC->getDTBPtr()->takeOverFrom(oldTC->getDTBPtr());
540
541        // Checker whether or not we have to transfer CheckerCPU
542        // objects over in the switch
543        CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr();
544        CheckerCPU *newChecker = newTC->getCheckerCpuPtr();
545        if (oldChecker && newChecker) {
546            BaseMasterPort *old_checker_itb_port =
547                oldChecker->getITBPtr()->getMasterPort();
548            BaseMasterPort *old_checker_dtb_port =
549                oldChecker->getDTBPtr()->getMasterPort();
550            BaseMasterPort *new_checker_itb_port =
551                newChecker->getITBPtr()->getMasterPort();
552            BaseMasterPort *new_checker_dtb_port =
553                newChecker->getDTBPtr()->getMasterPort();
554
555            newChecker->getITBPtr()->takeOverFrom(oldChecker->getITBPtr());
556            newChecker->getDTBPtr()->takeOverFrom(oldChecker->getDTBPtr());
557
558            // Move over any table walker ports if they exist for checker
559            if (new_checker_itb_port) {
560                assert(!new_checker_itb_port->isConnected());
561                assert(old_checker_itb_port);
562                assert(old_checker_itb_port->isConnected());
563                BaseSlavePort &slavePort =
564                    old_checker_itb_port->getSlavePort();
565                old_checker_itb_port->unbind();
566                new_checker_itb_port->bind(slavePort);
567            }
568            if (new_checker_dtb_port) {
569                assert(!new_checker_dtb_port->isConnected());
570                assert(old_checker_dtb_port);
571                assert(old_checker_dtb_port->isConnected());
572                BaseSlavePort &slavePort =
573                    old_checker_dtb_port->getSlavePort();
574                old_checker_dtb_port->unbind();
575                new_checker_dtb_port->bind(slavePort);
576            }
577        }
578    }
579
580    interrupts = oldCPU->interrupts;
581    interrupts->setCPU(this);
582    oldCPU->interrupts = NULL;
583
584    if (FullSystem) {
585        for (ThreadID i = 0; i < size; ++i)
586            threadContexts[i]->profileClear();
587
588        if (profileEvent)
589            schedule(profileEvent, curTick());
590    }
591
592    // All CPUs have an instruction and a data port, and the new CPU's
593    // ports are dangling while the old CPU has its ports connected
594    // already. Unbind the old CPU and then bind the ports of the one
595    // we are switching to.
596    assert(!getInstPort().isConnected());
597    assert(oldCPU->getInstPort().isConnected());
598    BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort();
599    oldCPU->getInstPort().unbind();
600    getInstPort().bind(inst_peer_port);
601
602    assert(!getDataPort().isConnected());
603    assert(oldCPU->getDataPort().isConnected());
604    BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort();
605    oldCPU->getDataPort().unbind();
606    getDataPort().bind(data_peer_port);
607}
608
609void
610BaseCPU::flushTLBs()
611{
612    for (ThreadID i = 0; i < threadContexts.size(); ++i) {
613        ThreadContext &tc(*threadContexts[i]);
614        CheckerCPU *checker(tc.getCheckerCpuPtr());
615
616        tc.getITBPtr()->flushAll();
617        tc.getDTBPtr()->flushAll();
618        if (checker) {
619            checker->getITBPtr()->flushAll();
620            checker->getDTBPtr()->flushAll();
621        }
622    }
623}
624
625
626BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval)
627    : cpu(_cpu), interval(_interval)
628{ }
629
630void
631BaseCPU::ProfileEvent::process()
632{
633    ThreadID size = cpu->threadContexts.size();
634    for (ThreadID i = 0; i < size; ++i) {
635        ThreadContext *tc = cpu->threadContexts[i];
636        tc->profileSample();
637    }
638
639    cpu->schedule(this, curTick() + interval);
640}
641
642void
643BaseCPU::serialize(CheckpointOut &cp) const
644{
645    SERIALIZE_SCALAR(instCnt);
646
647    if (!_switchedOut) {
648        /* Unlike _pid, _taskId is not serialized, as they are dynamically
649         * assigned unique ids that are only meaningful for the duration of
650         * a specific run. We will need to serialize the entire taskMap in
651         * system. */
652        SERIALIZE_SCALAR(_pid);
653
654        interrupts->serialize(cp);
655
656        // Serialize the threads, this is done by the CPU implementation.
657        for (ThreadID i = 0; i < numThreads; ++i) {
658            ScopedCheckpointSection sec(cp, csprintf("xc.%i", i));
659            serializeThread(cp, i);
660        }
661    }
662}
663
664void
665BaseCPU::unserialize(CheckpointIn &cp)
666{
667    UNSERIALIZE_SCALAR(instCnt);
668
669    if (!_switchedOut) {
670        UNSERIALIZE_SCALAR(_pid);
671        interrupts->unserialize(cp);
672
673        // Unserialize the threads, this is done by the CPU implementation.
674        for (ThreadID i = 0; i < numThreads; ++i) {
675            ScopedCheckpointSection sec(cp, csprintf("xc.%i", i));
676            unserializeThread(cp, i);
677        }
678    }
679}
680
681void
682BaseCPU::scheduleInstStop(ThreadID tid, Counter insts, const char *cause)
683{
684    const Tick now(comInstEventQueue[tid]->getCurTick());
685    Event *event(new LocalSimLoopExitEvent(cause, 0));
686
687    comInstEventQueue[tid]->schedule(event, now + insts);
688}
689
690AddressMonitor::AddressMonitor() {
691    armed = false;
692    waiting = false;
693    gotWakeup = false;
694}
695
696bool AddressMonitor::doMonitor(PacketPtr pkt) {
697    assert(pkt->req->hasPaddr());
698    if(armed && waiting) {
699        if(pAddr == pkt->getAddr()) {
700            DPRINTF(Mwait,"pAddr=0x%lx invalidated: waking up core\n",
701                    pkt->getAddr());
702            waiting = false;
703            return true;
704        }
705    }
706    return false;
707}
708
709void
710BaseCPU::scheduleLoadStop(ThreadID tid, Counter loads, const char *cause)
711{
712    const Tick now(comLoadEventQueue[tid]->getCurTick());
713    Event *event(new LocalSimLoopExitEvent(cause, 0));
714
715    comLoadEventQueue[tid]->schedule(event, now + loads);
716}
717
718
719void
720BaseCPU::traceFunctionsInternal(Addr pc)
721{
722    if (!debugSymbolTable)
723        return;
724
725    // if pc enters different function, print new function symbol and
726    // update saved range.  Otherwise do nothing.
727    if (pc < currentFunctionStart || pc >= currentFunctionEnd) {
728        string sym_str;
729        bool found = debugSymbolTable->findNearestSymbol(pc, sym_str,
730                                                         currentFunctionStart,
731                                                         currentFunctionEnd);
732
733        if (!found) {
734            // no symbol found: use addr as label
735            sym_str = csprintf("0x%x", pc);
736            currentFunctionStart = pc;
737            currentFunctionEnd = pc + 1;
738        }
739
740        ccprintf(*functionTraceStream, " (%d)\n%d: %s",
741                 curTick() - functionEntryTick, curTick(), sym_str);
742        functionEntryTick = curTick();
743    }
744}
745