base.cc revision 9814
12SN/A/* 28922Swilliam.wang@arm.com * Copyright (c) 2011-2012 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Nathan Binkert 437897Shestness@cs.utexas.edu * Rick Strong 442SN/A */ 452SN/A 461388SN/A#include <iostream> 478229Snate@binkert.org#include <sstream> 482SN/A#include <string> 492SN/A 507781SAli.Saidi@ARM.com#include "arch/tlb.hh" 518229Snate@binkert.org#include "base/loader/symtab.hh" 521191SN/A#include "base/cprintf.hh" 531191SN/A#include "base/misc.hh" 541388SN/A#include "base/output.hh" 555529Snate@binkert.org#include "base/trace.hh" 561717SN/A#include "cpu/base.hh" 578887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 582651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 598229Snate@binkert.org#include "cpu/profile.hh" 602680Sktlim@umich.edu#include "cpu/thread_context.hh" 618232Snate@binkert.org#include "debug/SyscallVerbose.hh" 625529Snate@binkert.org#include "params/BaseCPU.hh" 638779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 642190SN/A#include "sim/process.hh" 6556SN/A#include "sim/sim_events.hh" 668229Snate@binkert.org#include "sim/sim_exit.hh" 672190SN/A#include "sim/system.hh" 682SN/A 692359SN/A// Hack 702359SN/A#include "sim/stat_control.hh" 712359SN/A 722SN/Ausing namespace std; 732SN/A 742SN/Avector<BaseCPU *> BaseCPU::cpuList; 752SN/A 762SN/A// This variable reflects the max number of threads in any CPU. Be 772SN/A// careful to only use it once all the CPUs that you care about have 782SN/A// been initialized 792SN/Aint maxThreadsPerCPU = 1; 802SN/A 815606Snate@binkert.orgCPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 826144Sksewell@umich.edu : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 836144Sksewell@umich.edu cpu(_cpu), _repeatEvent(true) 843126Sktlim@umich.edu{ 856144Sksewell@umich.edu if (_interval) 867823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 873126Sktlim@umich.edu} 883126Sktlim@umich.edu 892356SN/Avoid 902356SN/ACPUProgressEvent::process() 912356SN/A{ 928834Satgutier@umich.edu Counter temp = cpu->totalOps(); 932356SN/A#ifndef NDEBUG 949179Sandreas.hansson@arm.com double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod()); 952367SN/A 966144Sksewell@umich.edu DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 976144Sksewell@umich.edu "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 986144Sksewell@umich.edu ipc); 992356SN/A ipc = 0.0; 1002367SN/A#else 1016144Sksewell@umich.edu cprintf("%lli: %s progress event, total committed:%i, progress insts " 1027823Ssteve.reinhardt@amd.com "committed: %lli\n", curTick(), cpu->name(), temp, 1036144Sksewell@umich.edu temp - lastNumInst); 1042367SN/A#endif 1052356SN/A lastNumInst = temp; 1066144Sksewell@umich.edu 1076144Sksewell@umich.edu if (_repeatEvent) 1087823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 1092356SN/A} 1102356SN/A 1112356SN/Aconst char * 1125336Shines@cs.fsu.eduCPUProgressEvent::description() const 1132356SN/A{ 1144873Sstever@eecs.umich.edu return "CPU Progress"; 1152356SN/A} 1162356SN/A 1178876Sandreas.hansson@arm.comBaseCPU::BaseCPU(Params *p, bool is_checker) 1189157Sandreas.hansson@arm.com : MemObject(p), instCnt(0), _cpuId(p->cpu_id), 1198832SAli.Saidi@ARM.com _instMasterId(p->system->getMasterId(name() + ".inst")), 1208832SAli.Saidi@ARM.com _dataMasterId(p->system->getMasterId(name() + ".data")), 1219332Sdam.sunwoo@arm.com _taskId(ContextSwitchTaskId::Unknown), _pid(Request::invldPid), 1229814Sandreas.hansson@arm.com _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()), 1239220Shestness@cs.wisc.edu interrupts(p->interrupts), profileEvent(NULL), 1249157Sandreas.hansson@arm.com numThreads(p->numThreads), system(p->system) 1252SN/A{ 1265712Shsul@eecs.umich.edu // if Python did not provide a valid ID, do it here 1275712Shsul@eecs.umich.edu if (_cpuId == -1 ) { 1285712Shsul@eecs.umich.edu _cpuId = cpuList.size(); 1295712Shsul@eecs.umich.edu } 1305712Shsul@eecs.umich.edu 1312SN/A // add self to global list of CPUs 1322SN/A cpuList.push_back(this); 1332SN/A 1345712Shsul@eecs.umich.edu DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId); 1355712Shsul@eecs.umich.edu 1366221Snate@binkert.org if (numThreads > maxThreadsPerCPU) 1376221Snate@binkert.org maxThreadsPerCPU = numThreads; 1382SN/A 1392SN/A // allocate per-thread instruction-based event queues 1406221Snate@binkert.org comInstEventQueue = new EventQueue *[numThreads]; 1416221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1426221Snate@binkert.org comInstEventQueue[tid] = 1436221Snate@binkert.org new EventQueue("instruction-based event queue"); 1442SN/A 1452SN/A // 1462SN/A // set up instruction-count-based termination events, if any 1472SN/A // 1485606Snate@binkert.org if (p->max_insts_any_thread != 0) { 1495606Snate@binkert.org const char *cause = "a thread reached the max instruction count"; 1509749Sandreas@sandberg.pp.se for (ThreadID tid = 0; tid < numThreads; ++tid) 1519749Sandreas@sandberg.pp.se scheduleInstStop(tid, p->max_insts_any_thread, cause); 1525606Snate@binkert.org } 1532SN/A 1549647Sdam.sunwoo@arm.com // Set up instruction-count-based termination events for SimPoints 1559647Sdam.sunwoo@arm.com // Typically, there are more than one action points. 1569647Sdam.sunwoo@arm.com // Simulation.py is responsible to take the necessary actions upon 1579647Sdam.sunwoo@arm.com // exitting the simulation loop. 1589647Sdam.sunwoo@arm.com if (!p->simpoint_start_insts.empty()) { 1599647Sdam.sunwoo@arm.com const char *cause = "simpoint starting point found"; 1609749Sandreas@sandberg.pp.se for (size_t i = 0; i < p->simpoint_start_insts.size(); ++i) 1619749Sandreas@sandberg.pp.se scheduleInstStop(0, p->simpoint_start_insts[i], cause); 1629647Sdam.sunwoo@arm.com } 1639647Sdam.sunwoo@arm.com 1641400SN/A if (p->max_insts_all_threads != 0) { 1655606Snate@binkert.org const char *cause = "all threads reached the max instruction count"; 1665606Snate@binkert.org 1672SN/A // allocate & initialize shared downcounter: each event will 1682SN/A // decrement this when triggered; simulation will terminate 1692SN/A // when counter reaches 0 1702SN/A int *counter = new int; 1716221Snate@binkert.org *counter = numThreads; 1726221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1735606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1746670Shsul@eecs.umich.edu comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 1755606Snate@binkert.org } 1762SN/A } 1772SN/A 178124SN/A // allocate per-thread load-based event queues 1796221Snate@binkert.org comLoadEventQueue = new EventQueue *[numThreads]; 1806221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1816221Snate@binkert.org comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 182124SN/A 183124SN/A // 184124SN/A // set up instruction-count-based termination events, if any 185124SN/A // 1865606Snate@binkert.org if (p->max_loads_any_thread != 0) { 1875606Snate@binkert.org const char *cause = "a thread reached the max load count"; 1889749Sandreas@sandberg.pp.se for (ThreadID tid = 0; tid < numThreads; ++tid) 1899749Sandreas@sandberg.pp.se scheduleLoadStop(tid, p->max_loads_any_thread, cause); 1905606Snate@binkert.org } 191124SN/A 1921400SN/A if (p->max_loads_all_threads != 0) { 1935606Snate@binkert.org const char *cause = "all threads reached the max load count"; 194124SN/A // allocate & initialize shared downcounter: each event will 195124SN/A // decrement this when triggered; simulation will terminate 196124SN/A // when counter reaches 0 197124SN/A int *counter = new int; 1986221Snate@binkert.org *counter = numThreads; 1996221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 2005606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 2016221Snate@binkert.org comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 2025606Snate@binkert.org } 203124SN/A } 204124SN/A 2051191SN/A functionTracingEnabled = false; 2065529Snate@binkert.org if (p->function_trace) { 2078634Schris.emmons@arm.com const string fname = csprintf("ftrace.%s", name()); 2088634Schris.emmons@arm.com functionTraceStream = simout.find(fname); 2098634Schris.emmons@arm.com if (!functionTraceStream) 2108634Schris.emmons@arm.com functionTraceStream = simout.create(fname); 2118634Schris.emmons@arm.com 2121191SN/A currentFunctionStart = currentFunctionEnd = 0; 2135529Snate@binkert.org functionEntryTick = p->function_trace_start; 2141191SN/A 2155529Snate@binkert.org if (p->function_trace_start == 0) { 2161191SN/A functionTracingEnabled = true; 2171191SN/A } else { 2185606Snate@binkert.org typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap; 2195606Snate@binkert.org Event *event = new wrap(this, true); 2205606Snate@binkert.org schedule(event, p->function_trace_start); 2211191SN/A } 2221191SN/A } 2238876Sandreas.hansson@arm.com 2248876Sandreas.hansson@arm.com // The interrupts should always be present unless this CPU is 2258876Sandreas.hansson@arm.com // switched in later or in case it is a checker CPU 2269433SAndreas.Sandberg@ARM.com if (!params()->switched_out && !is_checker) { 2278876Sandreas.hansson@arm.com if (interrupts) { 2288876Sandreas.hansson@arm.com interrupts->setCPU(this); 2298876Sandreas.hansson@arm.com } else { 2308876Sandreas.hansson@arm.com fatal("CPU %s has no interrupt controller.\n" 2318876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 2328876Sandreas.hansson@arm.com } 2338876Sandreas.hansson@arm.com } 2345810Sgblack@eecs.umich.edu 2358779Sgblack@eecs.umich.edu if (FullSystem) { 2368779Sgblack@eecs.umich.edu if (params()->profile) 2378779Sgblack@eecs.umich.edu profileEvent = new ProfileEvent(this, params()->profile); 2388779Sgblack@eecs.umich.edu } 2395529Snate@binkert.org tracer = params()->tracer; 2409384SAndreas.Sandberg@arm.com 2419384SAndreas.Sandberg@arm.com if (params()->isa.size() != numThreads) { 2429384SAndreas.Sandberg@arm.com fatal("Number of ISAs (%i) assigned to the CPU does not equal number " 2439384SAndreas.Sandberg@arm.com "of threads (%i).\n", params()->isa.size(), numThreads); 2449384SAndreas.Sandberg@arm.com } 2451917SN/A} 2461191SN/A 2471191SN/Avoid 2481191SN/ABaseCPU::enableFunctionTrace() 2491191SN/A{ 2501191SN/A functionTracingEnabled = true; 2511191SN/A} 2521191SN/A 2531191SN/ABaseCPU::~BaseCPU() 2541191SN/A{ 2559086Sandreas.hansson@arm.com delete profileEvent; 2569086Sandreas.hansson@arm.com delete[] comLoadEventQueue; 2579086Sandreas.hansson@arm.com delete[] comInstEventQueue; 2581191SN/A} 2591191SN/A 2601129SN/Avoid 2611129SN/ABaseCPU::init() 2621129SN/A{ 2639523SAndreas.Sandberg@ARM.com if (!params()->switched_out) { 2642680Sktlim@umich.edu registerThreadContexts(); 2659523SAndreas.Sandberg@ARM.com 2669523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 2679523SAndreas.Sandberg@ARM.com } 2681129SN/A} 269180SN/A 2702SN/Avoid 2711917SN/ABaseCPU::startup() 2721917SN/A{ 2738779Sgblack@eecs.umich.edu if (FullSystem) { 2749433SAndreas.Sandberg@ARM.com if (!params()->switched_out && profileEvent) 2758779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 2768779Sgblack@eecs.umich.edu } 2772356SN/A 2785529Snate@binkert.org if (params()->progress_interval) { 2799179Sandreas.hansson@arm.com new CPUProgressEvent(this, params()->progress_interval); 2802356SN/A } 2811917SN/A} 2821917SN/A 2831917SN/A 2841917SN/Avoid 2852SN/ABaseCPU::regStats() 2862SN/A{ 287729SN/A using namespace Stats; 288707SN/A 289707SN/A numCycles 290707SN/A .name(name() + ".numCycles") 291707SN/A .desc("number of cpu cycles simulated") 292707SN/A ; 293707SN/A 2947914SBrad.Beckmann@amd.com numWorkItemsStarted 2957914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsStarted") 2967914SBrad.Beckmann@amd.com .desc("number of work items this cpu started") 2977914SBrad.Beckmann@amd.com ; 2987914SBrad.Beckmann@amd.com 2997914SBrad.Beckmann@amd.com numWorkItemsCompleted 3007914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsCompleted") 3017914SBrad.Beckmann@amd.com .desc("number of work items this cpu completed") 3027914SBrad.Beckmann@amd.com ; 3037914SBrad.Beckmann@amd.com 3042680Sktlim@umich.edu int size = threadContexts.size(); 3052SN/A if (size > 1) { 3062SN/A for (int i = 0; i < size; ++i) { 3072SN/A stringstream namestr; 3082SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 3092680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 3102SN/A } 3112SN/A } else if (size == 1) 3122680Sktlim@umich.edu threadContexts[0]->regStats(name()); 3132SN/A} 3142SN/A 3159294Sandreas.hansson@arm.comBaseMasterPort & 3169294Sandreas.hansson@arm.comBaseCPU::getMasterPort(const string &if_name, PortID idx) 3178850Sandreas.hansson@arm.com{ 3188850Sandreas.hansson@arm.com // Get the right port based on name. This applies to all the 3198850Sandreas.hansson@arm.com // subclasses of the base CPU and relies on their implementation 3208850Sandreas.hansson@arm.com // of getDataPort and getInstPort. In all cases there methods 3219608Sandreas.hansson@arm.com // return a MasterPort pointer. 3228850Sandreas.hansson@arm.com if (if_name == "dcache_port") 3238922Swilliam.wang@arm.com return getDataPort(); 3248850Sandreas.hansson@arm.com else if (if_name == "icache_port") 3258922Swilliam.wang@arm.com return getInstPort(); 3268850Sandreas.hansson@arm.com else 3278922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 3288850Sandreas.hansson@arm.com} 3298850Sandreas.hansson@arm.com 330180SN/Avoid 3312680Sktlim@umich.eduBaseCPU::registerThreadContexts() 332180SN/A{ 3336221Snate@binkert.org ThreadID size = threadContexts.size(); 3346221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 3356221Snate@binkert.org ThreadContext *tc = threadContexts[tid]; 3362378SN/A 3375718Shsul@eecs.umich.edu /** This is so that contextId and cpuId match where there is a 3385718Shsul@eecs.umich.edu * 1cpu:1context relationship. Otherwise, the order of registration 3395718Shsul@eecs.umich.edu * could affect the assignment and cpu 1 could have context id 3, for 3405718Shsul@eecs.umich.edu * example. We may even want to do something like this for SMT so that 3415718Shsul@eecs.umich.edu * cpu 0 has the lowest thread contexts and cpu N has the highest, but 3425718Shsul@eecs.umich.edu * I'll just do this for now 3435718Shsul@eecs.umich.edu */ 3446221Snate@binkert.org if (numThreads == 1) 3455718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc, _cpuId)); 3465718Shsul@eecs.umich.edu else 3475718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc)); 3488779Sgblack@eecs.umich.edu 3498779Sgblack@eecs.umich.edu if (!FullSystem) 3508779Sgblack@eecs.umich.edu tc->getProcessPtr()->assignThreadContext(tc->contextId()); 351180SN/A } 352180SN/A} 353180SN/A 354180SN/A 3554000Ssaidi@eecs.umich.eduint 3564000Ssaidi@eecs.umich.eduBaseCPU::findContext(ThreadContext *tc) 3574000Ssaidi@eecs.umich.edu{ 3586221Snate@binkert.org ThreadID size = threadContexts.size(); 3596221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 3606221Snate@binkert.org if (tc == threadContexts[tid]) 3616221Snate@binkert.org return tid; 3624000Ssaidi@eecs.umich.edu } 3634000Ssaidi@eecs.umich.edu return 0; 3644000Ssaidi@eecs.umich.edu} 3654000Ssaidi@eecs.umich.edu 366180SN/Avoid 3672798Sktlim@umich.eduBaseCPU::switchOut() 368180SN/A{ 3699430SAndreas.Sandberg@ARM.com assert(!_switchedOut); 3709430SAndreas.Sandberg@ARM.com _switchedOut = true; 3712359SN/A if (profileEvent && profileEvent->scheduled()) 3725606Snate@binkert.org deschedule(profileEvent); 3739446SAndreas.Sandberg@ARM.com 3749446SAndreas.Sandberg@ARM.com // Flush all TLBs in the CPU to avoid having stale translations if 3759446SAndreas.Sandberg@ARM.com // it gets switched in later. 3769446SAndreas.Sandberg@ARM.com flushTLBs(); 377180SN/A} 378180SN/A 379180SN/Avoid 3808737Skoansin.tan@gmail.comBaseCPU::takeOverFrom(BaseCPU *oldCPU) 381180SN/A{ 3822680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 3839152Satgutier@umich.edu assert(_cpuId == oldCPU->cpuId()); 3849430SAndreas.Sandberg@ARM.com assert(_switchedOut); 3859430SAndreas.Sandberg@ARM.com assert(oldCPU != this); 3869332Sdam.sunwoo@arm.com _pid = oldCPU->getPid(); 3879332Sdam.sunwoo@arm.com _taskId = oldCPU->taskId(); 3889430SAndreas.Sandberg@ARM.com _switchedOut = false; 3895712Shsul@eecs.umich.edu 3906221Snate@binkert.org ThreadID size = threadContexts.size(); 3916221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 3922680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 3932680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 394180SN/A 3952680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 3962651Ssaidi@eecs.umich.edu 3972680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 3982651Ssaidi@eecs.umich.edu 3995714Shsul@eecs.umich.edu assert(newTC->contextId() == oldTC->contextId()); 4005715Shsul@eecs.umich.edu assert(newTC->threadId() == oldTC->threadId()); 4015714Shsul@eecs.umich.edu system->replaceThreadContext(newTC, newTC->contextId()); 4022359SN/A 4035875Ssteve.reinhardt@amd.com /* This code no longer works since the zero register (e.g., 4045875Ssteve.reinhardt@amd.com * r31 on Alpha) doesn't necessarily contain zero at this 4055875Ssteve.reinhardt@amd.com * point. 4065875Ssteve.reinhardt@amd.com if (DTRACE(Context)) 4075217Ssaidi@eecs.umich.edu ThreadContext::compare(oldTC, newTC); 4085875Ssteve.reinhardt@amd.com */ 4097781SAli.Saidi@ARM.com 4109294Sandreas.hansson@arm.com BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort(); 4119294Sandreas.hansson@arm.com BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort(); 4129294Sandreas.hansson@arm.com BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort(); 4139294Sandreas.hansson@arm.com BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort(); 4147781SAli.Saidi@ARM.com 4157781SAli.Saidi@ARM.com // Move over any table walker ports if they exist 4169178Sandreas.hansson@arm.com if (new_itb_port) { 4179178Sandreas.hansson@arm.com assert(!new_itb_port->isConnected()); 4187781SAli.Saidi@ARM.com assert(old_itb_port); 4199178Sandreas.hansson@arm.com assert(old_itb_port->isConnected()); 4209294Sandreas.hansson@arm.com BaseSlavePort &slavePort = old_itb_port->getSlavePort(); 4219178Sandreas.hansson@arm.com old_itb_port->unbind(); 4228922Swilliam.wang@arm.com new_itb_port->bind(slavePort); 4237781SAli.Saidi@ARM.com } 4249178Sandreas.hansson@arm.com if (new_dtb_port) { 4259178Sandreas.hansson@arm.com assert(!new_dtb_port->isConnected()); 4267781SAli.Saidi@ARM.com assert(old_dtb_port); 4279178Sandreas.hansson@arm.com assert(old_dtb_port->isConnected()); 4289294Sandreas.hansson@arm.com BaseSlavePort &slavePort = old_dtb_port->getSlavePort(); 4299178Sandreas.hansson@arm.com old_dtb_port->unbind(); 4308922Swilliam.wang@arm.com new_dtb_port->bind(slavePort); 4317781SAli.Saidi@ARM.com } 4328733Sgeoffrey.blake@arm.com 4338887Sgeoffrey.blake@arm.com // Checker whether or not we have to transfer CheckerCPU 4348887Sgeoffrey.blake@arm.com // objects over in the switch 4358887Sgeoffrey.blake@arm.com CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr(); 4368887Sgeoffrey.blake@arm.com CheckerCPU *newChecker = newTC->getCheckerCpuPtr(); 4378887Sgeoffrey.blake@arm.com if (oldChecker && newChecker) { 4389294Sandreas.hansson@arm.com BaseMasterPort *old_checker_itb_port = 4398922Swilliam.wang@arm.com oldChecker->getITBPtr()->getMasterPort(); 4409294Sandreas.hansson@arm.com BaseMasterPort *old_checker_dtb_port = 4418922Swilliam.wang@arm.com oldChecker->getDTBPtr()->getMasterPort(); 4429294Sandreas.hansson@arm.com BaseMasterPort *new_checker_itb_port = 4438922Swilliam.wang@arm.com newChecker->getITBPtr()->getMasterPort(); 4449294Sandreas.hansson@arm.com BaseMasterPort *new_checker_dtb_port = 4458922Swilliam.wang@arm.com newChecker->getDTBPtr()->getMasterPort(); 4468733Sgeoffrey.blake@arm.com 4478887Sgeoffrey.blake@arm.com // Move over any table walker ports if they exist for checker 4489178Sandreas.hansson@arm.com if (new_checker_itb_port) { 4499178Sandreas.hansson@arm.com assert(!new_checker_itb_port->isConnected()); 4508887Sgeoffrey.blake@arm.com assert(old_checker_itb_port); 4519178Sandreas.hansson@arm.com assert(old_checker_itb_port->isConnected()); 4529294Sandreas.hansson@arm.com BaseSlavePort &slavePort = 4539294Sandreas.hansson@arm.com old_checker_itb_port->getSlavePort(); 4549178Sandreas.hansson@arm.com old_checker_itb_port->unbind(); 4558922Swilliam.wang@arm.com new_checker_itb_port->bind(slavePort); 4568887Sgeoffrey.blake@arm.com } 4579178Sandreas.hansson@arm.com if (new_checker_dtb_port) { 4589178Sandreas.hansson@arm.com assert(!new_checker_dtb_port->isConnected()); 4598887Sgeoffrey.blake@arm.com assert(old_checker_dtb_port); 4609178Sandreas.hansson@arm.com assert(old_checker_dtb_port->isConnected()); 4619294Sandreas.hansson@arm.com BaseSlavePort &slavePort = 4629294Sandreas.hansson@arm.com old_checker_dtb_port->getSlavePort(); 4639178Sandreas.hansson@arm.com old_checker_dtb_port->unbind(); 4648922Swilliam.wang@arm.com new_checker_dtb_port->bind(slavePort); 4658887Sgeoffrey.blake@arm.com } 4668733Sgeoffrey.blake@arm.com } 467180SN/A } 468605SN/A 4693520Sgblack@eecs.umich.edu interrupts = oldCPU->interrupts; 4705810Sgblack@eecs.umich.edu interrupts->setCPU(this); 4719152Satgutier@umich.edu oldCPU->interrupts = NULL; 4722254SN/A 4738779Sgblack@eecs.umich.edu if (FullSystem) { 4748779Sgblack@eecs.umich.edu for (ThreadID i = 0; i < size; ++i) 4758779Sgblack@eecs.umich.edu threadContexts[i]->profileClear(); 4762254SN/A 4778779Sgblack@eecs.umich.edu if (profileEvent) 4788779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 4798779Sgblack@eecs.umich.edu } 4804192Sktlim@umich.edu 4819178Sandreas.hansson@arm.com // All CPUs have an instruction and a data port, and the new CPU's 4829178Sandreas.hansson@arm.com // ports are dangling while the old CPU has its ports connected 4839178Sandreas.hansson@arm.com // already. Unbind the old CPU and then bind the ports of the one 4849178Sandreas.hansson@arm.com // we are switching to. 4859178Sandreas.hansson@arm.com assert(!getInstPort().isConnected()); 4869178Sandreas.hansson@arm.com assert(oldCPU->getInstPort().isConnected()); 4879294Sandreas.hansson@arm.com BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort(); 4889178Sandreas.hansson@arm.com oldCPU->getInstPort().unbind(); 4899178Sandreas.hansson@arm.com getInstPort().bind(inst_peer_port); 4904192Sktlim@umich.edu 4919178Sandreas.hansson@arm.com assert(!getDataPort().isConnected()); 4929178Sandreas.hansson@arm.com assert(oldCPU->getDataPort().isConnected()); 4939294Sandreas.hansson@arm.com BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort(); 4949178Sandreas.hansson@arm.com oldCPU->getDataPort().unbind(); 4959178Sandreas.hansson@arm.com getDataPort().bind(data_peer_port); 496180SN/A} 497180SN/A 4989446SAndreas.Sandberg@ARM.comvoid 4999446SAndreas.Sandberg@ARM.comBaseCPU::flushTLBs() 5009446SAndreas.Sandberg@ARM.com{ 5019446SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < threadContexts.size(); ++i) { 5029446SAndreas.Sandberg@ARM.com ThreadContext &tc(*threadContexts[i]); 5039446SAndreas.Sandberg@ARM.com CheckerCPU *checker(tc.getCheckerCpuPtr()); 5049446SAndreas.Sandberg@ARM.com 5059446SAndreas.Sandberg@ARM.com tc.getITBPtr()->flushAll(); 5069446SAndreas.Sandberg@ARM.com tc.getDTBPtr()->flushAll(); 5079446SAndreas.Sandberg@ARM.com if (checker) { 5089446SAndreas.Sandberg@ARM.com checker->getITBPtr()->flushAll(); 5099446SAndreas.Sandberg@ARM.com checker->getDTBPtr()->flushAll(); 5109446SAndreas.Sandberg@ARM.com } 5119446SAndreas.Sandberg@ARM.com } 5129446SAndreas.Sandberg@ARM.com} 5139446SAndreas.Sandberg@ARM.com 514180SN/A 5155536Srstrong@hp.comBaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval) 5165606Snate@binkert.org : cpu(_cpu), interval(_interval) 5171917SN/A{ } 5181917SN/A 5191917SN/Avoid 5201917SN/ABaseCPU::ProfileEvent::process() 5211917SN/A{ 5226221Snate@binkert.org ThreadID size = cpu->threadContexts.size(); 5236221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 5242680Sktlim@umich.edu ThreadContext *tc = cpu->threadContexts[i]; 5252680Sktlim@umich.edu tc->profileSample(); 5261917SN/A } 5272254SN/A 5287823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + interval); 5291917SN/A} 5301917SN/A 5312SN/Avoid 532921SN/ABaseCPU::serialize(std::ostream &os) 533921SN/A{ 5344000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(instCnt); 5359332Sdam.sunwoo@arm.com 5369448SAndreas.Sandberg@ARM.com if (!_switchedOut) { 5379448SAndreas.Sandberg@ARM.com /* Unlike _pid, _taskId is not serialized, as they are dynamically 5389448SAndreas.Sandberg@ARM.com * assigned unique ids that are only meaningful for the duration of 5399448SAndreas.Sandberg@ARM.com * a specific run. We will need to serialize the entire taskMap in 5409448SAndreas.Sandberg@ARM.com * system. */ 5419448SAndreas.Sandberg@ARM.com SERIALIZE_SCALAR(_pid); 5429332Sdam.sunwoo@arm.com 5439448SAndreas.Sandberg@ARM.com interrupts->serialize(os); 5449448SAndreas.Sandberg@ARM.com 5459448SAndreas.Sandberg@ARM.com // Serialize the threads, this is done by the CPU implementation. 5469448SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < numThreads; ++i) { 5479448SAndreas.Sandberg@ARM.com nameOut(os, csprintf("%s.xc.%i", name(), i)); 5489448SAndreas.Sandberg@ARM.com serializeThread(os, i); 5499448SAndreas.Sandberg@ARM.com } 5509448SAndreas.Sandberg@ARM.com } 551921SN/A} 552921SN/A 553921SN/Avoid 554921SN/ABaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 555921SN/A{ 5564000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(instCnt); 5579448SAndreas.Sandberg@ARM.com 5589448SAndreas.Sandberg@ARM.com if (!_switchedOut) { 5599448SAndreas.Sandberg@ARM.com UNSERIALIZE_SCALAR(_pid); 5609448SAndreas.Sandberg@ARM.com interrupts->unserialize(cp, section); 5619448SAndreas.Sandberg@ARM.com 5629448SAndreas.Sandberg@ARM.com // Unserialize the threads, this is done by the CPU implementation. 5639448SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < numThreads; ++i) 5649448SAndreas.Sandberg@ARM.com unserializeThread(cp, csprintf("%s.xc.%i", section, i), i); 5659448SAndreas.Sandberg@ARM.com } 566921SN/A} 567921SN/A 5681191SN/Avoid 5699749Sandreas@sandberg.pp.seBaseCPU::scheduleInstStop(ThreadID tid, Counter insts, const char *cause) 5709749Sandreas@sandberg.pp.se{ 5719749Sandreas@sandberg.pp.se const Tick now(comInstEventQueue[tid]->getCurTick()); 5729749Sandreas@sandberg.pp.se Event *event(new SimLoopExitEvent(cause, 0)); 5739749Sandreas@sandberg.pp.se 5749749Sandreas@sandberg.pp.se comInstEventQueue[tid]->schedule(event, now + insts); 5759749Sandreas@sandberg.pp.se} 5769749Sandreas@sandberg.pp.se 5779749Sandreas@sandberg.pp.sevoid 5789749Sandreas@sandberg.pp.seBaseCPU::scheduleLoadStop(ThreadID tid, Counter loads, const char *cause) 5799749Sandreas@sandberg.pp.se{ 5809749Sandreas@sandberg.pp.se const Tick now(comLoadEventQueue[tid]->getCurTick()); 5819749Sandreas@sandberg.pp.se Event *event(new SimLoopExitEvent(cause, 0)); 5829749Sandreas@sandberg.pp.se 5839749Sandreas@sandberg.pp.se comLoadEventQueue[tid]->schedule(event, now + loads); 5849749Sandreas@sandberg.pp.se} 5859749Sandreas@sandberg.pp.se 5869749Sandreas@sandberg.pp.se 5879749Sandreas@sandberg.pp.sevoid 5881191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 5891191SN/A{ 5901191SN/A if (!debugSymbolTable) 5911191SN/A return; 5921191SN/A 5931191SN/A // if pc enters different function, print new function symbol and 5941191SN/A // update saved range. Otherwise do nothing. 5951191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 5961191SN/A string sym_str; 5971191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 5981191SN/A currentFunctionStart, 5991191SN/A currentFunctionEnd); 6001191SN/A 6011191SN/A if (!found) { 6021191SN/A // no symbol found: use addr as label 6031191SN/A sym_str = csprintf("0x%x", pc); 6041191SN/A currentFunctionStart = pc; 6051191SN/A currentFunctionEnd = pc + 1; 6061191SN/A } 6071191SN/A 6081191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 6097823Ssteve.reinhardt@amd.com curTick() - functionEntryTick, curTick(), sym_str); 6107823Ssteve.reinhardt@amd.com functionEntryTick = curTick(); 6111191SN/A } 6121191SN/A} 613