base.cc revision 9647
12SN/A/* 28922Swilliam.wang@arm.com * Copyright (c) 2011-2012 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Nathan Binkert 437897Shestness@cs.utexas.edu * Rick Strong 442SN/A */ 452SN/A 461388SN/A#include <iostream> 478229Snate@binkert.org#include <sstream> 482SN/A#include <string> 492SN/A 507781SAli.Saidi@ARM.com#include "arch/tlb.hh" 518229Snate@binkert.org#include "base/loader/symtab.hh" 521191SN/A#include "base/cprintf.hh" 531191SN/A#include "base/misc.hh" 541388SN/A#include "base/output.hh" 555529Snate@binkert.org#include "base/trace.hh" 561717SN/A#include "cpu/base.hh" 578887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 582651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 598229Snate@binkert.org#include "cpu/profile.hh" 602680Sktlim@umich.edu#include "cpu/thread_context.hh" 618232Snate@binkert.org#include "debug/SyscallVerbose.hh" 625529Snate@binkert.org#include "params/BaseCPU.hh" 638779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 642190SN/A#include "sim/process.hh" 6556SN/A#include "sim/sim_events.hh" 668229Snate@binkert.org#include "sim/sim_exit.hh" 672190SN/A#include "sim/system.hh" 682SN/A 692359SN/A// Hack 702359SN/A#include "sim/stat_control.hh" 712359SN/A 722SN/Ausing namespace std; 732SN/A 742SN/Avector<BaseCPU *> BaseCPU::cpuList; 752SN/A 762SN/A// This variable reflects the max number of threads in any CPU. Be 772SN/A// careful to only use it once all the CPUs that you care about have 782SN/A// been initialized 792SN/Aint maxThreadsPerCPU = 1; 802SN/A 815606Snate@binkert.orgCPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 826144Sksewell@umich.edu : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 836144Sksewell@umich.edu cpu(_cpu), _repeatEvent(true) 843126Sktlim@umich.edu{ 856144Sksewell@umich.edu if (_interval) 867823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 873126Sktlim@umich.edu} 883126Sktlim@umich.edu 892356SN/Avoid 902356SN/ACPUProgressEvent::process() 912356SN/A{ 928834Satgutier@umich.edu Counter temp = cpu->totalOps(); 932356SN/A#ifndef NDEBUG 949179Sandreas.hansson@arm.com double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod()); 952367SN/A 966144Sksewell@umich.edu DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 976144Sksewell@umich.edu "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 986144Sksewell@umich.edu ipc); 992356SN/A ipc = 0.0; 1002367SN/A#else 1016144Sksewell@umich.edu cprintf("%lli: %s progress event, total committed:%i, progress insts " 1027823Ssteve.reinhardt@amd.com "committed: %lli\n", curTick(), cpu->name(), temp, 1036144Sksewell@umich.edu temp - lastNumInst); 1042367SN/A#endif 1052356SN/A lastNumInst = temp; 1066144Sksewell@umich.edu 1076144Sksewell@umich.edu if (_repeatEvent) 1087823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 1092356SN/A} 1102356SN/A 1112356SN/Aconst char * 1125336Shines@cs.fsu.eduCPUProgressEvent::description() const 1132356SN/A{ 1144873Sstever@eecs.umich.edu return "CPU Progress"; 1152356SN/A} 1162356SN/A 1178876Sandreas.hansson@arm.comBaseCPU::BaseCPU(Params *p, bool is_checker) 1189157Sandreas.hansson@arm.com : MemObject(p), instCnt(0), _cpuId(p->cpu_id), 1198832SAli.Saidi@ARM.com _instMasterId(p->system->getMasterId(name() + ".inst")), 1208832SAli.Saidi@ARM.com _dataMasterId(p->system->getMasterId(name() + ".data")), 1219332Sdam.sunwoo@arm.com _taskId(ContextSwitchTaskId::Unknown), _pid(Request::invldPid), 1229433SAndreas.Sandberg@ARM.com _switchedOut(p->switched_out), 1239220Shestness@cs.wisc.edu interrupts(p->interrupts), profileEvent(NULL), 1249157Sandreas.hansson@arm.com numThreads(p->numThreads), system(p->system) 1252SN/A{ 1265712Shsul@eecs.umich.edu // if Python did not provide a valid ID, do it here 1275712Shsul@eecs.umich.edu if (_cpuId == -1 ) { 1285712Shsul@eecs.umich.edu _cpuId = cpuList.size(); 1295712Shsul@eecs.umich.edu } 1305712Shsul@eecs.umich.edu 1312SN/A // add self to global list of CPUs 1322SN/A cpuList.push_back(this); 1332SN/A 1345712Shsul@eecs.umich.edu DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId); 1355712Shsul@eecs.umich.edu 1366221Snate@binkert.org if (numThreads > maxThreadsPerCPU) 1376221Snate@binkert.org maxThreadsPerCPU = numThreads; 1382SN/A 1392SN/A // allocate per-thread instruction-based event queues 1406221Snate@binkert.org comInstEventQueue = new EventQueue *[numThreads]; 1416221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1426221Snate@binkert.org comInstEventQueue[tid] = 1436221Snate@binkert.org new EventQueue("instruction-based event queue"); 1442SN/A 1452SN/A // 1462SN/A // set up instruction-count-based termination events, if any 1472SN/A // 1485606Snate@binkert.org if (p->max_insts_any_thread != 0) { 1495606Snate@binkert.org const char *cause = "a thread reached the max instruction count"; 1506221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1515606Snate@binkert.org Event *event = new SimLoopExitEvent(cause, 0); 1526221Snate@binkert.org comInstEventQueue[tid]->schedule(event, p->max_insts_any_thread); 1535606Snate@binkert.org } 1545606Snate@binkert.org } 1552SN/A 1569647Sdam.sunwoo@arm.com // Set up instruction-count-based termination events for SimPoints 1579647Sdam.sunwoo@arm.com // Typically, there are more than one action points. 1589647Sdam.sunwoo@arm.com // Simulation.py is responsible to take the necessary actions upon 1599647Sdam.sunwoo@arm.com // exitting the simulation loop. 1609647Sdam.sunwoo@arm.com if (!p->simpoint_start_insts.empty()) { 1619647Sdam.sunwoo@arm.com const char *cause = "simpoint starting point found"; 1629647Sdam.sunwoo@arm.com for (size_t i = 0; i < p->simpoint_start_insts.size(); ++i) { 1639647Sdam.sunwoo@arm.com Event *event = new SimLoopExitEvent(cause, 0); 1649647Sdam.sunwoo@arm.com comInstEventQueue[0]->schedule(event, p->simpoint_start_insts[i]); 1659647Sdam.sunwoo@arm.com } 1669647Sdam.sunwoo@arm.com } 1679647Sdam.sunwoo@arm.com 1681400SN/A if (p->max_insts_all_threads != 0) { 1695606Snate@binkert.org const char *cause = "all threads reached the max instruction count"; 1705606Snate@binkert.org 1712SN/A // allocate & initialize shared downcounter: each event will 1722SN/A // decrement this when triggered; simulation will terminate 1732SN/A // when counter reaches 0 1742SN/A int *counter = new int; 1756221Snate@binkert.org *counter = numThreads; 1766221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1775606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1786670Shsul@eecs.umich.edu comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 1795606Snate@binkert.org } 1802SN/A } 1812SN/A 182124SN/A // allocate per-thread load-based event queues 1836221Snate@binkert.org comLoadEventQueue = new EventQueue *[numThreads]; 1846221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1856221Snate@binkert.org comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 186124SN/A 187124SN/A // 188124SN/A // set up instruction-count-based termination events, if any 189124SN/A // 1905606Snate@binkert.org if (p->max_loads_any_thread != 0) { 1915606Snate@binkert.org const char *cause = "a thread reached the max load count"; 1926221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1935606Snate@binkert.org Event *event = new SimLoopExitEvent(cause, 0); 1946221Snate@binkert.org comLoadEventQueue[tid]->schedule(event, p->max_loads_any_thread); 1955606Snate@binkert.org } 1965606Snate@binkert.org } 197124SN/A 1981400SN/A if (p->max_loads_all_threads != 0) { 1995606Snate@binkert.org const char *cause = "all threads reached the max load count"; 200124SN/A // allocate & initialize shared downcounter: each event will 201124SN/A // decrement this when triggered; simulation will terminate 202124SN/A // when counter reaches 0 203124SN/A int *counter = new int; 2046221Snate@binkert.org *counter = numThreads; 2056221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 2065606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 2076221Snate@binkert.org comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 2085606Snate@binkert.org } 209124SN/A } 210124SN/A 2111191SN/A functionTracingEnabled = false; 2125529Snate@binkert.org if (p->function_trace) { 2138634Schris.emmons@arm.com const string fname = csprintf("ftrace.%s", name()); 2148634Schris.emmons@arm.com functionTraceStream = simout.find(fname); 2158634Schris.emmons@arm.com if (!functionTraceStream) 2168634Schris.emmons@arm.com functionTraceStream = simout.create(fname); 2178634Schris.emmons@arm.com 2181191SN/A currentFunctionStart = currentFunctionEnd = 0; 2195529Snate@binkert.org functionEntryTick = p->function_trace_start; 2201191SN/A 2215529Snate@binkert.org if (p->function_trace_start == 0) { 2221191SN/A functionTracingEnabled = true; 2231191SN/A } else { 2245606Snate@binkert.org typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap; 2255606Snate@binkert.org Event *event = new wrap(this, true); 2265606Snate@binkert.org schedule(event, p->function_trace_start); 2271191SN/A } 2281191SN/A } 2298876Sandreas.hansson@arm.com 2308876Sandreas.hansson@arm.com // The interrupts should always be present unless this CPU is 2318876Sandreas.hansson@arm.com // switched in later or in case it is a checker CPU 2329433SAndreas.Sandberg@ARM.com if (!params()->switched_out && !is_checker) { 2338876Sandreas.hansson@arm.com if (interrupts) { 2348876Sandreas.hansson@arm.com interrupts->setCPU(this); 2358876Sandreas.hansson@arm.com } else { 2368876Sandreas.hansson@arm.com fatal("CPU %s has no interrupt controller.\n" 2378876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 2388876Sandreas.hansson@arm.com } 2398876Sandreas.hansson@arm.com } 2405810Sgblack@eecs.umich.edu 2418779Sgblack@eecs.umich.edu if (FullSystem) { 2428779Sgblack@eecs.umich.edu if (params()->profile) 2438779Sgblack@eecs.umich.edu profileEvent = new ProfileEvent(this, params()->profile); 2448779Sgblack@eecs.umich.edu } 2455529Snate@binkert.org tracer = params()->tracer; 2469384SAndreas.Sandberg@arm.com 2479384SAndreas.Sandberg@arm.com if (params()->isa.size() != numThreads) { 2489384SAndreas.Sandberg@arm.com fatal("Number of ISAs (%i) assigned to the CPU does not equal number " 2499384SAndreas.Sandberg@arm.com "of threads (%i).\n", params()->isa.size(), numThreads); 2509384SAndreas.Sandberg@arm.com } 2511917SN/A} 2521191SN/A 2531191SN/Avoid 2541191SN/ABaseCPU::enableFunctionTrace() 2551191SN/A{ 2561191SN/A functionTracingEnabled = true; 2571191SN/A} 2581191SN/A 2591191SN/ABaseCPU::~BaseCPU() 2601191SN/A{ 2619086Sandreas.hansson@arm.com delete profileEvent; 2629086Sandreas.hansson@arm.com delete[] comLoadEventQueue; 2639086Sandreas.hansson@arm.com delete[] comInstEventQueue; 2641191SN/A} 2651191SN/A 2661129SN/Avoid 2671129SN/ABaseCPU::init() 2681129SN/A{ 2699523SAndreas.Sandberg@ARM.com if (!params()->switched_out) { 2702680Sktlim@umich.edu registerThreadContexts(); 2719523SAndreas.Sandberg@ARM.com 2729523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 2739523SAndreas.Sandberg@ARM.com } 2741129SN/A} 275180SN/A 2762SN/Avoid 2771917SN/ABaseCPU::startup() 2781917SN/A{ 2798779Sgblack@eecs.umich.edu if (FullSystem) { 2809433SAndreas.Sandberg@ARM.com if (!params()->switched_out && profileEvent) 2818779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 2828779Sgblack@eecs.umich.edu } 2832356SN/A 2845529Snate@binkert.org if (params()->progress_interval) { 2859179Sandreas.hansson@arm.com new CPUProgressEvent(this, params()->progress_interval); 2862356SN/A } 2871917SN/A} 2881917SN/A 2891917SN/A 2901917SN/Avoid 2912SN/ABaseCPU::regStats() 2922SN/A{ 293729SN/A using namespace Stats; 294707SN/A 295707SN/A numCycles 296707SN/A .name(name() + ".numCycles") 297707SN/A .desc("number of cpu cycles simulated") 298707SN/A ; 299707SN/A 3007914SBrad.Beckmann@amd.com numWorkItemsStarted 3017914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsStarted") 3027914SBrad.Beckmann@amd.com .desc("number of work items this cpu started") 3037914SBrad.Beckmann@amd.com ; 3047914SBrad.Beckmann@amd.com 3057914SBrad.Beckmann@amd.com numWorkItemsCompleted 3067914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsCompleted") 3077914SBrad.Beckmann@amd.com .desc("number of work items this cpu completed") 3087914SBrad.Beckmann@amd.com ; 3097914SBrad.Beckmann@amd.com 3102680Sktlim@umich.edu int size = threadContexts.size(); 3112SN/A if (size > 1) { 3122SN/A for (int i = 0; i < size; ++i) { 3132SN/A stringstream namestr; 3142SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 3152680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 3162SN/A } 3172SN/A } else if (size == 1) 3182680Sktlim@umich.edu threadContexts[0]->regStats(name()); 3192SN/A} 3202SN/A 3219294Sandreas.hansson@arm.comBaseMasterPort & 3229294Sandreas.hansson@arm.comBaseCPU::getMasterPort(const string &if_name, PortID idx) 3238850Sandreas.hansson@arm.com{ 3248850Sandreas.hansson@arm.com // Get the right port based on name. This applies to all the 3258850Sandreas.hansson@arm.com // subclasses of the base CPU and relies on their implementation 3268850Sandreas.hansson@arm.com // of getDataPort and getInstPort. In all cases there methods 3279608Sandreas.hansson@arm.com // return a MasterPort pointer. 3288850Sandreas.hansson@arm.com if (if_name == "dcache_port") 3298922Swilliam.wang@arm.com return getDataPort(); 3308850Sandreas.hansson@arm.com else if (if_name == "icache_port") 3318922Swilliam.wang@arm.com return getInstPort(); 3328850Sandreas.hansson@arm.com else 3338922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 3348850Sandreas.hansson@arm.com} 3358850Sandreas.hansson@arm.com 336180SN/Avoid 3372680Sktlim@umich.eduBaseCPU::registerThreadContexts() 338180SN/A{ 3396221Snate@binkert.org ThreadID size = threadContexts.size(); 3406221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 3416221Snate@binkert.org ThreadContext *tc = threadContexts[tid]; 3422378SN/A 3435718Shsul@eecs.umich.edu /** This is so that contextId and cpuId match where there is a 3445718Shsul@eecs.umich.edu * 1cpu:1context relationship. Otherwise, the order of registration 3455718Shsul@eecs.umich.edu * could affect the assignment and cpu 1 could have context id 3, for 3465718Shsul@eecs.umich.edu * example. We may even want to do something like this for SMT so that 3475718Shsul@eecs.umich.edu * cpu 0 has the lowest thread contexts and cpu N has the highest, but 3485718Shsul@eecs.umich.edu * I'll just do this for now 3495718Shsul@eecs.umich.edu */ 3506221Snate@binkert.org if (numThreads == 1) 3515718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc, _cpuId)); 3525718Shsul@eecs.umich.edu else 3535718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc)); 3548779Sgblack@eecs.umich.edu 3558779Sgblack@eecs.umich.edu if (!FullSystem) 3568779Sgblack@eecs.umich.edu tc->getProcessPtr()->assignThreadContext(tc->contextId()); 357180SN/A } 358180SN/A} 359180SN/A 360180SN/A 3614000Ssaidi@eecs.umich.eduint 3624000Ssaidi@eecs.umich.eduBaseCPU::findContext(ThreadContext *tc) 3634000Ssaidi@eecs.umich.edu{ 3646221Snate@binkert.org ThreadID size = threadContexts.size(); 3656221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 3666221Snate@binkert.org if (tc == threadContexts[tid]) 3676221Snate@binkert.org return tid; 3684000Ssaidi@eecs.umich.edu } 3694000Ssaidi@eecs.umich.edu return 0; 3704000Ssaidi@eecs.umich.edu} 3714000Ssaidi@eecs.umich.edu 372180SN/Avoid 3732798Sktlim@umich.eduBaseCPU::switchOut() 374180SN/A{ 3759430SAndreas.Sandberg@ARM.com assert(!_switchedOut); 3769430SAndreas.Sandberg@ARM.com _switchedOut = true; 3772359SN/A if (profileEvent && profileEvent->scheduled()) 3785606Snate@binkert.org deschedule(profileEvent); 3799446SAndreas.Sandberg@ARM.com 3809446SAndreas.Sandberg@ARM.com // Flush all TLBs in the CPU to avoid having stale translations if 3819446SAndreas.Sandberg@ARM.com // it gets switched in later. 3829446SAndreas.Sandberg@ARM.com flushTLBs(); 383180SN/A} 384180SN/A 385180SN/Avoid 3868737Skoansin.tan@gmail.comBaseCPU::takeOverFrom(BaseCPU *oldCPU) 387180SN/A{ 3882680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 3899152Satgutier@umich.edu assert(_cpuId == oldCPU->cpuId()); 3909430SAndreas.Sandberg@ARM.com assert(_switchedOut); 3919430SAndreas.Sandberg@ARM.com assert(oldCPU != this); 3929332Sdam.sunwoo@arm.com _pid = oldCPU->getPid(); 3939332Sdam.sunwoo@arm.com _taskId = oldCPU->taskId(); 3949430SAndreas.Sandberg@ARM.com _switchedOut = false; 3955712Shsul@eecs.umich.edu 3966221Snate@binkert.org ThreadID size = threadContexts.size(); 3976221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 3982680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 3992680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 400180SN/A 4012680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 4022651Ssaidi@eecs.umich.edu 4032680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 4042651Ssaidi@eecs.umich.edu 4055714Shsul@eecs.umich.edu assert(newTC->contextId() == oldTC->contextId()); 4065715Shsul@eecs.umich.edu assert(newTC->threadId() == oldTC->threadId()); 4075714Shsul@eecs.umich.edu system->replaceThreadContext(newTC, newTC->contextId()); 4082359SN/A 4095875Ssteve.reinhardt@amd.com /* This code no longer works since the zero register (e.g., 4105875Ssteve.reinhardt@amd.com * r31 on Alpha) doesn't necessarily contain zero at this 4115875Ssteve.reinhardt@amd.com * point. 4125875Ssteve.reinhardt@amd.com if (DTRACE(Context)) 4135217Ssaidi@eecs.umich.edu ThreadContext::compare(oldTC, newTC); 4145875Ssteve.reinhardt@amd.com */ 4157781SAli.Saidi@ARM.com 4169294Sandreas.hansson@arm.com BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort(); 4179294Sandreas.hansson@arm.com BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort(); 4189294Sandreas.hansson@arm.com BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort(); 4199294Sandreas.hansson@arm.com BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort(); 4207781SAli.Saidi@ARM.com 4217781SAli.Saidi@ARM.com // Move over any table walker ports if they exist 4229178Sandreas.hansson@arm.com if (new_itb_port) { 4239178Sandreas.hansson@arm.com assert(!new_itb_port->isConnected()); 4247781SAli.Saidi@ARM.com assert(old_itb_port); 4259178Sandreas.hansson@arm.com assert(old_itb_port->isConnected()); 4269294Sandreas.hansson@arm.com BaseSlavePort &slavePort = old_itb_port->getSlavePort(); 4279178Sandreas.hansson@arm.com old_itb_port->unbind(); 4288922Swilliam.wang@arm.com new_itb_port->bind(slavePort); 4297781SAli.Saidi@ARM.com } 4309178Sandreas.hansson@arm.com if (new_dtb_port) { 4319178Sandreas.hansson@arm.com assert(!new_dtb_port->isConnected()); 4327781SAli.Saidi@ARM.com assert(old_dtb_port); 4339178Sandreas.hansson@arm.com assert(old_dtb_port->isConnected()); 4349294Sandreas.hansson@arm.com BaseSlavePort &slavePort = old_dtb_port->getSlavePort(); 4359178Sandreas.hansson@arm.com old_dtb_port->unbind(); 4368922Swilliam.wang@arm.com new_dtb_port->bind(slavePort); 4377781SAli.Saidi@ARM.com } 4388733Sgeoffrey.blake@arm.com 4398887Sgeoffrey.blake@arm.com // Checker whether or not we have to transfer CheckerCPU 4408887Sgeoffrey.blake@arm.com // objects over in the switch 4418887Sgeoffrey.blake@arm.com CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr(); 4428887Sgeoffrey.blake@arm.com CheckerCPU *newChecker = newTC->getCheckerCpuPtr(); 4438887Sgeoffrey.blake@arm.com if (oldChecker && newChecker) { 4449294Sandreas.hansson@arm.com BaseMasterPort *old_checker_itb_port = 4458922Swilliam.wang@arm.com oldChecker->getITBPtr()->getMasterPort(); 4469294Sandreas.hansson@arm.com BaseMasterPort *old_checker_dtb_port = 4478922Swilliam.wang@arm.com oldChecker->getDTBPtr()->getMasterPort(); 4489294Sandreas.hansson@arm.com BaseMasterPort *new_checker_itb_port = 4498922Swilliam.wang@arm.com newChecker->getITBPtr()->getMasterPort(); 4509294Sandreas.hansson@arm.com BaseMasterPort *new_checker_dtb_port = 4518922Swilliam.wang@arm.com newChecker->getDTBPtr()->getMasterPort(); 4528733Sgeoffrey.blake@arm.com 4538887Sgeoffrey.blake@arm.com // Move over any table walker ports if they exist for checker 4549178Sandreas.hansson@arm.com if (new_checker_itb_port) { 4559178Sandreas.hansson@arm.com assert(!new_checker_itb_port->isConnected()); 4568887Sgeoffrey.blake@arm.com assert(old_checker_itb_port); 4579178Sandreas.hansson@arm.com assert(old_checker_itb_port->isConnected()); 4589294Sandreas.hansson@arm.com BaseSlavePort &slavePort = 4599294Sandreas.hansson@arm.com old_checker_itb_port->getSlavePort(); 4609178Sandreas.hansson@arm.com old_checker_itb_port->unbind(); 4618922Swilliam.wang@arm.com new_checker_itb_port->bind(slavePort); 4628887Sgeoffrey.blake@arm.com } 4639178Sandreas.hansson@arm.com if (new_checker_dtb_port) { 4649178Sandreas.hansson@arm.com assert(!new_checker_dtb_port->isConnected()); 4658887Sgeoffrey.blake@arm.com assert(old_checker_dtb_port); 4669178Sandreas.hansson@arm.com assert(old_checker_dtb_port->isConnected()); 4679294Sandreas.hansson@arm.com BaseSlavePort &slavePort = 4689294Sandreas.hansson@arm.com old_checker_dtb_port->getSlavePort(); 4699178Sandreas.hansson@arm.com old_checker_dtb_port->unbind(); 4708922Swilliam.wang@arm.com new_checker_dtb_port->bind(slavePort); 4718887Sgeoffrey.blake@arm.com } 4728733Sgeoffrey.blake@arm.com } 473180SN/A } 474605SN/A 4753520Sgblack@eecs.umich.edu interrupts = oldCPU->interrupts; 4765810Sgblack@eecs.umich.edu interrupts->setCPU(this); 4779152Satgutier@umich.edu oldCPU->interrupts = NULL; 4782254SN/A 4798779Sgblack@eecs.umich.edu if (FullSystem) { 4808779Sgblack@eecs.umich.edu for (ThreadID i = 0; i < size; ++i) 4818779Sgblack@eecs.umich.edu threadContexts[i]->profileClear(); 4822254SN/A 4838779Sgblack@eecs.umich.edu if (profileEvent) 4848779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 4858779Sgblack@eecs.umich.edu } 4864192Sktlim@umich.edu 4879178Sandreas.hansson@arm.com // All CPUs have an instruction and a data port, and the new CPU's 4889178Sandreas.hansson@arm.com // ports are dangling while the old CPU has its ports connected 4899178Sandreas.hansson@arm.com // already. Unbind the old CPU and then bind the ports of the one 4909178Sandreas.hansson@arm.com // we are switching to. 4919178Sandreas.hansson@arm.com assert(!getInstPort().isConnected()); 4929178Sandreas.hansson@arm.com assert(oldCPU->getInstPort().isConnected()); 4939294Sandreas.hansson@arm.com BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort(); 4949178Sandreas.hansson@arm.com oldCPU->getInstPort().unbind(); 4959178Sandreas.hansson@arm.com getInstPort().bind(inst_peer_port); 4964192Sktlim@umich.edu 4979178Sandreas.hansson@arm.com assert(!getDataPort().isConnected()); 4989178Sandreas.hansson@arm.com assert(oldCPU->getDataPort().isConnected()); 4999294Sandreas.hansson@arm.com BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort(); 5009178Sandreas.hansson@arm.com oldCPU->getDataPort().unbind(); 5019178Sandreas.hansson@arm.com getDataPort().bind(data_peer_port); 502180SN/A} 503180SN/A 5049446SAndreas.Sandberg@ARM.comvoid 5059446SAndreas.Sandberg@ARM.comBaseCPU::flushTLBs() 5069446SAndreas.Sandberg@ARM.com{ 5079446SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < threadContexts.size(); ++i) { 5089446SAndreas.Sandberg@ARM.com ThreadContext &tc(*threadContexts[i]); 5099446SAndreas.Sandberg@ARM.com CheckerCPU *checker(tc.getCheckerCpuPtr()); 5109446SAndreas.Sandberg@ARM.com 5119446SAndreas.Sandberg@ARM.com tc.getITBPtr()->flushAll(); 5129446SAndreas.Sandberg@ARM.com tc.getDTBPtr()->flushAll(); 5139446SAndreas.Sandberg@ARM.com if (checker) { 5149446SAndreas.Sandberg@ARM.com checker->getITBPtr()->flushAll(); 5159446SAndreas.Sandberg@ARM.com checker->getDTBPtr()->flushAll(); 5169446SAndreas.Sandberg@ARM.com } 5179446SAndreas.Sandberg@ARM.com } 5189446SAndreas.Sandberg@ARM.com} 5199446SAndreas.Sandberg@ARM.com 520180SN/A 5215536Srstrong@hp.comBaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval) 5225606Snate@binkert.org : cpu(_cpu), interval(_interval) 5231917SN/A{ } 5241917SN/A 5251917SN/Avoid 5261917SN/ABaseCPU::ProfileEvent::process() 5271917SN/A{ 5286221Snate@binkert.org ThreadID size = cpu->threadContexts.size(); 5296221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 5302680Sktlim@umich.edu ThreadContext *tc = cpu->threadContexts[i]; 5312680Sktlim@umich.edu tc->profileSample(); 5321917SN/A } 5332254SN/A 5347823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + interval); 5351917SN/A} 5361917SN/A 5372SN/Avoid 538921SN/ABaseCPU::serialize(std::ostream &os) 539921SN/A{ 5404000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(instCnt); 5419332Sdam.sunwoo@arm.com 5429448SAndreas.Sandberg@ARM.com if (!_switchedOut) { 5439448SAndreas.Sandberg@ARM.com /* Unlike _pid, _taskId is not serialized, as they are dynamically 5449448SAndreas.Sandberg@ARM.com * assigned unique ids that are only meaningful for the duration of 5459448SAndreas.Sandberg@ARM.com * a specific run. We will need to serialize the entire taskMap in 5469448SAndreas.Sandberg@ARM.com * system. */ 5479448SAndreas.Sandberg@ARM.com SERIALIZE_SCALAR(_pid); 5489332Sdam.sunwoo@arm.com 5499448SAndreas.Sandberg@ARM.com interrupts->serialize(os); 5509448SAndreas.Sandberg@ARM.com 5519448SAndreas.Sandberg@ARM.com // Serialize the threads, this is done by the CPU implementation. 5529448SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < numThreads; ++i) { 5539448SAndreas.Sandberg@ARM.com nameOut(os, csprintf("%s.xc.%i", name(), i)); 5549448SAndreas.Sandberg@ARM.com serializeThread(os, i); 5559448SAndreas.Sandberg@ARM.com } 5569448SAndreas.Sandberg@ARM.com } 557921SN/A} 558921SN/A 559921SN/Avoid 560921SN/ABaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 561921SN/A{ 5624000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(instCnt); 5639448SAndreas.Sandberg@ARM.com 5649448SAndreas.Sandberg@ARM.com if (!_switchedOut) { 5659448SAndreas.Sandberg@ARM.com UNSERIALIZE_SCALAR(_pid); 5669448SAndreas.Sandberg@ARM.com interrupts->unserialize(cp, section); 5679448SAndreas.Sandberg@ARM.com 5689448SAndreas.Sandberg@ARM.com // Unserialize the threads, this is done by the CPU implementation. 5699448SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < numThreads; ++i) 5709448SAndreas.Sandberg@ARM.com unserializeThread(cp, csprintf("%s.xc.%i", section, i), i); 5719448SAndreas.Sandberg@ARM.com } 572921SN/A} 573921SN/A 5741191SN/Avoid 5751191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 5761191SN/A{ 5771191SN/A if (!debugSymbolTable) 5781191SN/A return; 5791191SN/A 5801191SN/A // if pc enters different function, print new function symbol and 5811191SN/A // update saved range. Otherwise do nothing. 5821191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 5831191SN/A string sym_str; 5841191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 5851191SN/A currentFunctionStart, 5861191SN/A currentFunctionEnd); 5871191SN/A 5881191SN/A if (!found) { 5891191SN/A // no symbol found: use addr as label 5901191SN/A sym_str = csprintf("0x%x", pc); 5911191SN/A currentFunctionStart = pc; 5921191SN/A currentFunctionEnd = pc + 1; 5931191SN/A } 5941191SN/A 5951191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 5967823Ssteve.reinhardt@amd.com curTick() - functionEntryTick, curTick(), sym_str); 5977823Ssteve.reinhardt@amd.com functionEntryTick = curTick(); 5981191SN/A } 5991191SN/A} 600