base.cc revision 8737
12SN/A/* 28707Sandreas.hansson@arm.com * Copyright (c) 2011 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Nathan Binkert 437897Shestness@cs.utexas.edu * Rick Strong 442SN/A */ 452SN/A 461388SN/A#include <iostream> 478229Snate@binkert.org#include <sstream> 482SN/A#include <string> 492SN/A 507781SAli.Saidi@ARM.com#include "arch/tlb.hh" 518229Snate@binkert.org#include "base/loader/symtab.hh" 521191SN/A#include "base/cprintf.hh" 531191SN/A#include "base/misc.hh" 541388SN/A#include "base/output.hh" 555529Snate@binkert.org#include "base/trace.hh" 568733Sgeoffrey.blake@arm.com#include "config/use_checker.hh" 571717SN/A#include "cpu/base.hh" 582651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 598229Snate@binkert.org#include "cpu/profile.hh" 602680Sktlim@umich.edu#include "cpu/thread_context.hh" 618232Snate@binkert.org#include "debug/SyscallVerbose.hh" 625529Snate@binkert.org#include "params/BaseCPU.hh" 632190SN/A#include "sim/process.hh" 6456SN/A#include "sim/sim_events.hh" 658229Snate@binkert.org#include "sim/sim_exit.hh" 662190SN/A#include "sim/system.hh" 672SN/A 688733Sgeoffrey.blake@arm.com#if USE_CHECKER 698733Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 708733Sgeoffrey.blake@arm.com#endif 718733Sgeoffrey.blake@arm.com 722359SN/A// Hack 732359SN/A#include "sim/stat_control.hh" 742359SN/A 752SN/Ausing namespace std; 762SN/A 772SN/Avector<BaseCPU *> BaseCPU::cpuList; 782SN/A 792SN/A// This variable reflects the max number of threads in any CPU. Be 802SN/A// careful to only use it once all the CPUs that you care about have 812SN/A// been initialized 822SN/Aint maxThreadsPerCPU = 1; 832SN/A 845606Snate@binkert.orgCPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 856144Sksewell@umich.edu : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 866144Sksewell@umich.edu cpu(_cpu), _repeatEvent(true) 873126Sktlim@umich.edu{ 886144Sksewell@umich.edu if (_interval) 897823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 903126Sktlim@umich.edu} 913126Sktlim@umich.edu 922356SN/Avoid 932356SN/ACPUProgressEvent::process() 942356SN/A{ 952367SN/A Counter temp = cpu->totalInstructions(); 962356SN/A#ifndef NDEBUG 976144Sksewell@umich.edu double ipc = double(temp - lastNumInst) / (_interval / cpu->ticks(1)); 982367SN/A 996144Sksewell@umich.edu DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 1006144Sksewell@umich.edu "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 1016144Sksewell@umich.edu ipc); 1022356SN/A ipc = 0.0; 1032367SN/A#else 1046144Sksewell@umich.edu cprintf("%lli: %s progress event, total committed:%i, progress insts " 1057823Ssteve.reinhardt@amd.com "committed: %lli\n", curTick(), cpu->name(), temp, 1066144Sksewell@umich.edu temp - lastNumInst); 1072367SN/A#endif 1082356SN/A lastNumInst = temp; 1096144Sksewell@umich.edu 1106144Sksewell@umich.edu if (_repeatEvent) 1117823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 1122356SN/A} 1132356SN/A 1142356SN/Aconst char * 1155336Shines@cs.fsu.eduCPUProgressEvent::description() const 1162356SN/A{ 1174873Sstever@eecs.umich.edu return "CPU Progress"; 1182356SN/A} 1192356SN/A 1201858SN/A#if FULL_SYSTEM 1211400SN/ABaseCPU::BaseCPU(Params *p) 1225712Shsul@eecs.umich.edu : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id), 1235712Shsul@eecs.umich.edu interrupts(p->interrupts), 1246221Snate@binkert.org numThreads(p->numThreads), system(p->system), 1253661Srdreslin@umich.edu phase(p->phase) 1262SN/A#else 1271400SN/ABaseCPU::BaseCPU(Params *p) 1285712Shsul@eecs.umich.edu : MemObject(p), clock(p->clock), _cpuId(p->cpu_id), 1296221Snate@binkert.org numThreads(p->numThreads), system(p->system), 1303661Srdreslin@umich.edu phase(p->phase) 1312SN/A#endif 1322SN/A{ 1337823Ssteve.reinhardt@amd.com// currentTick = curTick(); 1341062SN/A 1355712Shsul@eecs.umich.edu // if Python did not provide a valid ID, do it here 1365712Shsul@eecs.umich.edu if (_cpuId == -1 ) { 1375712Shsul@eecs.umich.edu _cpuId = cpuList.size(); 1385712Shsul@eecs.umich.edu } 1395712Shsul@eecs.umich.edu 1402SN/A // add self to global list of CPUs 1412SN/A cpuList.push_back(this); 1422SN/A 1435712Shsul@eecs.umich.edu DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId); 1445712Shsul@eecs.umich.edu 1456221Snate@binkert.org if (numThreads > maxThreadsPerCPU) 1466221Snate@binkert.org maxThreadsPerCPU = numThreads; 1472SN/A 1482SN/A // allocate per-thread instruction-based event queues 1496221Snate@binkert.org comInstEventQueue = new EventQueue *[numThreads]; 1506221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1516221Snate@binkert.org comInstEventQueue[tid] = 1526221Snate@binkert.org new EventQueue("instruction-based event queue"); 1532SN/A 1542SN/A // 1552SN/A // set up instruction-count-based termination events, if any 1562SN/A // 1575606Snate@binkert.org if (p->max_insts_any_thread != 0) { 1585606Snate@binkert.org const char *cause = "a thread reached the max instruction count"; 1596221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1605606Snate@binkert.org Event *event = new SimLoopExitEvent(cause, 0); 1616221Snate@binkert.org comInstEventQueue[tid]->schedule(event, p->max_insts_any_thread); 1625606Snate@binkert.org } 1635606Snate@binkert.org } 1642SN/A 1651400SN/A if (p->max_insts_all_threads != 0) { 1665606Snate@binkert.org const char *cause = "all threads reached the max instruction count"; 1675606Snate@binkert.org 1682SN/A // allocate & initialize shared downcounter: each event will 1692SN/A // decrement this when triggered; simulation will terminate 1702SN/A // when counter reaches 0 1712SN/A int *counter = new int; 1726221Snate@binkert.org *counter = numThreads; 1736221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1745606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1756670Shsul@eecs.umich.edu comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 1765606Snate@binkert.org } 1772SN/A } 1782SN/A 179124SN/A // allocate per-thread load-based event queues 1806221Snate@binkert.org comLoadEventQueue = new EventQueue *[numThreads]; 1816221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1826221Snate@binkert.org comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 183124SN/A 184124SN/A // 185124SN/A // set up instruction-count-based termination events, if any 186124SN/A // 1875606Snate@binkert.org if (p->max_loads_any_thread != 0) { 1885606Snate@binkert.org const char *cause = "a thread reached the max load count"; 1896221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1905606Snate@binkert.org Event *event = new SimLoopExitEvent(cause, 0); 1916221Snate@binkert.org comLoadEventQueue[tid]->schedule(event, p->max_loads_any_thread); 1925606Snate@binkert.org } 1935606Snate@binkert.org } 194124SN/A 1951400SN/A if (p->max_loads_all_threads != 0) { 1965606Snate@binkert.org const char *cause = "all threads reached the max load count"; 197124SN/A // allocate & initialize shared downcounter: each event will 198124SN/A // decrement this when triggered; simulation will terminate 199124SN/A // when counter reaches 0 200124SN/A int *counter = new int; 2016221Snate@binkert.org *counter = numThreads; 2026221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 2035606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 2046221Snate@binkert.org comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 2055606Snate@binkert.org } 206124SN/A } 207124SN/A 2081191SN/A functionTracingEnabled = false; 2095529Snate@binkert.org if (p->function_trace) { 2108634Schris.emmons@arm.com const string fname = csprintf("ftrace.%s", name()); 2118634Schris.emmons@arm.com functionTraceStream = simout.find(fname); 2128634Schris.emmons@arm.com if (!functionTraceStream) 2138634Schris.emmons@arm.com functionTraceStream = simout.create(fname); 2148634Schris.emmons@arm.com 2151191SN/A currentFunctionStart = currentFunctionEnd = 0; 2165529Snate@binkert.org functionEntryTick = p->function_trace_start; 2171191SN/A 2185529Snate@binkert.org if (p->function_trace_start == 0) { 2191191SN/A functionTracingEnabled = true; 2201191SN/A } else { 2215606Snate@binkert.org typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap; 2225606Snate@binkert.org Event *event = new wrap(this, true); 2235606Snate@binkert.org schedule(event, p->function_trace_start); 2241191SN/A } 2251191SN/A } 2261917SN/A#if FULL_SYSTEM 2278733Sgeoffrey.blake@arm.com // Check if CPU model has interrupts connected. The CheckerCPU 2288733Sgeoffrey.blake@arm.com // cannot take interrupts directly for example. 2298733Sgeoffrey.blake@arm.com if (interrupts) 2308733Sgeoffrey.blake@arm.com interrupts->setCPU(this); 2315810Sgblack@eecs.umich.edu 2321917SN/A profileEvent = NULL; 2335529Snate@binkert.org if (params()->profile) 2345529Snate@binkert.org profileEvent = new ProfileEvent(this, params()->profile); 2351917SN/A#endif 2365529Snate@binkert.org tracer = params()->tracer; 2371917SN/A} 2381191SN/A 2391191SN/Avoid 2401191SN/ABaseCPU::enableFunctionTrace() 2411191SN/A{ 2421191SN/A functionTracingEnabled = true; 2431191SN/A} 2441191SN/A 2451191SN/ABaseCPU::~BaseCPU() 2461191SN/A{ 2471191SN/A} 2481191SN/A 2491129SN/Avoid 2501129SN/ABaseCPU::init() 2511129SN/A{ 2525529Snate@binkert.org if (!params()->defer_registration) 2532680Sktlim@umich.edu registerThreadContexts(); 2541129SN/A} 255180SN/A 2562SN/Avoid 2571917SN/ABaseCPU::startup() 2581917SN/A{ 2591917SN/A#if FULL_SYSTEM 2605529Snate@binkert.org if (!params()->defer_registration && profileEvent) 2617823Ssteve.reinhardt@amd.com schedule(profileEvent, curTick()); 2621917SN/A#endif 2632356SN/A 2645529Snate@binkert.org if (params()->progress_interval) { 2655606Snate@binkert.org Tick num_ticks = ticks(params()->progress_interval); 2666144Sksewell@umich.edu 2678607Sgblack@eecs.umich.edu new CPUProgressEvent(this, num_ticks); 2682356SN/A } 2691917SN/A} 2701917SN/A 2711917SN/A 2721917SN/Avoid 2732SN/ABaseCPU::regStats() 2742SN/A{ 275729SN/A using namespace Stats; 276707SN/A 277707SN/A numCycles 278707SN/A .name(name() + ".numCycles") 279707SN/A .desc("number of cpu cycles simulated") 280707SN/A ; 281707SN/A 2827914SBrad.Beckmann@amd.com numWorkItemsStarted 2837914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsStarted") 2847914SBrad.Beckmann@amd.com .desc("number of work items this cpu started") 2857914SBrad.Beckmann@amd.com ; 2867914SBrad.Beckmann@amd.com 2877914SBrad.Beckmann@amd.com numWorkItemsCompleted 2887914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsCompleted") 2897914SBrad.Beckmann@amd.com .desc("number of work items this cpu completed") 2907914SBrad.Beckmann@amd.com ; 2917914SBrad.Beckmann@amd.com 2922680Sktlim@umich.edu int size = threadContexts.size(); 2932SN/A if (size > 1) { 2942SN/A for (int i = 0; i < size; ++i) { 2952SN/A stringstream namestr; 2962SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 2972680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 2982SN/A } 2992SN/A } else if (size == 1) 3002680Sktlim@umich.edu threadContexts[0]->regStats(name()); 3012190SN/A 3022190SN/A#if FULL_SYSTEM 3032190SN/A#endif 3042SN/A} 3052SN/A 3063495Sktlim@umich.eduTick 3073495Sktlim@umich.eduBaseCPU::nextCycle() 3083495Sktlim@umich.edu{ 3097823Ssteve.reinhardt@amd.com Tick next_tick = curTick() - phase + clock - 1; 3103495Sktlim@umich.edu next_tick -= (next_tick % clock); 3113661Srdreslin@umich.edu next_tick += phase; 3123495Sktlim@umich.edu return next_tick; 3133495Sktlim@umich.edu} 3143495Sktlim@umich.edu 3153495Sktlim@umich.eduTick 3163495Sktlim@umich.eduBaseCPU::nextCycle(Tick begin_tick) 3173495Sktlim@umich.edu{ 3183495Sktlim@umich.edu Tick next_tick = begin_tick; 3194599Sacolyte@umich.edu if (next_tick % clock != 0) 3204599Sacolyte@umich.edu next_tick = next_tick - (next_tick % clock) + clock; 3213661Srdreslin@umich.edu next_tick += phase; 3223495Sktlim@umich.edu 3237823Ssteve.reinhardt@amd.com assert(next_tick >= curTick()); 3243495Sktlim@umich.edu return next_tick; 3253495Sktlim@umich.edu} 326180SN/A 327180SN/Avoid 3282680Sktlim@umich.eduBaseCPU::registerThreadContexts() 329180SN/A{ 3306221Snate@binkert.org ThreadID size = threadContexts.size(); 3316221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 3326221Snate@binkert.org ThreadContext *tc = threadContexts[tid]; 3332378SN/A 3345718Shsul@eecs.umich.edu /** This is so that contextId and cpuId match where there is a 3355718Shsul@eecs.umich.edu * 1cpu:1context relationship. Otherwise, the order of registration 3365718Shsul@eecs.umich.edu * could affect the assignment and cpu 1 could have context id 3, for 3375718Shsul@eecs.umich.edu * example. We may even want to do something like this for SMT so that 3385718Shsul@eecs.umich.edu * cpu 0 has the lowest thread contexts and cpu N has the highest, but 3395718Shsul@eecs.umich.edu * I'll just do this for now 3405718Shsul@eecs.umich.edu */ 3416221Snate@binkert.org if (numThreads == 1) 3425718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc, _cpuId)); 3435718Shsul@eecs.umich.edu else 3445718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc)); 3455713Shsul@eecs.umich.edu#if !FULL_SYSTEM 3465714Shsul@eecs.umich.edu tc->getProcessPtr()->assignThreadContext(tc->contextId()); 347180SN/A#endif 348180SN/A } 349180SN/A} 350180SN/A 351180SN/A 3524000Ssaidi@eecs.umich.eduint 3534000Ssaidi@eecs.umich.eduBaseCPU::findContext(ThreadContext *tc) 3544000Ssaidi@eecs.umich.edu{ 3556221Snate@binkert.org ThreadID size = threadContexts.size(); 3566221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 3576221Snate@binkert.org if (tc == threadContexts[tid]) 3586221Snate@binkert.org return tid; 3594000Ssaidi@eecs.umich.edu } 3604000Ssaidi@eecs.umich.edu return 0; 3614000Ssaidi@eecs.umich.edu} 3624000Ssaidi@eecs.umich.edu 363180SN/Avoid 3642798Sktlim@umich.eduBaseCPU::switchOut() 365180SN/A{ 3662359SN/A// panic("This CPU doesn't support sampling!"); 3672359SN/A#if FULL_SYSTEM 3682359SN/A if (profileEvent && profileEvent->scheduled()) 3695606Snate@binkert.org deschedule(profileEvent); 3702359SN/A#endif 371180SN/A} 372180SN/A 373180SN/Avoid 3748737Skoansin.tan@gmail.comBaseCPU::takeOverFrom(BaseCPU *oldCPU) 375180SN/A{ 3768737Skoansin.tan@gmail.com Port *ic = getPort("icache_port"); 3778737Skoansin.tan@gmail.com Port *dc = getPort("dcache_port"); 3782680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 379180SN/A 3805712Shsul@eecs.umich.edu _cpuId = oldCPU->cpuId(); 3815712Shsul@eecs.umich.edu 3826221Snate@binkert.org ThreadID size = threadContexts.size(); 3836221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 3842680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 3852680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 386180SN/A 3872680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 3882651Ssaidi@eecs.umich.edu 3892680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 3902651Ssaidi@eecs.umich.edu 3915714Shsul@eecs.umich.edu assert(newTC->contextId() == oldTC->contextId()); 3925715Shsul@eecs.umich.edu assert(newTC->threadId() == oldTC->threadId()); 3935714Shsul@eecs.umich.edu system->replaceThreadContext(newTC, newTC->contextId()); 3942359SN/A 3955875Ssteve.reinhardt@amd.com /* This code no longer works since the zero register (e.g., 3965875Ssteve.reinhardt@amd.com * r31 on Alpha) doesn't necessarily contain zero at this 3975875Ssteve.reinhardt@amd.com * point. 3985875Ssteve.reinhardt@amd.com if (DTRACE(Context)) 3995217Ssaidi@eecs.umich.edu ThreadContext::compare(oldTC, newTC); 4005875Ssteve.reinhardt@amd.com */ 4017781SAli.Saidi@ARM.com 4027781SAli.Saidi@ARM.com Port *old_itb_port, *old_dtb_port, *new_itb_port, *new_dtb_port; 4037781SAli.Saidi@ARM.com old_itb_port = oldTC->getITBPtr()->getPort(); 4047781SAli.Saidi@ARM.com old_dtb_port = oldTC->getDTBPtr()->getPort(); 4057781SAli.Saidi@ARM.com new_itb_port = newTC->getITBPtr()->getPort(); 4067781SAli.Saidi@ARM.com new_dtb_port = newTC->getDTBPtr()->getPort(); 4077781SAli.Saidi@ARM.com 4087781SAli.Saidi@ARM.com // Move over any table walker ports if they exist 4097781SAli.Saidi@ARM.com if (new_itb_port && !new_itb_port->isConnected()) { 4107781SAli.Saidi@ARM.com assert(old_itb_port); 4117781SAli.Saidi@ARM.com Port *peer = old_itb_port->getPeer();; 4127781SAli.Saidi@ARM.com new_itb_port->setPeer(peer); 4137781SAli.Saidi@ARM.com peer->setPeer(new_itb_port); 4147781SAli.Saidi@ARM.com } 4157781SAli.Saidi@ARM.com if (new_dtb_port && !new_dtb_port->isConnected()) { 4167781SAli.Saidi@ARM.com assert(old_dtb_port); 4177781SAli.Saidi@ARM.com Port *peer = old_dtb_port->getPeer();; 4187781SAli.Saidi@ARM.com new_dtb_port->setPeer(peer); 4197781SAli.Saidi@ARM.com peer->setPeer(new_dtb_port); 4207781SAli.Saidi@ARM.com } 4218733Sgeoffrey.blake@arm.com 4228733Sgeoffrey.blake@arm.com#if USE_CHECKER 4238733Sgeoffrey.blake@arm.com Port *old_checker_itb_port, *old_checker_dtb_port; 4248733Sgeoffrey.blake@arm.com Port *new_checker_itb_port, *new_checker_dtb_port; 4258733Sgeoffrey.blake@arm.com 4268733Sgeoffrey.blake@arm.com CheckerCPU *oldChecker = 4278733Sgeoffrey.blake@arm.com dynamic_cast<CheckerCPU*>(oldTC->getCheckerCpuPtr()); 4288733Sgeoffrey.blake@arm.com CheckerCPU *newChecker = 4298733Sgeoffrey.blake@arm.com dynamic_cast<CheckerCPU*>(newTC->getCheckerCpuPtr()); 4308733Sgeoffrey.blake@arm.com old_checker_itb_port = oldChecker->getITBPtr()->getPort(); 4318733Sgeoffrey.blake@arm.com old_checker_dtb_port = oldChecker->getDTBPtr()->getPort(); 4328733Sgeoffrey.blake@arm.com new_checker_itb_port = newChecker->getITBPtr()->getPort(); 4338733Sgeoffrey.blake@arm.com new_checker_dtb_port = newChecker->getDTBPtr()->getPort(); 4348733Sgeoffrey.blake@arm.com 4358733Sgeoffrey.blake@arm.com // Move over any table walker ports if they exist for checker 4368733Sgeoffrey.blake@arm.com if (new_checker_itb_port && !new_checker_itb_port->isConnected()) { 4378733Sgeoffrey.blake@arm.com assert(old_checker_itb_port); 4388733Sgeoffrey.blake@arm.com Port *peer = old_checker_itb_port->getPeer();; 4398733Sgeoffrey.blake@arm.com new_checker_itb_port->setPeer(peer); 4408733Sgeoffrey.blake@arm.com peer->setPeer(new_checker_itb_port); 4418733Sgeoffrey.blake@arm.com } 4428733Sgeoffrey.blake@arm.com if (new_checker_dtb_port && !new_checker_dtb_port->isConnected()) { 4438733Sgeoffrey.blake@arm.com assert(old_checker_dtb_port); 4448733Sgeoffrey.blake@arm.com Port *peer = old_checker_dtb_port->getPeer();; 4458733Sgeoffrey.blake@arm.com new_checker_dtb_port->setPeer(peer); 4468733Sgeoffrey.blake@arm.com peer->setPeer(new_checker_dtb_port); 4478733Sgeoffrey.blake@arm.com } 4488733Sgeoffrey.blake@arm.com#endif 4498733Sgeoffrey.blake@arm.com 450180SN/A } 451605SN/A 4521858SN/A#if FULL_SYSTEM 4533520Sgblack@eecs.umich.edu interrupts = oldCPU->interrupts; 4545810Sgblack@eecs.umich.edu interrupts->setCPU(this); 4552254SN/A 4566221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) 4572680Sktlim@umich.edu threadContexts[i]->profileClear(); 4582254SN/A 4594947Snate@binkert.org if (profileEvent) 4607823Ssteve.reinhardt@amd.com schedule(profileEvent, curTick()); 461612SN/A#endif 4624192Sktlim@umich.edu 4634192Sktlim@umich.edu // Connect new CPU to old CPU's memory only if new CPU isn't 4644192Sktlim@umich.edu // connected to anything. Also connect old CPU's memory to new 4654192Sktlim@umich.edu // CPU. 4665476Snate@binkert.org if (!ic->isConnected()) { 4675476Snate@binkert.org Port *peer = oldCPU->getPort("icache_port")->getPeer(); 4684192Sktlim@umich.edu ic->setPeer(peer); 4695476Snate@binkert.org peer->setPeer(ic); 4704192Sktlim@umich.edu } 4714192Sktlim@umich.edu 4725476Snate@binkert.org if (!dc->isConnected()) { 4735476Snate@binkert.org Port *peer = oldCPU->getPort("dcache_port")->getPeer(); 4744192Sktlim@umich.edu dc->setPeer(peer); 4755476Snate@binkert.org peer->setPeer(dc); 4764192Sktlim@umich.edu } 477180SN/A} 478180SN/A 479180SN/A 4801858SN/A#if FULL_SYSTEM 4815536Srstrong@hp.comBaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval) 4825606Snate@binkert.org : cpu(_cpu), interval(_interval) 4831917SN/A{ } 4841917SN/A 4851917SN/Avoid 4861917SN/ABaseCPU::ProfileEvent::process() 4871917SN/A{ 4886221Snate@binkert.org ThreadID size = cpu->threadContexts.size(); 4896221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 4902680Sktlim@umich.edu ThreadContext *tc = cpu->threadContexts[i]; 4912680Sktlim@umich.edu tc->profileSample(); 4921917SN/A } 4932254SN/A 4947823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + interval); 4951917SN/A} 4961917SN/A 4972SN/Avoid 498921SN/ABaseCPU::serialize(std::ostream &os) 499921SN/A{ 5004000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(instCnt); 5015647Sgblack@eecs.umich.edu interrupts->serialize(os); 502921SN/A} 503921SN/A 504921SN/Avoid 505921SN/ABaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 506921SN/A{ 5074000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(instCnt); 5085647Sgblack@eecs.umich.edu interrupts->unserialize(cp, section); 509921SN/A} 510921SN/A 5112SN/A#endif // FULL_SYSTEM 5122SN/A 5131191SN/Avoid 5141191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 5151191SN/A{ 5161191SN/A if (!debugSymbolTable) 5171191SN/A return; 5181191SN/A 5191191SN/A // if pc enters different function, print new function symbol and 5201191SN/A // update saved range. Otherwise do nothing. 5211191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 5221191SN/A string sym_str; 5231191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 5241191SN/A currentFunctionStart, 5251191SN/A currentFunctionEnd); 5261191SN/A 5271191SN/A if (!found) { 5281191SN/A // no symbol found: use addr as label 5291191SN/A sym_str = csprintf("0x%x", pc); 5301191SN/A currentFunctionStart = pc; 5311191SN/A currentFunctionEnd = pc + 1; 5321191SN/A } 5331191SN/A 5341191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 5357823Ssteve.reinhardt@amd.com curTick() - functionEntryTick, curTick(), sym_str); 5367823Ssteve.reinhardt@amd.com functionEntryTick = curTick(); 5371191SN/A } 5381191SN/A} 5398707Sandreas.hansson@arm.com 5408707Sandreas.hansson@arm.combool 5418707Sandreas.hansson@arm.comBaseCPU::CpuPort::recvTiming(PacketPtr pkt) 5428707Sandreas.hansson@arm.com{ 5438707Sandreas.hansson@arm.com panic("BaseCPU doesn't expect recvTiming callback!"); 5448707Sandreas.hansson@arm.com return true; 5458707Sandreas.hansson@arm.com} 5468707Sandreas.hansson@arm.com 5478707Sandreas.hansson@arm.comvoid 5488707Sandreas.hansson@arm.comBaseCPU::CpuPort::recvRetry() 5498707Sandreas.hansson@arm.com{ 5508707Sandreas.hansson@arm.com panic("BaseCPU doesn't expect recvRetry callback!"); 5518707Sandreas.hansson@arm.com} 5528707Sandreas.hansson@arm.com 5538707Sandreas.hansson@arm.comTick 5548707Sandreas.hansson@arm.comBaseCPU::CpuPort::recvAtomic(PacketPtr pkt) 5558707Sandreas.hansson@arm.com{ 5568707Sandreas.hansson@arm.com panic("BaseCPU doesn't expect recvAtomic callback!"); 5578707Sandreas.hansson@arm.com return curTick(); 5588707Sandreas.hansson@arm.com} 5598707Sandreas.hansson@arm.com 5608707Sandreas.hansson@arm.comvoid 5618707Sandreas.hansson@arm.comBaseCPU::CpuPort::recvFunctional(PacketPtr pkt) 5628707Sandreas.hansson@arm.com{ 5638707Sandreas.hansson@arm.com // No internal storage to update (in the general case). In the 5648707Sandreas.hansson@arm.com // long term this should never be called, but that assumed a split 5658707Sandreas.hansson@arm.com // into master/slave and request/response. 5668707Sandreas.hansson@arm.com} 5678707Sandreas.hansson@arm.com 5688707Sandreas.hansson@arm.comvoid 5698711Sandreas.hansson@arm.comBaseCPU::CpuPort::recvRangeChange() 5708707Sandreas.hansson@arm.com{ 5718707Sandreas.hansson@arm.com} 572