base.cc revision 7897
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 37897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 42SN/A * All rights reserved. 52SN/A * 62SN/A * Redistribution and use in source and binary forms, with or without 72SN/A * modification, are permitted provided that the following conditions are 82SN/A * met: redistributions of source code must retain the above copyright 92SN/A * notice, this list of conditions and the following disclaimer; 102SN/A * redistributions in binary form must reproduce the above copyright 112SN/A * notice, this list of conditions and the following disclaimer in the 122SN/A * documentation and/or other materials provided with the distribution; 132SN/A * neither the name of the copyright holders nor the names of its 142SN/A * contributors may be used to endorse or promote products derived from 152SN/A * this software without specific prior written permission. 162SN/A * 172SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 302665Ssaidi@eecs.umich.edu * Nathan Binkert 317897Shestness@cs.utexas.edu * Rick Strong 322SN/A */ 332SN/A 341388SN/A#include <iostream> 352SN/A#include <string> 362SN/A#include <sstream> 372SN/A 387781SAli.Saidi@ARM.com#include "arch/tlb.hh" 391191SN/A#include "base/cprintf.hh" 401191SN/A#include "base/loader/symtab.hh" 411191SN/A#include "base/misc.hh" 421388SN/A#include "base/output.hh" 435529Snate@binkert.org#include "base/trace.hh" 441717SN/A#include "cpu/base.hh" 452651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 462680Sktlim@umich.edu#include "cpu/thread_context.hh" 471977SN/A#include "cpu/profile.hh" 485529Snate@binkert.org#include "params/BaseCPU.hh" 493144Shsul@eecs.umich.edu#include "sim/sim_exit.hh" 502190SN/A#include "sim/process.hh" 5156SN/A#include "sim/sim_events.hh" 522190SN/A#include "sim/system.hh" 532SN/A 542359SN/A// Hack 552359SN/A#include "sim/stat_control.hh" 562359SN/A 572SN/Ausing namespace std; 582SN/A 592SN/Avector<BaseCPU *> BaseCPU::cpuList; 602SN/A 612SN/A// This variable reflects the max number of threads in any CPU. Be 622SN/A// careful to only use it once all the CPUs that you care about have 632SN/A// been initialized 642SN/Aint maxThreadsPerCPU = 1; 652SN/A 665606Snate@binkert.orgCPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 676144Sksewell@umich.edu : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 686144Sksewell@umich.edu cpu(_cpu), _repeatEvent(true) 693126Sktlim@umich.edu{ 706144Sksewell@umich.edu if (_interval) 717823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 723126Sktlim@umich.edu} 733126Sktlim@umich.edu 742356SN/Avoid 752356SN/ACPUProgressEvent::process() 762356SN/A{ 772367SN/A Counter temp = cpu->totalInstructions(); 782356SN/A#ifndef NDEBUG 796144Sksewell@umich.edu double ipc = double(temp - lastNumInst) / (_interval / cpu->ticks(1)); 802367SN/A 816144Sksewell@umich.edu DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 826144Sksewell@umich.edu "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 836144Sksewell@umich.edu ipc); 842356SN/A ipc = 0.0; 852367SN/A#else 866144Sksewell@umich.edu cprintf("%lli: %s progress event, total committed:%i, progress insts " 877823Ssteve.reinhardt@amd.com "committed: %lli\n", curTick(), cpu->name(), temp, 886144Sksewell@umich.edu temp - lastNumInst); 892367SN/A#endif 902356SN/A lastNumInst = temp; 916144Sksewell@umich.edu 926144Sksewell@umich.edu if (_repeatEvent) 937823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 942356SN/A} 952356SN/A 962356SN/Aconst char * 975336Shines@cs.fsu.eduCPUProgressEvent::description() const 982356SN/A{ 994873Sstever@eecs.umich.edu return "CPU Progress"; 1002356SN/A} 1012356SN/A 1021858SN/A#if FULL_SYSTEM 1031400SN/ABaseCPU::BaseCPU(Params *p) 1045712Shsul@eecs.umich.edu : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id), 1055712Shsul@eecs.umich.edu interrupts(p->interrupts), 1066221Snate@binkert.org numThreads(p->numThreads), system(p->system), 1073661Srdreslin@umich.edu phase(p->phase) 1082SN/A#else 1091400SN/ABaseCPU::BaseCPU(Params *p) 1105712Shsul@eecs.umich.edu : MemObject(p), clock(p->clock), _cpuId(p->cpu_id), 1116221Snate@binkert.org numThreads(p->numThreads), system(p->system), 1123661Srdreslin@umich.edu phase(p->phase) 1132SN/A#endif 1142SN/A{ 1157823Ssteve.reinhardt@amd.com// currentTick = curTick(); 1161062SN/A 1175712Shsul@eecs.umich.edu // if Python did not provide a valid ID, do it here 1185712Shsul@eecs.umich.edu if (_cpuId == -1 ) { 1195712Shsul@eecs.umich.edu _cpuId = cpuList.size(); 1205712Shsul@eecs.umich.edu } 1215712Shsul@eecs.umich.edu 1222SN/A // add self to global list of CPUs 1232SN/A cpuList.push_back(this); 1242SN/A 1255712Shsul@eecs.umich.edu DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId); 1265712Shsul@eecs.umich.edu 1276221Snate@binkert.org if (numThreads > maxThreadsPerCPU) 1286221Snate@binkert.org maxThreadsPerCPU = numThreads; 1292SN/A 1302SN/A // allocate per-thread instruction-based event queues 1316221Snate@binkert.org comInstEventQueue = new EventQueue *[numThreads]; 1326221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1336221Snate@binkert.org comInstEventQueue[tid] = 1346221Snate@binkert.org new EventQueue("instruction-based event queue"); 1352SN/A 1362SN/A // 1372SN/A // set up instruction-count-based termination events, if any 1382SN/A // 1395606Snate@binkert.org if (p->max_insts_any_thread != 0) { 1405606Snate@binkert.org const char *cause = "a thread reached the max instruction count"; 1416221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1425606Snate@binkert.org Event *event = new SimLoopExitEvent(cause, 0); 1436221Snate@binkert.org comInstEventQueue[tid]->schedule(event, p->max_insts_any_thread); 1445606Snate@binkert.org } 1455606Snate@binkert.org } 1462SN/A 1471400SN/A if (p->max_insts_all_threads != 0) { 1485606Snate@binkert.org const char *cause = "all threads reached the max instruction count"; 1495606Snate@binkert.org 1502SN/A // allocate & initialize shared downcounter: each event will 1512SN/A // decrement this when triggered; simulation will terminate 1522SN/A // when counter reaches 0 1532SN/A int *counter = new int; 1546221Snate@binkert.org *counter = numThreads; 1556221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1565606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1576670Shsul@eecs.umich.edu comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 1585606Snate@binkert.org } 1592SN/A } 1602SN/A 161124SN/A // allocate per-thread load-based event queues 1626221Snate@binkert.org comLoadEventQueue = new EventQueue *[numThreads]; 1636221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1646221Snate@binkert.org comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 165124SN/A 166124SN/A // 167124SN/A // set up instruction-count-based termination events, if any 168124SN/A // 1695606Snate@binkert.org if (p->max_loads_any_thread != 0) { 1705606Snate@binkert.org const char *cause = "a thread reached the max load count"; 1716221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1725606Snate@binkert.org Event *event = new SimLoopExitEvent(cause, 0); 1736221Snate@binkert.org comLoadEventQueue[tid]->schedule(event, p->max_loads_any_thread); 1745606Snate@binkert.org } 1755606Snate@binkert.org } 176124SN/A 1771400SN/A if (p->max_loads_all_threads != 0) { 1785606Snate@binkert.org const char *cause = "all threads reached the max load count"; 179124SN/A // allocate & initialize shared downcounter: each event will 180124SN/A // decrement this when triggered; simulation will terminate 181124SN/A // when counter reaches 0 182124SN/A int *counter = new int; 1836221Snate@binkert.org *counter = numThreads; 1846221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1855606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1866221Snate@binkert.org comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 1875606Snate@binkert.org } 188124SN/A } 189124SN/A 1901191SN/A functionTracingEnabled = false; 1915529Snate@binkert.org if (p->function_trace) { 1921388SN/A functionTraceStream = simout.find(csprintf("ftrace.%s", name())); 1931191SN/A currentFunctionStart = currentFunctionEnd = 0; 1945529Snate@binkert.org functionEntryTick = p->function_trace_start; 1951191SN/A 1965529Snate@binkert.org if (p->function_trace_start == 0) { 1971191SN/A functionTracingEnabled = true; 1981191SN/A } else { 1995606Snate@binkert.org typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap; 2005606Snate@binkert.org Event *event = new wrap(this, true); 2015606Snate@binkert.org schedule(event, p->function_trace_start); 2021191SN/A } 2031191SN/A } 2041917SN/A#if FULL_SYSTEM 2055810Sgblack@eecs.umich.edu interrupts->setCPU(this); 2065810Sgblack@eecs.umich.edu 2071917SN/A profileEvent = NULL; 2085529Snate@binkert.org if (params()->profile) 2095529Snate@binkert.org profileEvent = new ProfileEvent(this, params()->profile); 2101917SN/A#endif 2115529Snate@binkert.org tracer = params()->tracer; 2121917SN/A} 2131191SN/A 2141191SN/Avoid 2151191SN/ABaseCPU::enableFunctionTrace() 2161191SN/A{ 2171191SN/A functionTracingEnabled = true; 2181191SN/A} 2191191SN/A 2201191SN/ABaseCPU::~BaseCPU() 2211191SN/A{ 2221191SN/A} 2231191SN/A 2241129SN/Avoid 2251129SN/ABaseCPU::init() 2261129SN/A{ 2275529Snate@binkert.org if (!params()->defer_registration) 2282680Sktlim@umich.edu registerThreadContexts(); 2291129SN/A} 230180SN/A 2312SN/Avoid 2321917SN/ABaseCPU::startup() 2331917SN/A{ 2341917SN/A#if FULL_SYSTEM 2355529Snate@binkert.org if (!params()->defer_registration && profileEvent) 2367823Ssteve.reinhardt@amd.com schedule(profileEvent, curTick()); 2371917SN/A#endif 2382356SN/A 2395529Snate@binkert.org if (params()->progress_interval) { 2405606Snate@binkert.org Tick num_ticks = ticks(params()->progress_interval); 2416144Sksewell@umich.edu 2426144Sksewell@umich.edu Event *event; 2436144Sksewell@umich.edu event = new CPUProgressEvent(this, num_ticks); 2442356SN/A } 2451917SN/A} 2461917SN/A 2471917SN/A 2481917SN/Avoid 2492SN/ABaseCPU::regStats() 2502SN/A{ 251729SN/A using namespace Stats; 252707SN/A 253707SN/A numCycles 254707SN/A .name(name() + ".numCycles") 255707SN/A .desc("number of cpu cycles simulated") 256707SN/A ; 257707SN/A 2582680Sktlim@umich.edu int size = threadContexts.size(); 2592SN/A if (size > 1) { 2602SN/A for (int i = 0; i < size; ++i) { 2612SN/A stringstream namestr; 2622SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 2632680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 2642SN/A } 2652SN/A } else if (size == 1) 2662680Sktlim@umich.edu threadContexts[0]->regStats(name()); 2672190SN/A 2682190SN/A#if FULL_SYSTEM 2692190SN/A#endif 2702SN/A} 2712SN/A 2723495Sktlim@umich.eduTick 2733495Sktlim@umich.eduBaseCPU::nextCycle() 2743495Sktlim@umich.edu{ 2757823Ssteve.reinhardt@amd.com Tick next_tick = curTick() - phase + clock - 1; 2763495Sktlim@umich.edu next_tick -= (next_tick % clock); 2773661Srdreslin@umich.edu next_tick += phase; 2783495Sktlim@umich.edu return next_tick; 2793495Sktlim@umich.edu} 2803495Sktlim@umich.edu 2813495Sktlim@umich.eduTick 2823495Sktlim@umich.eduBaseCPU::nextCycle(Tick begin_tick) 2833495Sktlim@umich.edu{ 2843495Sktlim@umich.edu Tick next_tick = begin_tick; 2854599Sacolyte@umich.edu if (next_tick % clock != 0) 2864599Sacolyte@umich.edu next_tick = next_tick - (next_tick % clock) + clock; 2873661Srdreslin@umich.edu next_tick += phase; 2883495Sktlim@umich.edu 2897823Ssteve.reinhardt@amd.com assert(next_tick >= curTick()); 2903495Sktlim@umich.edu return next_tick; 2913495Sktlim@umich.edu} 292180SN/A 293180SN/Avoid 2942680Sktlim@umich.eduBaseCPU::registerThreadContexts() 295180SN/A{ 2966221Snate@binkert.org ThreadID size = threadContexts.size(); 2976221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 2986221Snate@binkert.org ThreadContext *tc = threadContexts[tid]; 2992378SN/A 3005718Shsul@eecs.umich.edu /** This is so that contextId and cpuId match where there is a 3015718Shsul@eecs.umich.edu * 1cpu:1context relationship. Otherwise, the order of registration 3025718Shsul@eecs.umich.edu * could affect the assignment and cpu 1 could have context id 3, for 3035718Shsul@eecs.umich.edu * example. We may even want to do something like this for SMT so that 3045718Shsul@eecs.umich.edu * cpu 0 has the lowest thread contexts and cpu N has the highest, but 3055718Shsul@eecs.umich.edu * I'll just do this for now 3065718Shsul@eecs.umich.edu */ 3076221Snate@binkert.org if (numThreads == 1) 3085718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc, _cpuId)); 3095718Shsul@eecs.umich.edu else 3105718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc)); 3115713Shsul@eecs.umich.edu#if !FULL_SYSTEM 3125714Shsul@eecs.umich.edu tc->getProcessPtr()->assignThreadContext(tc->contextId()); 313180SN/A#endif 314180SN/A } 315180SN/A} 316180SN/A 317180SN/A 3184000Ssaidi@eecs.umich.eduint 3194000Ssaidi@eecs.umich.eduBaseCPU::findContext(ThreadContext *tc) 3204000Ssaidi@eecs.umich.edu{ 3216221Snate@binkert.org ThreadID size = threadContexts.size(); 3226221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 3236221Snate@binkert.org if (tc == threadContexts[tid]) 3246221Snate@binkert.org return tid; 3254000Ssaidi@eecs.umich.edu } 3264000Ssaidi@eecs.umich.edu return 0; 3274000Ssaidi@eecs.umich.edu} 3284000Ssaidi@eecs.umich.edu 329180SN/Avoid 3302798Sktlim@umich.eduBaseCPU::switchOut() 331180SN/A{ 3322359SN/A// panic("This CPU doesn't support sampling!"); 3332359SN/A#if FULL_SYSTEM 3342359SN/A if (profileEvent && profileEvent->scheduled()) 3355606Snate@binkert.org deschedule(profileEvent); 3362359SN/A#endif 337180SN/A} 338180SN/A 339180SN/Avoid 3404192Sktlim@umich.eduBaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc) 341180SN/A{ 3422680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 343180SN/A 3445712Shsul@eecs.umich.edu _cpuId = oldCPU->cpuId(); 3455712Shsul@eecs.umich.edu 3466221Snate@binkert.org ThreadID size = threadContexts.size(); 3476221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 3482680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 3492680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 350180SN/A 3512680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 3522651Ssaidi@eecs.umich.edu 3532680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 3542651Ssaidi@eecs.umich.edu 3555714Shsul@eecs.umich.edu assert(newTC->contextId() == oldTC->contextId()); 3565715Shsul@eecs.umich.edu assert(newTC->threadId() == oldTC->threadId()); 3575714Shsul@eecs.umich.edu system->replaceThreadContext(newTC, newTC->contextId()); 3582359SN/A 3595875Ssteve.reinhardt@amd.com /* This code no longer works since the zero register (e.g., 3605875Ssteve.reinhardt@amd.com * r31 on Alpha) doesn't necessarily contain zero at this 3615875Ssteve.reinhardt@amd.com * point. 3625875Ssteve.reinhardt@amd.com if (DTRACE(Context)) 3635217Ssaidi@eecs.umich.edu ThreadContext::compare(oldTC, newTC); 3645875Ssteve.reinhardt@amd.com */ 3657781SAli.Saidi@ARM.com 3667781SAli.Saidi@ARM.com Port *old_itb_port, *old_dtb_port, *new_itb_port, *new_dtb_port; 3677781SAli.Saidi@ARM.com old_itb_port = oldTC->getITBPtr()->getPort(); 3687781SAli.Saidi@ARM.com old_dtb_port = oldTC->getDTBPtr()->getPort(); 3697781SAli.Saidi@ARM.com new_itb_port = newTC->getITBPtr()->getPort(); 3707781SAli.Saidi@ARM.com new_dtb_port = newTC->getDTBPtr()->getPort(); 3717781SAli.Saidi@ARM.com 3727781SAli.Saidi@ARM.com // Move over any table walker ports if they exist 3737781SAli.Saidi@ARM.com if (new_itb_port && !new_itb_port->isConnected()) { 3747781SAli.Saidi@ARM.com assert(old_itb_port); 3757781SAli.Saidi@ARM.com Port *peer = old_itb_port->getPeer();; 3767781SAli.Saidi@ARM.com new_itb_port->setPeer(peer); 3777781SAli.Saidi@ARM.com peer->setPeer(new_itb_port); 3787781SAli.Saidi@ARM.com } 3797781SAli.Saidi@ARM.com if (new_dtb_port && !new_dtb_port->isConnected()) { 3807781SAli.Saidi@ARM.com assert(old_dtb_port); 3817781SAli.Saidi@ARM.com Port *peer = old_dtb_port->getPeer();; 3827781SAli.Saidi@ARM.com new_dtb_port->setPeer(peer); 3837781SAli.Saidi@ARM.com peer->setPeer(new_dtb_port); 3847781SAli.Saidi@ARM.com } 385180SN/A } 386605SN/A 3871858SN/A#if FULL_SYSTEM 3883520Sgblack@eecs.umich.edu interrupts = oldCPU->interrupts; 3895810Sgblack@eecs.umich.edu interrupts->setCPU(this); 3902254SN/A 3916221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) 3922680Sktlim@umich.edu threadContexts[i]->profileClear(); 3932254SN/A 3944947Snate@binkert.org if (profileEvent) 3957823Ssteve.reinhardt@amd.com schedule(profileEvent, curTick()); 396612SN/A#endif 3974192Sktlim@umich.edu 3984192Sktlim@umich.edu // Connect new CPU to old CPU's memory only if new CPU isn't 3994192Sktlim@umich.edu // connected to anything. Also connect old CPU's memory to new 4004192Sktlim@umich.edu // CPU. 4015476Snate@binkert.org if (!ic->isConnected()) { 4025476Snate@binkert.org Port *peer = oldCPU->getPort("icache_port")->getPeer(); 4034192Sktlim@umich.edu ic->setPeer(peer); 4045476Snate@binkert.org peer->setPeer(ic); 4054192Sktlim@umich.edu } 4064192Sktlim@umich.edu 4075476Snate@binkert.org if (!dc->isConnected()) { 4085476Snate@binkert.org Port *peer = oldCPU->getPort("dcache_port")->getPeer(); 4094192Sktlim@umich.edu dc->setPeer(peer); 4105476Snate@binkert.org peer->setPeer(dc); 4114192Sktlim@umich.edu } 412180SN/A} 413180SN/A 414180SN/A 4151858SN/A#if FULL_SYSTEM 4165536Srstrong@hp.comBaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval) 4175606Snate@binkert.org : cpu(_cpu), interval(_interval) 4181917SN/A{ } 4191917SN/A 4201917SN/Avoid 4211917SN/ABaseCPU::ProfileEvent::process() 4221917SN/A{ 4236221Snate@binkert.org ThreadID size = cpu->threadContexts.size(); 4246221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 4252680Sktlim@umich.edu ThreadContext *tc = cpu->threadContexts[i]; 4262680Sktlim@umich.edu tc->profileSample(); 4271917SN/A } 4282254SN/A 4297823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + interval); 4301917SN/A} 4311917SN/A 4322SN/Avoid 433921SN/ABaseCPU::serialize(std::ostream &os) 434921SN/A{ 4354000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(instCnt); 4365647Sgblack@eecs.umich.edu interrupts->serialize(os); 437921SN/A} 438921SN/A 439921SN/Avoid 440921SN/ABaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 441921SN/A{ 4424000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(instCnt); 4435647Sgblack@eecs.umich.edu interrupts->unserialize(cp, section); 444921SN/A} 445921SN/A 4462SN/A#endif // FULL_SYSTEM 4472SN/A 4481191SN/Avoid 4491191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 4501191SN/A{ 4511191SN/A if (!debugSymbolTable) 4521191SN/A return; 4531191SN/A 4541191SN/A // if pc enters different function, print new function symbol and 4551191SN/A // update saved range. Otherwise do nothing. 4561191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 4571191SN/A string sym_str; 4581191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 4591191SN/A currentFunctionStart, 4601191SN/A currentFunctionEnd); 4611191SN/A 4621191SN/A if (!found) { 4631191SN/A // no symbol found: use addr as label 4641191SN/A sym_str = csprintf("0x%x", pc); 4651191SN/A currentFunctionStart = pc; 4661191SN/A currentFunctionEnd = pc + 1; 4671191SN/A } 4681191SN/A 4691191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 4707823Ssteve.reinhardt@amd.com curTick() - functionEntryTick, curTick(), sym_str); 4717823Ssteve.reinhardt@amd.com functionEntryTick = curTick(); 4721191SN/A } 4731191SN/A} 474