base.cc revision 4776
12SN/A/*
21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
292665Ssaidi@eecs.umich.edu *          Nathan Binkert
302SN/A */
312SN/A
321388SN/A#include <iostream>
332SN/A#include <string>
342SN/A#include <sstream>
352SN/A
361191SN/A#include "base/cprintf.hh"
371191SN/A#include "base/loader/symtab.hh"
381191SN/A#include "base/misc.hh"
391388SN/A#include "base/output.hh"
401717SN/A#include "cpu/base.hh"
412651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh"
422680Sktlim@umich.edu#include "cpu/thread_context.hh"
431977SN/A#include "cpu/profile.hh"
443144Shsul@eecs.umich.edu#include "sim/sim_exit.hh"
452190SN/A#include "sim/process.hh"
4656SN/A#include "sim/sim_events.hh"
472190SN/A#include "sim/system.hh"
482SN/A
491062SN/A#include "base/trace.hh"
501062SN/A
512359SN/A// Hack
522359SN/A#include "sim/stat_control.hh"
532359SN/A
542SN/Ausing namespace std;
552SN/A
562SN/Avector<BaseCPU *> BaseCPU::cpuList;
572SN/A
582SN/A// This variable reflects the max number of threads in any CPU.  Be
592SN/A// careful to only use it once all the CPUs that you care about have
602SN/A// been initialized
612SN/Aint maxThreadsPerCPU = 1;
622SN/A
633126Sktlim@umich.eduCPUProgressEvent::CPUProgressEvent(EventQueue *q, Tick ival,
643126Sktlim@umich.edu                                   BaseCPU *_cpu)
654075Sbinkertn@umich.edu    : Event(q, Event::Progress_Event_Pri), interval(ival),
663126Sktlim@umich.edu      lastNumInst(0), cpu(_cpu)
673126Sktlim@umich.edu{
683126Sktlim@umich.edu    if (interval)
693126Sktlim@umich.edu        schedule(curTick + interval);
703126Sktlim@umich.edu}
713126Sktlim@umich.edu
722356SN/Avoid
732356SN/ACPUProgressEvent::process()
742356SN/A{
752367SN/A    Counter temp = cpu->totalInstructions();
762356SN/A#ifndef NDEBUG
772356SN/A    double ipc = double(temp - lastNumInst) / (interval / cpu->cycles(1));
782367SN/A
792356SN/A    DPRINTFN("%s progress event, instructions committed: %lli, IPC: %0.8d\n",
802356SN/A             cpu->name(), temp - lastNumInst, ipc);
812356SN/A    ipc = 0.0;
822367SN/A#else
832367SN/A    cprintf("%lli: %s progress event, instructions committed: %lli\n",
842367SN/A            curTick, cpu->name(), temp - lastNumInst);
852367SN/A#endif
862356SN/A    lastNumInst = temp;
872356SN/A    schedule(curTick + interval);
882356SN/A}
892356SN/A
902356SN/Aconst char *
912356SN/ACPUProgressEvent::description()
922356SN/A{
932356SN/A    return "CPU Progress event";
942356SN/A}
952356SN/A
961858SN/A#if FULL_SYSTEM
971400SN/ABaseCPU::BaseCPU(Params *p)
983923Shsul@eecs.umich.edu    : MemObject(p->name), clock(p->clock), instCnt(0),
993661Srdreslin@umich.edu      params(p), number_of_threads(p->numberOfThreads), system(p->system),
1003661Srdreslin@umich.edu      phase(p->phase)
1012SN/A#else
1021400SN/ABaseCPU::BaseCPU(Params *p)
1032856Srdreslin@umich.edu    : MemObject(p->name), clock(p->clock), params(p),
1043661Srdreslin@umich.edu      number_of_threads(p->numberOfThreads), system(p->system),
1053661Srdreslin@umich.edu      phase(p->phase)
1062SN/A#endif
1072SN/A{
1082359SN/A//    currentTick = curTick;
1092831Sksewell@umich.edu    DPRINTF(FullCPU, "BaseCPU: Creating object, mem address %#x.\n", this);
1101062SN/A
1112SN/A    // add self to global list of CPUs
1122SN/A    cpuList.push_back(this);
1132SN/A
1142831Sksewell@umich.edu    DPRINTF(FullCPU, "BaseCPU: CPU added to cpuList, mem address %#x.\n",
1151062SN/A            this);
1161062SN/A
1172SN/A    if (number_of_threads > maxThreadsPerCPU)
1182SN/A        maxThreadsPerCPU = number_of_threads;
1192SN/A
1202SN/A    // allocate per-thread instruction-based event queues
1211354SN/A    comInstEventQueue = new EventQueue *[number_of_threads];
1222SN/A    for (int i = 0; i < number_of_threads; ++i)
123503SN/A        comInstEventQueue[i] = new EventQueue("instruction-based event queue");
1242SN/A
1252SN/A    //
1262SN/A    // set up instruction-count-based termination events, if any
1272SN/A    //
1281400SN/A    if (p->max_insts_any_thread != 0)
1292SN/A        for (int i = 0; i < number_of_threads; ++i)
1303144Shsul@eecs.umich.edu            schedExitSimLoop("a thread reached the max instruction count",
1313144Shsul@eecs.umich.edu                             p->max_insts_any_thread, 0,
1323144Shsul@eecs.umich.edu                             comInstEventQueue[i]);
1332SN/A
1341400SN/A    if (p->max_insts_all_threads != 0) {
1352SN/A        // allocate & initialize shared downcounter: each event will
1362SN/A        // decrement this when triggered; simulation will terminate
1372SN/A        // when counter reaches 0
1382SN/A        int *counter = new int;
1392SN/A        *counter = number_of_threads;
1402SN/A        for (int i = 0; i < number_of_threads; ++i)
141503SN/A            new CountedExitEvent(comInstEventQueue[i],
1422SN/A                "all threads reached the max instruction count",
1431400SN/A                p->max_insts_all_threads, *counter);
1442SN/A    }
1452SN/A
146124SN/A    // allocate per-thread load-based event queues
1471354SN/A    comLoadEventQueue = new EventQueue *[number_of_threads];
148124SN/A    for (int i = 0; i < number_of_threads; ++i)
149124SN/A        comLoadEventQueue[i] = new EventQueue("load-based event queue");
150124SN/A
151124SN/A    //
152124SN/A    // set up instruction-count-based termination events, if any
153124SN/A    //
1541400SN/A    if (p->max_loads_any_thread != 0)
155124SN/A        for (int i = 0; i < number_of_threads; ++i)
1563144Shsul@eecs.umich.edu            schedExitSimLoop("a thread reached the max load count",
1573144Shsul@eecs.umich.edu                             p->max_loads_any_thread, 0,
1583144Shsul@eecs.umich.edu                             comLoadEventQueue[i]);
159124SN/A
1601400SN/A    if (p->max_loads_all_threads != 0) {
161124SN/A        // allocate & initialize shared downcounter: each event will
162124SN/A        // decrement this when triggered; simulation will terminate
163124SN/A        // when counter reaches 0
164124SN/A        int *counter = new int;
165124SN/A        *counter = number_of_threads;
166124SN/A        for (int i = 0; i < number_of_threads; ++i)
167124SN/A            new CountedExitEvent(comLoadEventQueue[i],
168124SN/A                "all threads reached the max load count",
1691400SN/A                p->max_loads_all_threads, *counter);
170124SN/A    }
171124SN/A
1721191SN/A    functionTracingEnabled = false;
1731400SN/A    if (p->functionTrace) {
1741388SN/A        functionTraceStream = simout.find(csprintf("ftrace.%s", name()));
1751191SN/A        currentFunctionStart = currentFunctionEnd = 0;
1761400SN/A        functionEntryTick = p->functionTraceStart;
1771191SN/A
1781400SN/A        if (p->functionTraceStart == 0) {
1791191SN/A            functionTracingEnabled = true;
1801191SN/A        } else {
1814471Sstever@eecs.umich.edu            new EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace>(this,
1824471Sstever@eecs.umich.edu                                                                     p->functionTraceStart,
1834471Sstever@eecs.umich.edu                                                                     true);
1841191SN/A        }
1851191SN/A    }
1861917SN/A#if FULL_SYSTEM
1871917SN/A    profileEvent = NULL;
1881917SN/A    if (params->profile)
1891917SN/A        profileEvent = new ProfileEvent(this, params->profile);
1901917SN/A#endif
1914776Sgblack@eecs.umich.edu    tracer = params->tracer;
1922SN/A}
1932SN/A
1941917SN/ABaseCPU::Params::Params()
1951917SN/A{
1961917SN/A#if FULL_SYSTEM
1971917SN/A    profile = false;
1981917SN/A#endif
1992315SN/A    checker = NULL;
2004776Sgblack@eecs.umich.edu    tracer = NULL;
2011917SN/A}
2021191SN/A
2031191SN/Avoid
2041191SN/ABaseCPU::enableFunctionTrace()
2051191SN/A{
2061191SN/A    functionTracingEnabled = true;
2071191SN/A}
2081191SN/A
2091191SN/ABaseCPU::~BaseCPU()
2101191SN/A{
2111191SN/A}
2121191SN/A
2131129SN/Avoid
2141129SN/ABaseCPU::init()
2151129SN/A{
2161400SN/A    if (!params->deferRegistration)
2172680Sktlim@umich.edu        registerThreadContexts();
2181129SN/A}
219180SN/A
2202SN/Avoid
2211917SN/ABaseCPU::startup()
2221917SN/A{
2231917SN/A#if FULL_SYSTEM
2241917SN/A    if (!params->deferRegistration && profileEvent)
2251917SN/A        profileEvent->schedule(curTick);
2261917SN/A#endif
2272356SN/A
2282356SN/A    if (params->progress_interval) {
2294031Sktlim@umich.edu        new CPUProgressEvent(&mainEventQueue,
2304031Sktlim@umich.edu                             cycles(params->progress_interval),
2312356SN/A                             this);
2322356SN/A    }
2331917SN/A}
2341917SN/A
2351917SN/A
2361917SN/Avoid
2372SN/ABaseCPU::regStats()
2382SN/A{
239729SN/A    using namespace Stats;
240707SN/A
241707SN/A    numCycles
242707SN/A        .name(name() + ".numCycles")
243707SN/A        .desc("number of cpu cycles simulated")
244707SN/A        ;
245707SN/A
2462680Sktlim@umich.edu    int size = threadContexts.size();
2472SN/A    if (size > 1) {
2482SN/A        for (int i = 0; i < size; ++i) {
2492SN/A            stringstream namestr;
2502SN/A            ccprintf(namestr, "%s.ctx%d", name(), i);
2512680Sktlim@umich.edu            threadContexts[i]->regStats(namestr.str());
2522SN/A        }
2532SN/A    } else if (size == 1)
2542680Sktlim@umich.edu        threadContexts[0]->regStats(name());
2552190SN/A
2562190SN/A#if FULL_SYSTEM
2572190SN/A#endif
2582SN/A}
2592SN/A
2603495Sktlim@umich.eduTick
2613495Sktlim@umich.eduBaseCPU::nextCycle()
2623495Sktlim@umich.edu{
2633661Srdreslin@umich.edu    Tick next_tick = curTick - phase + clock - 1;
2643495Sktlim@umich.edu    next_tick -= (next_tick % clock);
2653661Srdreslin@umich.edu    next_tick += phase;
2663495Sktlim@umich.edu    return next_tick;
2673495Sktlim@umich.edu}
2683495Sktlim@umich.edu
2693495Sktlim@umich.eduTick
2703495Sktlim@umich.eduBaseCPU::nextCycle(Tick begin_tick)
2713495Sktlim@umich.edu{
2723495Sktlim@umich.edu    Tick next_tick = begin_tick;
2734599Sacolyte@umich.edu    if (next_tick % clock != 0)
2744599Sacolyte@umich.edu        next_tick = next_tick - (next_tick % clock) + clock;
2753661Srdreslin@umich.edu    next_tick += phase;
2763495Sktlim@umich.edu
2773495Sktlim@umich.edu    assert(next_tick >= curTick);
2783495Sktlim@umich.edu    return next_tick;
2793495Sktlim@umich.edu}
280180SN/A
281180SN/Avoid
2822680Sktlim@umich.eduBaseCPU::registerThreadContexts()
283180SN/A{
2842680Sktlim@umich.edu    for (int i = 0; i < threadContexts.size(); ++i) {
2852680Sktlim@umich.edu        ThreadContext *tc = threadContexts[i];
2862378SN/A
2871858SN/A#if FULL_SYSTEM
2881806SN/A        int id = params->cpu_id;
2891806SN/A        if (id != -1)
2901806SN/A            id += i;
291180SN/A
2922680Sktlim@umich.edu        tc->setCpuId(system->registerThreadContext(tc, id));
293180SN/A#else
2942680Sktlim@umich.edu        tc->setCpuId(tc->getProcessPtr()->registerThreadContext(tc));
295180SN/A#endif
296180SN/A    }
297180SN/A}
298180SN/A
299180SN/A
3004000Ssaidi@eecs.umich.eduint
3014000Ssaidi@eecs.umich.eduBaseCPU::findContext(ThreadContext *tc)
3024000Ssaidi@eecs.umich.edu{
3034000Ssaidi@eecs.umich.edu    for (int i = 0; i < threadContexts.size(); ++i) {
3044000Ssaidi@eecs.umich.edu        if (tc == threadContexts[i])
3054000Ssaidi@eecs.umich.edu            return i;
3064000Ssaidi@eecs.umich.edu    }
3074000Ssaidi@eecs.umich.edu    return 0;
3084000Ssaidi@eecs.umich.edu}
3094000Ssaidi@eecs.umich.edu
310180SN/Avoid
3112798Sktlim@umich.eduBaseCPU::switchOut()
312180SN/A{
3132359SN/A//    panic("This CPU doesn't support sampling!");
3142359SN/A#if FULL_SYSTEM
3152359SN/A    if (profileEvent && profileEvent->scheduled())
3162359SN/A        profileEvent->deschedule();
3172359SN/A#endif
318180SN/A}
319180SN/A
320180SN/Avoid
3214192Sktlim@umich.eduBaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
322180SN/A{
3232680Sktlim@umich.edu    assert(threadContexts.size() == oldCPU->threadContexts.size());
324180SN/A
3252680Sktlim@umich.edu    for (int i = 0; i < threadContexts.size(); ++i) {
3262680Sktlim@umich.edu        ThreadContext *newTC = threadContexts[i];
3272680Sktlim@umich.edu        ThreadContext *oldTC = oldCPU->threadContexts[i];
328180SN/A
3292680Sktlim@umich.edu        newTC->takeOverFrom(oldTC);
3302651Ssaidi@eecs.umich.edu
3312680Sktlim@umich.edu        CpuEvent::replaceThreadContext(oldTC, newTC);
3322651Ssaidi@eecs.umich.edu
3332680Sktlim@umich.edu        assert(newTC->readCpuId() == oldTC->readCpuId());
3341858SN/A#if FULL_SYSTEM
3352680Sktlim@umich.edu        system->replaceThreadContext(newTC, newTC->readCpuId());
336180SN/A#else
3372680Sktlim@umich.edu        assert(newTC->getProcessPtr() == oldTC->getProcessPtr());
3382680Sktlim@umich.edu        newTC->getProcessPtr()->replaceThreadContext(newTC, newTC->readCpuId());
339180SN/A#endif
3402359SN/A
3412359SN/A//    TheISA::compareXCs(oldXC, newXC);
342180SN/A    }
343605SN/A
3441858SN/A#if FULL_SYSTEM
3453520Sgblack@eecs.umich.edu    interrupts = oldCPU->interrupts;
3462254SN/A
3472680Sktlim@umich.edu    for (int i = 0; i < threadContexts.size(); ++i)
3482680Sktlim@umich.edu        threadContexts[i]->profileClear();
3492254SN/A
3502359SN/A    // The Sampler must take care of this!
3512359SN/A//    if (profileEvent)
3522359SN/A//        profileEvent->schedule(curTick);
353612SN/A#endif
3544192Sktlim@umich.edu
3554192Sktlim@umich.edu    // Connect new CPU to old CPU's memory only if new CPU isn't
3564192Sktlim@umich.edu    // connected to anything.  Also connect old CPU's memory to new
3574192Sktlim@umich.edu    // CPU.
3584192Sktlim@umich.edu    Port *peer;
3594192Sktlim@umich.edu    if (ic->getPeer() == NULL) {
3604192Sktlim@umich.edu        peer = oldCPU->getPort("icache_port")->getPeer();
3614192Sktlim@umich.edu        ic->setPeer(peer);
3624192Sktlim@umich.edu    } else {
3634192Sktlim@umich.edu        peer = ic->getPeer();
3644192Sktlim@umich.edu    }
3654192Sktlim@umich.edu    peer->setPeer(ic);
3664192Sktlim@umich.edu
3674192Sktlim@umich.edu    if (dc->getPeer() == NULL) {
3684192Sktlim@umich.edu        peer = oldCPU->getPort("dcache_port")->getPeer();
3694192Sktlim@umich.edu        dc->setPeer(peer);
3704192Sktlim@umich.edu    } else {
3714192Sktlim@umich.edu        peer = dc->getPeer();
3724192Sktlim@umich.edu    }
3734192Sktlim@umich.edu    peer->setPeer(dc);
374180SN/A}
375180SN/A
376180SN/A
3771858SN/A#if FULL_SYSTEM
3781917SN/ABaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, int _interval)
3791917SN/A    : Event(&mainEventQueue), cpu(_cpu), interval(_interval)
3801917SN/A{ }
3811917SN/A
3821917SN/Avoid
3831917SN/ABaseCPU::ProfileEvent::process()
3841917SN/A{
3852680Sktlim@umich.edu    for (int i = 0, size = cpu->threadContexts.size(); i < size; ++i) {
3862680Sktlim@umich.edu        ThreadContext *tc = cpu->threadContexts[i];
3872680Sktlim@umich.edu        tc->profileSample();
3881917SN/A    }
3892254SN/A
3901917SN/A    schedule(curTick + interval);
3911917SN/A}
3921917SN/A
3932SN/Avoid
3942SN/ABaseCPU::post_interrupt(int int_num, int index)
3952SN/A{
3963520Sgblack@eecs.umich.edu    interrupts.post(int_num, index);
3972SN/A}
3982SN/A
3992SN/Avoid
4002SN/ABaseCPU::clear_interrupt(int int_num, int index)
4012SN/A{
4023520Sgblack@eecs.umich.edu    interrupts.clear(int_num, index);
4032SN/A}
4042SN/A
4052SN/Avoid
4062SN/ABaseCPU::clear_interrupts()
4072SN/A{
4083520Sgblack@eecs.umich.edu    interrupts.clear_all();
4092SN/A}
4102SN/A
4114103Ssaidi@eecs.umich.eduuint64_t
4124103Ssaidi@eecs.umich.eduBaseCPU::get_interrupts(int int_num)
4134103Ssaidi@eecs.umich.edu{
4144103Ssaidi@eecs.umich.edu    return interrupts.get_vec(int_num);
4154103Ssaidi@eecs.umich.edu}
416921SN/A
417921SN/Avoid
418921SN/ABaseCPU::serialize(std::ostream &os)
419921SN/A{
4204000Ssaidi@eecs.umich.edu    SERIALIZE_SCALAR(instCnt);
4213520Sgblack@eecs.umich.edu    interrupts.serialize(os);
422921SN/A}
423921SN/A
424921SN/Avoid
425921SN/ABaseCPU::unserialize(Checkpoint *cp, const std::string &section)
426921SN/A{
4274000Ssaidi@eecs.umich.edu    UNSERIALIZE_SCALAR(instCnt);
4283520Sgblack@eecs.umich.edu    interrupts.unserialize(cp, section);
429921SN/A}
430921SN/A
4312SN/A#endif // FULL_SYSTEM
4322SN/A
4331191SN/Avoid
4341191SN/ABaseCPU::traceFunctionsInternal(Addr pc)
4351191SN/A{
4361191SN/A    if (!debugSymbolTable)
4371191SN/A        return;
4381191SN/A
4391191SN/A    // if pc enters different function, print new function symbol and
4401191SN/A    // update saved range.  Otherwise do nothing.
4411191SN/A    if (pc < currentFunctionStart || pc >= currentFunctionEnd) {
4421191SN/A        string sym_str;
4431191SN/A        bool found = debugSymbolTable->findNearestSymbol(pc, sym_str,
4441191SN/A                                                         currentFunctionStart,
4451191SN/A                                                         currentFunctionEnd);
4461191SN/A
4471191SN/A        if (!found) {
4481191SN/A            // no symbol found: use addr as label
4491191SN/A            sym_str = csprintf("0x%x", pc);
4501191SN/A            currentFunctionStart = pc;
4511191SN/A            currentFunctionEnd = pc + 1;
4521191SN/A        }
4531191SN/A
4541191SN/A        ccprintf(*functionTraceStream, " (%d)\n%d: %s",
4551191SN/A                 curTick - functionEntryTick, curTick, sym_str);
4561191SN/A        functionEntryTick = curTick;
4571191SN/A    }
4581191SN/A}
459