base.cc revision 3126
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 321388SN/A#include <iostream> 332SN/A#include <string> 342SN/A#include <sstream> 352SN/A 361191SN/A#include "base/cprintf.hh" 371191SN/A#include "base/loader/symtab.hh" 381191SN/A#include "base/misc.hh" 391388SN/A#include "base/output.hh" 401717SN/A#include "cpu/base.hh" 412651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 422680Sktlim@umich.edu#include "cpu/thread_context.hh" 431977SN/A#include "cpu/profile.hh" 44161SN/A#include "sim/param.hh" 452190SN/A#include "sim/process.hh" 4656SN/A#include "sim/sim_events.hh" 472190SN/A#include "sim/system.hh" 482SN/A 491062SN/A#include "base/trace.hh" 501062SN/A 512359SN/A// Hack 522359SN/A#include "sim/stat_control.hh" 532359SN/A 542SN/Ausing namespace std; 552SN/A 562SN/Avector<BaseCPU *> BaseCPU::cpuList; 572SN/A 582SN/A// This variable reflects the max number of threads in any CPU. Be 592SN/A// careful to only use it once all the CPUs that you care about have 602SN/A// been initialized 612SN/Aint maxThreadsPerCPU = 1; 622SN/A 633126Sktlim@umich.eduCPUProgressEvent::CPUProgressEvent(EventQueue *q, Tick ival, 643126Sktlim@umich.edu BaseCPU *_cpu) 653126Sktlim@umich.edu : Event(q, Event::Stat_Event_Pri), interval(ival), 663126Sktlim@umich.edu lastNumInst(0), cpu(_cpu) 673126Sktlim@umich.edu{ 683126Sktlim@umich.edu if (interval) 693126Sktlim@umich.edu schedule(curTick + interval); 703126Sktlim@umich.edu} 713126Sktlim@umich.edu 722356SN/Avoid 732356SN/ACPUProgressEvent::process() 742356SN/A{ 752367SN/A Counter temp = cpu->totalInstructions(); 762356SN/A#ifndef NDEBUG 772356SN/A double ipc = double(temp - lastNumInst) / (interval / cpu->cycles(1)); 782367SN/A 792356SN/A DPRINTFN("%s progress event, instructions committed: %lli, IPC: %0.8d\n", 802356SN/A cpu->name(), temp - lastNumInst, ipc); 812356SN/A ipc = 0.0; 822367SN/A#else 832367SN/A cprintf("%lli: %s progress event, instructions committed: %lli\n", 842367SN/A curTick, cpu->name(), temp - lastNumInst); 852367SN/A#endif 862356SN/A lastNumInst = temp; 872356SN/A schedule(curTick + interval); 882356SN/A} 892356SN/A 902356SN/Aconst char * 912356SN/ACPUProgressEvent::description() 922356SN/A{ 932356SN/A return "CPU Progress event"; 942356SN/A} 952356SN/A 961858SN/A#if FULL_SYSTEM 971400SN/ABaseCPU::BaseCPU(Params *p) 982881Srdreslin@umich.edu : MemObject(p->name), clock(p->clock), checkInterrupts(true), 991400SN/A params(p), number_of_threads(p->numberOfThreads), system(p->system) 1002SN/A#else 1011400SN/ABaseCPU::BaseCPU(Params *p) 1022856Srdreslin@umich.edu : MemObject(p->name), clock(p->clock), params(p), 1032378SN/A number_of_threads(p->numberOfThreads), system(p->system) 1042SN/A#endif 1052SN/A{ 1062359SN/A// currentTick = curTick; 1072831Sksewell@umich.edu DPRINTF(FullCPU, "BaseCPU: Creating object, mem address %#x.\n", this); 1081062SN/A 1092SN/A // add self to global list of CPUs 1102SN/A cpuList.push_back(this); 1112SN/A 1122831Sksewell@umich.edu DPRINTF(FullCPU, "BaseCPU: CPU added to cpuList, mem address %#x.\n", 1131062SN/A this); 1141062SN/A 1152SN/A if (number_of_threads > maxThreadsPerCPU) 1162SN/A maxThreadsPerCPU = number_of_threads; 1172SN/A 1182SN/A // allocate per-thread instruction-based event queues 1191354SN/A comInstEventQueue = new EventQueue *[number_of_threads]; 1202SN/A for (int i = 0; i < number_of_threads; ++i) 121503SN/A comInstEventQueue[i] = new EventQueue("instruction-based event queue"); 1222SN/A 1232SN/A // 1242SN/A // set up instruction-count-based termination events, if any 1252SN/A // 1261400SN/A if (p->max_insts_any_thread != 0) 1272SN/A for (int i = 0; i < number_of_threads; ++i) 1282667Sstever@eecs.umich.edu new SimLoopExitEvent(comInstEventQueue[i], p->max_insts_any_thread, 1292667Sstever@eecs.umich.edu "a thread reached the max instruction count"); 1302SN/A 1311400SN/A if (p->max_insts_all_threads != 0) { 1322SN/A // allocate & initialize shared downcounter: each event will 1332SN/A // decrement this when triggered; simulation will terminate 1342SN/A // when counter reaches 0 1352SN/A int *counter = new int; 1362SN/A *counter = number_of_threads; 1372SN/A for (int i = 0; i < number_of_threads; ++i) 138503SN/A new CountedExitEvent(comInstEventQueue[i], 1392SN/A "all threads reached the max instruction count", 1401400SN/A p->max_insts_all_threads, *counter); 1412SN/A } 1422SN/A 143124SN/A // allocate per-thread load-based event queues 1441354SN/A comLoadEventQueue = new EventQueue *[number_of_threads]; 145124SN/A for (int i = 0; i < number_of_threads; ++i) 146124SN/A comLoadEventQueue[i] = new EventQueue("load-based event queue"); 147124SN/A 148124SN/A // 149124SN/A // set up instruction-count-based termination events, if any 150124SN/A // 1511400SN/A if (p->max_loads_any_thread != 0) 152124SN/A for (int i = 0; i < number_of_threads; ++i) 1532667Sstever@eecs.umich.edu new SimLoopExitEvent(comLoadEventQueue[i], p->max_loads_any_thread, 1542667Sstever@eecs.umich.edu "a thread reached the max load count"); 155124SN/A 1561400SN/A if (p->max_loads_all_threads != 0) { 157124SN/A // allocate & initialize shared downcounter: each event will 158124SN/A // decrement this when triggered; simulation will terminate 159124SN/A // when counter reaches 0 160124SN/A int *counter = new int; 161124SN/A *counter = number_of_threads; 162124SN/A for (int i = 0; i < number_of_threads; ++i) 163124SN/A new CountedExitEvent(comLoadEventQueue[i], 164124SN/A "all threads reached the max load count", 1651400SN/A p->max_loads_all_threads, *counter); 166124SN/A } 167124SN/A 1681858SN/A#if FULL_SYSTEM 1692SN/A memset(interrupts, 0, sizeof(interrupts)); 1702SN/A intstatus = 0; 1712SN/A#endif 1721191SN/A 1731191SN/A functionTracingEnabled = false; 1741400SN/A if (p->functionTrace) { 1751388SN/A functionTraceStream = simout.find(csprintf("ftrace.%s", name())); 1761191SN/A currentFunctionStart = currentFunctionEnd = 0; 1771400SN/A functionEntryTick = p->functionTraceStart; 1781191SN/A 1791400SN/A if (p->functionTraceStart == 0) { 1801191SN/A functionTracingEnabled = true; 1811191SN/A } else { 1821191SN/A Event *e = 1831191SN/A new EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace>(this, 1841191SN/A true); 1851400SN/A e->schedule(p->functionTraceStart); 1861191SN/A } 1871191SN/A } 1881917SN/A#if FULL_SYSTEM 1891917SN/A profileEvent = NULL; 1901917SN/A if (params->profile) 1911917SN/A profileEvent = new ProfileEvent(this, params->profile); 1921917SN/A#endif 1932SN/A} 1942SN/A 1951917SN/ABaseCPU::Params::Params() 1961917SN/A{ 1971917SN/A#if FULL_SYSTEM 1981917SN/A profile = false; 1991917SN/A#endif 2002315SN/A checker = NULL; 2011917SN/A} 2021191SN/A 2031191SN/Avoid 2041191SN/ABaseCPU::enableFunctionTrace() 2051191SN/A{ 2061191SN/A functionTracingEnabled = true; 2071191SN/A} 2081191SN/A 2091191SN/ABaseCPU::~BaseCPU() 2101191SN/A{ 2111191SN/A} 2121191SN/A 2131129SN/Avoid 2141129SN/ABaseCPU::init() 2151129SN/A{ 2161400SN/A if (!params->deferRegistration) 2172680Sktlim@umich.edu registerThreadContexts(); 2181129SN/A} 219180SN/A 2202SN/Avoid 2211917SN/ABaseCPU::startup() 2221917SN/A{ 2231917SN/A#if FULL_SYSTEM 2241917SN/A if (!params->deferRegistration && profileEvent) 2251917SN/A profileEvent->schedule(curTick); 2261917SN/A#endif 2272356SN/A 2282356SN/A if (params->progress_interval) { 2292356SN/A new CPUProgressEvent(&mainEventQueue, params->progress_interval, 2302356SN/A this); 2312356SN/A } 2321917SN/A} 2331917SN/A 2341917SN/A 2351917SN/Avoid 2362SN/ABaseCPU::regStats() 2372SN/A{ 238729SN/A using namespace Stats; 239707SN/A 240707SN/A numCycles 241707SN/A .name(name() + ".numCycles") 242707SN/A .desc("number of cpu cycles simulated") 243707SN/A ; 244707SN/A 2452680Sktlim@umich.edu int size = threadContexts.size(); 2462SN/A if (size > 1) { 2472SN/A for (int i = 0; i < size; ++i) { 2482SN/A stringstream namestr; 2492SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 2502680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 2512SN/A } 2522SN/A } else if (size == 1) 2532680Sktlim@umich.edu threadContexts[0]->regStats(name()); 2542190SN/A 2552190SN/A#if FULL_SYSTEM 2562190SN/A#endif 2572SN/A} 2582SN/A 259180SN/A 260180SN/Avoid 2612680Sktlim@umich.eduBaseCPU::registerThreadContexts() 262180SN/A{ 2632680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2642680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2652378SN/A 2661858SN/A#if FULL_SYSTEM 2671806SN/A int id = params->cpu_id; 2681806SN/A if (id != -1) 2691806SN/A id += i; 270180SN/A 2712680Sktlim@umich.edu tc->setCpuId(system->registerThreadContext(tc, id)); 272180SN/A#else 2732680Sktlim@umich.edu tc->setCpuId(tc->getProcessPtr()->registerThreadContext(tc)); 274180SN/A#endif 275180SN/A } 276180SN/A} 277180SN/A 278180SN/A 279180SN/Avoid 2802798Sktlim@umich.eduBaseCPU::switchOut() 281180SN/A{ 2822359SN/A// panic("This CPU doesn't support sampling!"); 2832359SN/A#if FULL_SYSTEM 2842359SN/A if (profileEvent && profileEvent->scheduled()) 2852359SN/A profileEvent->deschedule(); 2862359SN/A#endif 287180SN/A} 288180SN/A 289180SN/Avoid 290180SN/ABaseCPU::takeOverFrom(BaseCPU *oldCPU) 291180SN/A{ 2922680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 293180SN/A 2942680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2952680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 2962680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 297180SN/A 2982680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 2992651Ssaidi@eecs.umich.edu 3002680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 3012651Ssaidi@eecs.umich.edu 3022680Sktlim@umich.edu assert(newTC->readCpuId() == oldTC->readCpuId()); 3031858SN/A#if FULL_SYSTEM 3042680Sktlim@umich.edu system->replaceThreadContext(newTC, newTC->readCpuId()); 305180SN/A#else 3062680Sktlim@umich.edu assert(newTC->getProcessPtr() == oldTC->getProcessPtr()); 3072680Sktlim@umich.edu newTC->getProcessPtr()->replaceThreadContext(newTC, newTC->readCpuId()); 308180SN/A#endif 3092359SN/A 3102359SN/A// TheISA::compareXCs(oldXC, newXC); 311180SN/A } 312605SN/A 3131858SN/A#if FULL_SYSTEM 3142107SN/A for (int i = 0; i < TheISA::NumInterruptLevels; ++i) 315605SN/A interrupts[i] = oldCPU->interrupts[i]; 316605SN/A intstatus = oldCPU->intstatus; 3172359SN/A checkInterrupts = oldCPU->checkInterrupts; 3182254SN/A 3192680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) 3202680Sktlim@umich.edu threadContexts[i]->profileClear(); 3212254SN/A 3222359SN/A // The Sampler must take care of this! 3232359SN/A// if (profileEvent) 3242359SN/A// profileEvent->schedule(curTick); 325612SN/A#endif 326180SN/A} 327180SN/A 328180SN/A 3291858SN/A#if FULL_SYSTEM 3301917SN/ABaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, int _interval) 3311917SN/A : Event(&mainEventQueue), cpu(_cpu), interval(_interval) 3321917SN/A{ } 3331917SN/A 3341917SN/Avoid 3351917SN/ABaseCPU::ProfileEvent::process() 3361917SN/A{ 3372680Sktlim@umich.edu for (int i = 0, size = cpu->threadContexts.size(); i < size; ++i) { 3382680Sktlim@umich.edu ThreadContext *tc = cpu->threadContexts[i]; 3392680Sktlim@umich.edu tc->profileSample(); 3401917SN/A } 3412254SN/A 3421917SN/A schedule(curTick + interval); 3431917SN/A} 3441917SN/A 3452SN/Avoid 3462SN/ABaseCPU::post_interrupt(int int_num, int index) 3472SN/A{ 3482SN/A DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 3492SN/A 3502107SN/A if (int_num < 0 || int_num >= TheISA::NumInterruptLevels) 3512SN/A panic("int_num out of bounds\n"); 3522SN/A 353822SN/A if (index < 0 || index >= sizeof(uint64_t) * 8) 3542SN/A panic("int_num out of bounds\n"); 3552SN/A 3561133SN/A checkInterrupts = true; 3572SN/A interrupts[int_num] |= 1 << index; 3582SN/A intstatus |= (ULL(1) << int_num); 3592SN/A} 3602SN/A 3612SN/Avoid 3622SN/ABaseCPU::clear_interrupt(int int_num, int index) 3632SN/A{ 3642SN/A DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 3652SN/A 3662107SN/A if (int_num < 0 || int_num >= TheISA::NumInterruptLevels) 3672SN/A panic("int_num out of bounds\n"); 3682SN/A 369822SN/A if (index < 0 || index >= sizeof(uint64_t) * 8) 3702SN/A panic("int_num out of bounds\n"); 3712SN/A 3722SN/A interrupts[int_num] &= ~(1 << index); 3732SN/A if (interrupts[int_num] == 0) 3742SN/A intstatus &= ~(ULL(1) << int_num); 3752SN/A} 3762SN/A 3772SN/Avoid 3782SN/ABaseCPU::clear_interrupts() 3792SN/A{ 3802SN/A DPRINTF(Interrupt, "Interrupts all cleared\n"); 3812SN/A 3822SN/A memset(interrupts, 0, sizeof(interrupts)); 3832SN/A intstatus = 0; 3842SN/A} 3852SN/A 386921SN/A 387921SN/Avoid 388921SN/ABaseCPU::serialize(std::ostream &os) 389921SN/A{ 3902107SN/A SERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels); 391921SN/A SERIALIZE_SCALAR(intstatus); 392921SN/A} 393921SN/A 394921SN/Avoid 395921SN/ABaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 396921SN/A{ 3972107SN/A UNSERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels); 398921SN/A UNSERIALIZE_SCALAR(intstatus); 399921SN/A} 400921SN/A 4012SN/A#endif // FULL_SYSTEM 4022SN/A 4031191SN/Avoid 4041191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 4051191SN/A{ 4061191SN/A if (!debugSymbolTable) 4071191SN/A return; 4081191SN/A 4091191SN/A // if pc enters different function, print new function symbol and 4101191SN/A // update saved range. Otherwise do nothing. 4111191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 4121191SN/A string sym_str; 4131191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 4141191SN/A currentFunctionStart, 4151191SN/A currentFunctionEnd); 4161191SN/A 4171191SN/A if (!found) { 4181191SN/A // no symbol found: use addr as label 4191191SN/A sym_str = csprintf("0x%x", pc); 4201191SN/A currentFunctionStart = pc; 4211191SN/A currentFunctionEnd = pc + 1; 4221191SN/A } 4231191SN/A 4241191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 4251191SN/A curTick - functionEntryTick, curTick, sym_str); 4261191SN/A functionEntryTick = curTick; 4271191SN/A } 4281191SN/A} 4291191SN/A 4301191SN/A 4312SN/ADEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU) 432