base.cc revision 2798
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 321388SN/A#include <iostream> 332SN/A#include <string> 342SN/A#include <sstream> 352SN/A 361191SN/A#include "base/cprintf.hh" 371191SN/A#include "base/loader/symtab.hh" 381191SN/A#include "base/misc.hh" 391388SN/A#include "base/output.hh" 401717SN/A#include "cpu/base.hh" 412651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 422680Sktlim@umich.edu#include "cpu/thread_context.hh" 431977SN/A#include "cpu/profile.hh" 441717SN/A#include "cpu/sampler/sampler.hh" 45161SN/A#include "sim/param.hh" 462190SN/A#include "sim/process.hh" 4756SN/A#include "sim/sim_events.hh" 482190SN/A#include "sim/system.hh" 492SN/A 501062SN/A#include "base/trace.hh" 511062SN/A 522SN/Ausing namespace std; 532SN/A 542SN/Avector<BaseCPU *> BaseCPU::cpuList; 552SN/A 562SN/A// This variable reflects the max number of threads in any CPU. Be 572SN/A// careful to only use it once all the CPUs that you care about have 582SN/A// been initialized 592SN/Aint maxThreadsPerCPU = 1; 602SN/A 611858SN/A#if FULL_SYSTEM 621400SN/ABaseCPU::BaseCPU(Params *p) 631695SN/A : SimObject(p->name), clock(p->clock), checkInterrupts(true), 641400SN/A params(p), number_of_threads(p->numberOfThreads), system(p->system) 652SN/A#else 661400SN/ABaseCPU::BaseCPU(Params *p) 671695SN/A : SimObject(p->name), clock(p->clock), params(p), 682378SN/A number_of_threads(p->numberOfThreads), system(p->system) 692SN/A#endif 702SN/A{ 711062SN/A DPRINTF(FullCPU, "BaseCPU: Creating object, mem address %#x.\n", this); 721062SN/A 732SN/A // add self to global list of CPUs 742SN/A cpuList.push_back(this); 752SN/A 761062SN/A DPRINTF(FullCPU, "BaseCPU: CPU added to cpuList, mem address %#x.\n", 771062SN/A this); 781062SN/A 792SN/A if (number_of_threads > maxThreadsPerCPU) 802SN/A maxThreadsPerCPU = number_of_threads; 812SN/A 822SN/A // allocate per-thread instruction-based event queues 831354SN/A comInstEventQueue = new EventQueue *[number_of_threads]; 842SN/A for (int i = 0; i < number_of_threads; ++i) 85503SN/A comInstEventQueue[i] = new EventQueue("instruction-based event queue"); 862SN/A 872SN/A // 882SN/A // set up instruction-count-based termination events, if any 892SN/A // 901400SN/A if (p->max_insts_any_thread != 0) 912SN/A for (int i = 0; i < number_of_threads; ++i) 922667Sstever@eecs.umich.edu new SimLoopExitEvent(comInstEventQueue[i], p->max_insts_any_thread, 932667Sstever@eecs.umich.edu "a thread reached the max instruction count"); 942SN/A 951400SN/A if (p->max_insts_all_threads != 0) { 962SN/A // allocate & initialize shared downcounter: each event will 972SN/A // decrement this when triggered; simulation will terminate 982SN/A // when counter reaches 0 992SN/A int *counter = new int; 1002SN/A *counter = number_of_threads; 1012SN/A for (int i = 0; i < number_of_threads; ++i) 102503SN/A new CountedExitEvent(comInstEventQueue[i], 1032SN/A "all threads reached the max instruction count", 1041400SN/A p->max_insts_all_threads, *counter); 1052SN/A } 1062SN/A 107124SN/A // allocate per-thread load-based event queues 1081354SN/A comLoadEventQueue = new EventQueue *[number_of_threads]; 109124SN/A for (int i = 0; i < number_of_threads; ++i) 110124SN/A comLoadEventQueue[i] = new EventQueue("load-based event queue"); 111124SN/A 112124SN/A // 113124SN/A // set up instruction-count-based termination events, if any 114124SN/A // 1151400SN/A if (p->max_loads_any_thread != 0) 116124SN/A for (int i = 0; i < number_of_threads; ++i) 1172667Sstever@eecs.umich.edu new SimLoopExitEvent(comLoadEventQueue[i], p->max_loads_any_thread, 1182667Sstever@eecs.umich.edu "a thread reached the max load count"); 119124SN/A 1201400SN/A if (p->max_loads_all_threads != 0) { 121124SN/A // allocate & initialize shared downcounter: each event will 122124SN/A // decrement this when triggered; simulation will terminate 123124SN/A // when counter reaches 0 124124SN/A int *counter = new int; 125124SN/A *counter = number_of_threads; 126124SN/A for (int i = 0; i < number_of_threads; ++i) 127124SN/A new CountedExitEvent(comLoadEventQueue[i], 128124SN/A "all threads reached the max load count", 1291400SN/A p->max_loads_all_threads, *counter); 130124SN/A } 131124SN/A 1321858SN/A#if FULL_SYSTEM 1332SN/A memset(interrupts, 0, sizeof(interrupts)); 1342SN/A intstatus = 0; 1352SN/A#endif 1361191SN/A 1371191SN/A functionTracingEnabled = false; 1381400SN/A if (p->functionTrace) { 1391388SN/A functionTraceStream = simout.find(csprintf("ftrace.%s", name())); 1401191SN/A currentFunctionStart = currentFunctionEnd = 0; 1411400SN/A functionEntryTick = p->functionTraceStart; 1421191SN/A 1431400SN/A if (p->functionTraceStart == 0) { 1441191SN/A functionTracingEnabled = true; 1451191SN/A } else { 1461191SN/A Event *e = 1471191SN/A new EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace>(this, 1481191SN/A true); 1491400SN/A e->schedule(p->functionTraceStart); 1501191SN/A } 1511191SN/A } 1521917SN/A#if FULL_SYSTEM 1531917SN/A profileEvent = NULL; 1541917SN/A if (params->profile) 1551917SN/A profileEvent = new ProfileEvent(this, params->profile); 1561917SN/A#endif 1572190SN/A 1582SN/A} 1592SN/A 1601917SN/ABaseCPU::Params::Params() 1611917SN/A{ 1621917SN/A#if FULL_SYSTEM 1631917SN/A profile = false; 1641917SN/A#endif 1652315SN/A checker = NULL; 1661917SN/A} 1671191SN/A 1681191SN/Avoid 1691191SN/ABaseCPU::enableFunctionTrace() 1701191SN/A{ 1711191SN/A functionTracingEnabled = true; 1721191SN/A} 1731191SN/A 1741191SN/ABaseCPU::~BaseCPU() 1751191SN/A{ 1761191SN/A} 1771191SN/A 1781129SN/Avoid 1791129SN/ABaseCPU::init() 1801129SN/A{ 1811400SN/A if (!params->deferRegistration) 1822680Sktlim@umich.edu registerThreadContexts(); 1831129SN/A} 184180SN/A 1852SN/Avoid 1861917SN/ABaseCPU::startup() 1871917SN/A{ 1881917SN/A#if FULL_SYSTEM 1891917SN/A if (!params->deferRegistration && profileEvent) 1901917SN/A profileEvent->schedule(curTick); 1911917SN/A#endif 1921917SN/A} 1931917SN/A 1941917SN/A 1951917SN/Avoid 1962SN/ABaseCPU::regStats() 1972SN/A{ 198729SN/A using namespace Stats; 199707SN/A 200707SN/A numCycles 201707SN/A .name(name() + ".numCycles") 202707SN/A .desc("number of cpu cycles simulated") 203707SN/A ; 204707SN/A 2052680Sktlim@umich.edu int size = threadContexts.size(); 2062SN/A if (size > 1) { 2072SN/A for (int i = 0; i < size; ++i) { 2082SN/A stringstream namestr; 2092SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 2102680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 2112SN/A } 2122SN/A } else if (size == 1) 2132680Sktlim@umich.edu threadContexts[0]->regStats(name()); 2142190SN/A 2152190SN/A#if FULL_SYSTEM 2162190SN/A#endif 2172SN/A} 2182SN/A 219180SN/A 220180SN/Avoid 2212680Sktlim@umich.eduBaseCPU::registerThreadContexts() 222180SN/A{ 2232680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2242680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2252378SN/A 2261858SN/A#if FULL_SYSTEM 2271806SN/A int id = params->cpu_id; 2281806SN/A if (id != -1) 2291806SN/A id += i; 230180SN/A 2312680Sktlim@umich.edu tc->setCpuId(system->registerThreadContext(tc, id)); 232180SN/A#else 2332680Sktlim@umich.edu tc->setCpuId(tc->getProcessPtr()->registerThreadContext(tc)); 234180SN/A#endif 235180SN/A } 236180SN/A} 237180SN/A 238180SN/A 239180SN/Avoid 2402798Sktlim@umich.eduBaseCPU::switchOut() 241180SN/A{ 2421545SN/A panic("This CPU doesn't support sampling!"); 243180SN/A} 244180SN/A 245180SN/Avoid 246180SN/ABaseCPU::takeOverFrom(BaseCPU *oldCPU) 247180SN/A{ 2482680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 249180SN/A 2502680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2512680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 2522680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 253180SN/A 2542680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 2552651Ssaidi@eecs.umich.edu 2562680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 2572651Ssaidi@eecs.umich.edu 2582680Sktlim@umich.edu assert(newTC->readCpuId() == oldTC->readCpuId()); 2591858SN/A#if FULL_SYSTEM 2602680Sktlim@umich.edu system->replaceThreadContext(newTC, newTC->readCpuId()); 261180SN/A#else 2622680Sktlim@umich.edu assert(newTC->getProcessPtr() == oldTC->getProcessPtr()); 2632680Sktlim@umich.edu newTC->getProcessPtr()->replaceThreadContext(newTC, newTC->readCpuId()); 264180SN/A#endif 265180SN/A } 266605SN/A 2671858SN/A#if FULL_SYSTEM 2682107SN/A for (int i = 0; i < TheISA::NumInterruptLevels; ++i) 269605SN/A interrupts[i] = oldCPU->interrupts[i]; 270605SN/A intstatus = oldCPU->intstatus; 2712254SN/A 2722680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) 2732680Sktlim@umich.edu threadContexts[i]->profileClear(); 2742254SN/A 2751917SN/A if (profileEvent) 2761917SN/A profileEvent->schedule(curTick); 277612SN/A#endif 278180SN/A} 279180SN/A 280180SN/A 2811858SN/A#if FULL_SYSTEM 2821917SN/ABaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, int _interval) 2831917SN/A : Event(&mainEventQueue), cpu(_cpu), interval(_interval) 2841917SN/A{ } 2851917SN/A 2861917SN/Avoid 2871917SN/ABaseCPU::ProfileEvent::process() 2881917SN/A{ 2892680Sktlim@umich.edu for (int i = 0, size = cpu->threadContexts.size(); i < size; ++i) { 2902680Sktlim@umich.edu ThreadContext *tc = cpu->threadContexts[i]; 2912680Sktlim@umich.edu tc->profileSample(); 2921917SN/A } 2932254SN/A 2941917SN/A schedule(curTick + interval); 2951917SN/A} 2961917SN/A 2972SN/Avoid 2982SN/ABaseCPU::post_interrupt(int int_num, int index) 2992SN/A{ 3002SN/A DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 3012SN/A 3022107SN/A if (int_num < 0 || int_num >= TheISA::NumInterruptLevels) 3032SN/A panic("int_num out of bounds\n"); 3042SN/A 305822SN/A if (index < 0 || index >= sizeof(uint64_t) * 8) 3062SN/A panic("int_num out of bounds\n"); 3072SN/A 3081133SN/A checkInterrupts = true; 3092SN/A interrupts[int_num] |= 1 << index; 3102SN/A intstatus |= (ULL(1) << int_num); 3112SN/A} 3122SN/A 3132SN/Avoid 3142SN/ABaseCPU::clear_interrupt(int int_num, int index) 3152SN/A{ 3162SN/A DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 3172SN/A 3182107SN/A if (int_num < 0 || int_num >= TheISA::NumInterruptLevels) 3192SN/A panic("int_num out of bounds\n"); 3202SN/A 321822SN/A if (index < 0 || index >= sizeof(uint64_t) * 8) 3222SN/A panic("int_num out of bounds\n"); 3232SN/A 3242SN/A interrupts[int_num] &= ~(1 << index); 3252SN/A if (interrupts[int_num] == 0) 3262SN/A intstatus &= ~(ULL(1) << int_num); 3272SN/A} 3282SN/A 3292SN/Avoid 3302SN/ABaseCPU::clear_interrupts() 3312SN/A{ 3322SN/A DPRINTF(Interrupt, "Interrupts all cleared\n"); 3332SN/A 3342SN/A memset(interrupts, 0, sizeof(interrupts)); 3352SN/A intstatus = 0; 3362SN/A} 3372SN/A 338921SN/A 339921SN/Avoid 340921SN/ABaseCPU::serialize(std::ostream &os) 341921SN/A{ 3422107SN/A SERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels); 343921SN/A SERIALIZE_SCALAR(intstatus); 344921SN/A} 345921SN/A 346921SN/Avoid 347921SN/ABaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 348921SN/A{ 3492107SN/A UNSERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels); 350921SN/A UNSERIALIZE_SCALAR(intstatus); 351921SN/A} 352921SN/A 3532SN/A#endif // FULL_SYSTEM 3542SN/A 3551191SN/Avoid 3561191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 3571191SN/A{ 3581191SN/A if (!debugSymbolTable) 3591191SN/A return; 3601191SN/A 3611191SN/A // if pc enters different function, print new function symbol and 3621191SN/A // update saved range. Otherwise do nothing. 3631191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 3641191SN/A string sym_str; 3651191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 3661191SN/A currentFunctionStart, 3671191SN/A currentFunctionEnd); 3681191SN/A 3691191SN/A if (!found) { 3701191SN/A // no symbol found: use addr as label 3711191SN/A sym_str = csprintf("0x%x", pc); 3721191SN/A currentFunctionStart = pc; 3731191SN/A currentFunctionEnd = pc + 1; 3741191SN/A } 3751191SN/A 3761191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 3771191SN/A curTick - functionEntryTick, curTick, sym_str); 3781191SN/A functionEntryTick = curTick; 3791191SN/A } 3801191SN/A} 3811191SN/A 3821191SN/A 3832SN/ADEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU) 384