base.cc revision 2665
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 321388SN/A#include <iostream> 332SN/A#include <string> 342SN/A#include <sstream> 352SN/A 361191SN/A#include "base/cprintf.hh" 371191SN/A#include "base/loader/symtab.hh" 381191SN/A#include "base/misc.hh" 391388SN/A#include "base/output.hh" 401717SN/A#include "cpu/base.hh" 412651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 4256SN/A#include "cpu/exec_context.hh" 431977SN/A#include "cpu/profile.hh" 441717SN/A#include "cpu/sampler/sampler.hh" 45161SN/A#include "sim/param.hh" 462190SN/A#include "sim/process.hh" 4756SN/A#include "sim/sim_events.hh" 482190SN/A#include "sim/system.hh" 492SN/A 501062SN/A#include "base/trace.hh" 511062SN/A 522190SN/A#if FULL_SYSTEM 532190SN/A#include "kern/kernel_stats.hh" 542190SN/A#endif 552190SN/A 562SN/Ausing namespace std; 572SN/A 582SN/Avector<BaseCPU *> BaseCPU::cpuList; 592SN/A 602SN/A// This variable reflects the max number of threads in any CPU. Be 612SN/A// careful to only use it once all the CPUs that you care about have 622SN/A// been initialized 632SN/Aint maxThreadsPerCPU = 1; 642SN/A 651858SN/A#if FULL_SYSTEM 661400SN/ABaseCPU::BaseCPU(Params *p) 671695SN/A : SimObject(p->name), clock(p->clock), checkInterrupts(true), 681400SN/A params(p), number_of_threads(p->numberOfThreads), system(p->system) 692SN/A#else 701400SN/ABaseCPU::BaseCPU(Params *p) 711695SN/A : SimObject(p->name), clock(p->clock), params(p), 722378SN/A number_of_threads(p->numberOfThreads), system(p->system) 732SN/A#endif 742SN/A{ 751062SN/A DPRINTF(FullCPU, "BaseCPU: Creating object, mem address %#x.\n", this); 761062SN/A 772SN/A // add self to global list of CPUs 782SN/A cpuList.push_back(this); 792SN/A 801062SN/A DPRINTF(FullCPU, "BaseCPU: CPU added to cpuList, mem address %#x.\n", 811062SN/A this); 821062SN/A 832SN/A if (number_of_threads > maxThreadsPerCPU) 842SN/A maxThreadsPerCPU = number_of_threads; 852SN/A 862SN/A // allocate per-thread instruction-based event queues 871354SN/A comInstEventQueue = new EventQueue *[number_of_threads]; 882SN/A for (int i = 0; i < number_of_threads; ++i) 89503SN/A comInstEventQueue[i] = new EventQueue("instruction-based event queue"); 902SN/A 912SN/A // 922SN/A // set up instruction-count-based termination events, if any 932SN/A // 941400SN/A if (p->max_insts_any_thread != 0) 952SN/A for (int i = 0; i < number_of_threads; ++i) 961400SN/A new SimExitEvent(comInstEventQueue[i], p->max_insts_any_thread, 972SN/A "a thread reached the max instruction count"); 982SN/A 991400SN/A if (p->max_insts_all_threads != 0) { 1002SN/A // allocate & initialize shared downcounter: each event will 1012SN/A // decrement this when triggered; simulation will terminate 1022SN/A // when counter reaches 0 1032SN/A int *counter = new int; 1042SN/A *counter = number_of_threads; 1052SN/A for (int i = 0; i < number_of_threads; ++i) 106503SN/A new CountedExitEvent(comInstEventQueue[i], 1072SN/A "all threads reached the max instruction count", 1081400SN/A p->max_insts_all_threads, *counter); 1092SN/A } 1102SN/A 111124SN/A // allocate per-thread load-based event queues 1121354SN/A comLoadEventQueue = new EventQueue *[number_of_threads]; 113124SN/A for (int i = 0; i < number_of_threads; ++i) 114124SN/A comLoadEventQueue[i] = new EventQueue("load-based event queue"); 115124SN/A 116124SN/A // 117124SN/A // set up instruction-count-based termination events, if any 118124SN/A // 1191400SN/A if (p->max_loads_any_thread != 0) 120124SN/A for (int i = 0; i < number_of_threads; ++i) 1211400SN/A new SimExitEvent(comLoadEventQueue[i], p->max_loads_any_thread, 122124SN/A "a thread reached the max load count"); 123124SN/A 1241400SN/A if (p->max_loads_all_threads != 0) { 125124SN/A // allocate & initialize shared downcounter: each event will 126124SN/A // decrement this when triggered; simulation will terminate 127124SN/A // when counter reaches 0 128124SN/A int *counter = new int; 129124SN/A *counter = number_of_threads; 130124SN/A for (int i = 0; i < number_of_threads; ++i) 131124SN/A new CountedExitEvent(comLoadEventQueue[i], 132124SN/A "all threads reached the max load count", 1331400SN/A p->max_loads_all_threads, *counter); 134124SN/A } 135124SN/A 1361858SN/A#if FULL_SYSTEM 1372SN/A memset(interrupts, 0, sizeof(interrupts)); 1382SN/A intstatus = 0; 1392SN/A#endif 1401191SN/A 1411191SN/A functionTracingEnabled = false; 1421400SN/A if (p->functionTrace) { 1431388SN/A functionTraceStream = simout.find(csprintf("ftrace.%s", name())); 1441191SN/A currentFunctionStart = currentFunctionEnd = 0; 1451400SN/A functionEntryTick = p->functionTraceStart; 1461191SN/A 1471400SN/A if (p->functionTraceStart == 0) { 1481191SN/A functionTracingEnabled = true; 1491191SN/A } else { 1501191SN/A Event *e = 1511191SN/A new EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace>(this, 1521191SN/A true); 1531400SN/A e->schedule(p->functionTraceStart); 1541191SN/A } 1551191SN/A } 1561917SN/A#if FULL_SYSTEM 1571917SN/A profileEvent = NULL; 1581917SN/A if (params->profile) 1591917SN/A profileEvent = new ProfileEvent(this, params->profile); 1602190SN/A 1612190SN/A kernelStats = new Kernel::Statistics(system); 1621917SN/A#endif 1632190SN/A 1642SN/A} 1652SN/A 1661917SN/ABaseCPU::Params::Params() 1671917SN/A{ 1681917SN/A#if FULL_SYSTEM 1691917SN/A profile = false; 1701917SN/A#endif 1711917SN/A} 1721191SN/A 1731191SN/Avoid 1741191SN/ABaseCPU::enableFunctionTrace() 1751191SN/A{ 1761191SN/A functionTracingEnabled = true; 1771191SN/A} 1781191SN/A 1791191SN/ABaseCPU::~BaseCPU() 1801191SN/A{ 1812190SN/A#if FULL_SYSTEM 1822190SN/A if (kernelStats) 1832190SN/A delete kernelStats; 1842190SN/A#endif 1851191SN/A} 1861191SN/A 1871129SN/Avoid 1881129SN/ABaseCPU::init() 1891129SN/A{ 1901400SN/A if (!params->deferRegistration) 1911129SN/A registerExecContexts(); 1921129SN/A} 193180SN/A 1942SN/Avoid 1951917SN/ABaseCPU::startup() 1961917SN/A{ 1971917SN/A#if FULL_SYSTEM 1981917SN/A if (!params->deferRegistration && profileEvent) 1991917SN/A profileEvent->schedule(curTick); 2001917SN/A#endif 2011917SN/A} 2021917SN/A 2031917SN/A 2041917SN/Avoid 2052SN/ABaseCPU::regStats() 2062SN/A{ 207729SN/A using namespace Stats; 208707SN/A 209707SN/A numCycles 210707SN/A .name(name() + ".numCycles") 211707SN/A .desc("number of cpu cycles simulated") 212707SN/A ; 213707SN/A 214180SN/A int size = execContexts.size(); 2152SN/A if (size > 1) { 2162SN/A for (int i = 0; i < size; ++i) { 2172SN/A stringstream namestr; 2182SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 219180SN/A execContexts[i]->regStats(namestr.str()); 2202SN/A } 2212SN/A } else if (size == 1) 222180SN/A execContexts[0]->regStats(name()); 2232190SN/A 2242190SN/A#if FULL_SYSTEM 2252190SN/A if (kernelStats) 2262190SN/A kernelStats->regStats(name() + ".kern"); 2272190SN/A#endif 2282SN/A} 2292SN/A 230180SN/A 231180SN/Avoid 232180SN/ABaseCPU::registerExecContexts() 233180SN/A{ 234180SN/A for (int i = 0; i < execContexts.size(); ++i) { 235180SN/A ExecContext *xc = execContexts[i]; 2362378SN/A 2371858SN/A#if FULL_SYSTEM 2381806SN/A int id = params->cpu_id; 2391806SN/A if (id != -1) 2401806SN/A id += i; 241180SN/A 2422190SN/A xc->setCpuId(system->registerExecContext(xc, id)); 243180SN/A#else 2442190SN/A xc->setCpuId(xc->getProcessPtr()->registerExecContext(xc)); 245180SN/A#endif 246180SN/A } 247180SN/A} 248180SN/A 249180SN/A 250180SN/Avoid 2511752SN/ABaseCPU::switchOut(Sampler *sampler) 252180SN/A{ 2531545SN/A panic("This CPU doesn't support sampling!"); 254180SN/A} 255180SN/A 256180SN/Avoid 257180SN/ABaseCPU::takeOverFrom(BaseCPU *oldCPU) 258180SN/A{ 259180SN/A assert(execContexts.size() == oldCPU->execContexts.size()); 260180SN/A 261180SN/A for (int i = 0; i < execContexts.size(); ++i) { 262180SN/A ExecContext *newXC = execContexts[i]; 263180SN/A ExecContext *oldXC = oldCPU->execContexts[i]; 264180SN/A 265180SN/A newXC->takeOverFrom(oldXC); 2662651Ssaidi@eecs.umich.edu 2672651Ssaidi@eecs.umich.edu CpuEvent::replaceExecContext(oldXC, newXC); 2682651Ssaidi@eecs.umich.edu 2692190SN/A assert(newXC->readCpuId() == oldXC->readCpuId()); 2701858SN/A#if FULL_SYSTEM 2712190SN/A system->replaceExecContext(newXC, newXC->readCpuId()); 272180SN/A#else 2732190SN/A assert(newXC->getProcessPtr() == oldXC->getProcessPtr()); 2742190SN/A newXC->getProcessPtr()->replaceExecContext(newXC, newXC->readCpuId()); 275180SN/A#endif 276180SN/A } 277605SN/A 2781858SN/A#if FULL_SYSTEM 2792107SN/A for (int i = 0; i < TheISA::NumInterruptLevels; ++i) 280605SN/A interrupts[i] = oldCPU->interrupts[i]; 281605SN/A intstatus = oldCPU->intstatus; 2822254SN/A 2831917SN/A for (int i = 0; i < execContexts.size(); ++i) 2842254SN/A execContexts[i]->profileClear(); 2852254SN/A 2861917SN/A if (profileEvent) 2871917SN/A profileEvent->schedule(curTick); 288612SN/A#endif 289180SN/A} 290180SN/A 291180SN/A 2921858SN/A#if FULL_SYSTEM 2931917SN/ABaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, int _interval) 2941917SN/A : Event(&mainEventQueue), cpu(_cpu), interval(_interval) 2951917SN/A{ } 2961917SN/A 2971917SN/Avoid 2981917SN/ABaseCPU::ProfileEvent::process() 2991917SN/A{ 3002254SN/A for (int i = 0, size = cpu->execContexts.size(); i < size; ++i) { 3011917SN/A ExecContext *xc = cpu->execContexts[i]; 3022254SN/A xc->profileSample(); 3031917SN/A } 3042254SN/A 3051917SN/A schedule(curTick + interval); 3061917SN/A} 3071917SN/A 3082SN/Avoid 3092SN/ABaseCPU::post_interrupt(int int_num, int index) 3102SN/A{ 3112SN/A DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 3122SN/A 3132107SN/A if (int_num < 0 || int_num >= TheISA::NumInterruptLevels) 3142SN/A panic("int_num out of bounds\n"); 3152SN/A 316822SN/A if (index < 0 || index >= sizeof(uint64_t) * 8) 3172SN/A panic("int_num out of bounds\n"); 3182SN/A 3191133SN/A checkInterrupts = true; 3202SN/A interrupts[int_num] |= 1 << index; 3212SN/A intstatus |= (ULL(1) << int_num); 3222SN/A} 3232SN/A 3242SN/Avoid 3252SN/ABaseCPU::clear_interrupt(int int_num, int index) 3262SN/A{ 3272SN/A DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 3282SN/A 3292107SN/A if (int_num < 0 || int_num >= TheISA::NumInterruptLevels) 3302SN/A panic("int_num out of bounds\n"); 3312SN/A 332822SN/A if (index < 0 || index >= sizeof(uint64_t) * 8) 3332SN/A panic("int_num out of bounds\n"); 3342SN/A 3352SN/A interrupts[int_num] &= ~(1 << index); 3362SN/A if (interrupts[int_num] == 0) 3372SN/A intstatus &= ~(ULL(1) << int_num); 3382SN/A} 3392SN/A 3402SN/Avoid 3412SN/ABaseCPU::clear_interrupts() 3422SN/A{ 3432SN/A DPRINTF(Interrupt, "Interrupts all cleared\n"); 3442SN/A 3452SN/A memset(interrupts, 0, sizeof(interrupts)); 3462SN/A intstatus = 0; 3472SN/A} 3482SN/A 349921SN/A 350921SN/Avoid 351921SN/ABaseCPU::serialize(std::ostream &os) 352921SN/A{ 3532107SN/A SERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels); 354921SN/A SERIALIZE_SCALAR(intstatus); 3552190SN/A 3562190SN/A#if FULL_SYSTEM 3572190SN/A if (kernelStats) 3582190SN/A kernelStats->serialize(os); 3592190SN/A#endif 3602190SN/A 361921SN/A} 362921SN/A 363921SN/Avoid 364921SN/ABaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 365921SN/A{ 3662107SN/A UNSERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels); 367921SN/A UNSERIALIZE_SCALAR(intstatus); 3682190SN/A 3692190SN/A#if FULL_SYSTEM 3702190SN/A if (kernelStats) 3712190SN/A kernelStats->unserialize(cp, section); 3722190SN/A#endif 373921SN/A} 374921SN/A 3752SN/A#endif // FULL_SYSTEM 3762SN/A 3771191SN/Avoid 3781191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 3791191SN/A{ 3801191SN/A if (!debugSymbolTable) 3811191SN/A return; 3821191SN/A 3831191SN/A // if pc enters different function, print new function symbol and 3841191SN/A // update saved range. Otherwise do nothing. 3851191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 3861191SN/A string sym_str; 3871191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 3881191SN/A currentFunctionStart, 3891191SN/A currentFunctionEnd); 3901191SN/A 3911191SN/A if (!found) { 3921191SN/A // no symbol found: use addr as label 3931191SN/A sym_str = csprintf("0x%x", pc); 3941191SN/A currentFunctionStart = pc; 3951191SN/A currentFunctionEnd = pc + 1; 3961191SN/A } 3971191SN/A 3981191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 3991191SN/A curTick - functionEntryTick, curTick, sym_str); 4001191SN/A functionEntryTick = curTick; 4011191SN/A } 4021191SN/A} 4031191SN/A 4041191SN/A 4052SN/ADEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU) 406