base.cc revision 2254
12SN/A/* 22188SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A */ 282665SN/A 292665SN/A#include <iostream> 302665SN/A#include <string> 312665SN/A#include <sstream> 322SN/A 332SN/A#include "base/cprintf.hh" 342SN/A#include "base/loader/symtab.hh" 352SN/A#include "base/misc.hh" 362465SN/A#include "base/output.hh" 377680Sgblack@eecs.umich.edu#include "cpu/base.hh" 386658Snate@binkert.org#include "cpu/exec_context.hh" 391717SN/A#include "cpu/profile.hh" 402683Sktlim@umich.edu#include "cpu/sampler/sampler.hh" 412680SN/A#include "sim/param.hh" 425529Snate@binkert.org#include "sim/process.hh" 432SN/A#include "sim/sim_events.hh" 441858SN/A#include "sim/system.hh" 453565Sgblack@eecs.umich.edu 465529Snate@binkert.org#include "base/trace.hh" 471917SN/A 481070SN/A#if FULL_SYSTEM 491917SN/A#include "kern/kernel_stats.hh" 502188SN/A#endif 511917SN/A 522290SN/Ausing namespace std; 537723SAli.Saidi@ARM.com 541070SN/Avector<BaseCPU *> BaseCPU::cpuList; 551917SN/A 562SN/A// This variable reflects the max number of threads in any CPU. Be 575529Snate@binkert.org// careful to only use it once all the CPUs that you care about have 58360SN/A// been initialized 592519SN/Aint maxThreadsPerCPU = 1; 602SN/A 612SN/A#if FULL_SYSTEM 622SN/ABaseCPU::BaseCPU(Params *p) 632SN/A : SimObject(p->name), clock(p->clock), checkInterrupts(true), 642SN/A params(p), number_of_threads(p->numberOfThreads), system(p->system) 651858SN/A#else 662683Sktlim@umich.eduBaseCPU::BaseCPU(Params *p) 676022Sgblack@eecs.umich.edu : SimObject(p->name), clock(p->clock), params(p), 682683Sktlim@umich.edu number_of_threads(p->numberOfThreads) 696324Sgblack@eecs.umich.edu#endif 706324Sgblack@eecs.umich.edu{ 712521SN/A DPRINTF(FullCPU, "BaseCPU: Creating object, mem address %#x.\n", this); 722SN/A 732683Sktlim@umich.edu // add self to global list of CPUs 742190SN/A cpuList.push_back(this); 752680SN/A 762290SN/A DPRINTF(FullCPU, "BaseCPU: CPU added to cpuList, mem address %#x.\n", 776316Sgblack@eecs.umich.edu this); 781917SN/A 795529Snate@binkert.org if (number_of_threads > maxThreadsPerCPU) 801982SN/A maxThreadsPerCPU = number_of_threads; 811917SN/A 822683Sktlim@umich.edu // allocate per-thread instruction-based event queues 832683Sktlim@umich.edu comInstEventQueue = new EventQueue *[number_of_threads]; 841917SN/A for (int i = 0; i < number_of_threads; ++i) 851917SN/A comInstEventQueue[i] = new EventQueue("instruction-based event queue"); 861917SN/A 871917SN/A // 881917SN/A // set up instruction-count-based termination events, if any 891917SN/A // 901917SN/A if (p->max_insts_any_thread != 0) 911917SN/A for (int i = 0; i < number_of_threads; ++i) 922521SN/A new SimExitEvent(comInstEventQueue[i], p->max_insts_any_thread, 935482Snate@binkert.org "a thread reached the max instruction count"); 943548Sgblack@eecs.umich.edu 952SN/A if (p->max_insts_all_threads != 0) { 962SN/A // allocate & initialize shared downcounter: each event will 974997Sgblack@eecs.umich.edu // decrement this when triggered; simulation will terminate 986331Sgblack@eecs.umich.edu // when counter reaches 0 996331Sgblack@eecs.umich.edu int *counter = new int; 1004997Sgblack@eecs.umich.edu *counter = number_of_threads; 1012SN/A for (int i = 0; i < number_of_threads; ++i) 1026316Sgblack@eecs.umich.edu new CountedExitEvent(comInstEventQueue[i], 1032683Sktlim@umich.edu "all threads reached the max instruction count", 1042SN/A p->max_insts_all_threads, *counter); 1052190SN/A } 1062862Sktlim@umich.edu 1072862Sktlim@umich.edu // allocate per-thread load-based event queues 1082864Sktlim@umich.edu comLoadEventQueue = new EventQueue *[number_of_threads]; 1092862Sktlim@umich.edu for (int i = 0; i < number_of_threads; ++i) 1105712Shsul@eecs.umich.edu comLoadEventQueue[i] = new EventQueue("load-based event queue"); 1112862Sktlim@umich.edu 1126331Sgblack@eecs.umich.edu // 1132862Sktlim@umich.edu // set up instruction-count-based termination events, if any 1142190SN/A // 1152683Sktlim@umich.edu if (p->max_loads_any_thread != 0) 1162190SN/A for (int i = 0; i < number_of_threads; ++i) 1172190SN/A new SimExitEvent(comLoadEventQueue[i], p->max_loads_any_thread, 1182683Sktlim@umich.edu "a thread reached the max load count"); 1191070SN/A 1203486Sktlim@umich.edu if (p->max_loads_all_threads != 0) { 1213486Sktlim@umich.edu // allocate & initialize shared downcounter: each event will 1223486Sktlim@umich.edu // decrement this when triggered; simulation will terminate 1233486Sktlim@umich.edu // when counter reaches 0 1242680SN/A int *counter = new int; 1251070SN/A *counter = number_of_threads; 1261070SN/A for (int i = 0; i < number_of_threads; ++i) 1271917SN/A new CountedExitEvent(comLoadEventQueue[i], 1282683Sktlim@umich.edu "all threads reached the max load count", 129180SN/A p->max_loads_all_threads, *counter); 130180SN/A } 1311858SN/A 1322235SN/A#if FULL_SYSTEM 133180SN/A memset(interrupts, 0, sizeof(interrupts)); 1342235SN/A intstatus = 0; 135180SN/A#endif 136180SN/A 1372862Sktlim@umich.edu functionTracingEnabled = false; 1382862Sktlim@umich.edu if (p->functionTrace) { 1392313SN/A functionTraceStream = simout.find(csprintf("ftrace.%s", name())); 1402313SN/A currentFunctionStart = currentFunctionEnd = 0; 1412680SN/A functionEntryTick = p->functionTraceStart; 1422313SN/A 1432680SN/A if (p->functionTraceStart == 0) { 1442313SN/A functionTracingEnabled = true; 1452313SN/A } else { 1462680SN/A Event *e = 1472313SN/A new EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace>(this, 1482361SN/A true); 1493548Sgblack@eecs.umich.edu e->schedule(p->functionTraceStart); 1502361SN/A } 1512361SN/A } 1522361SN/A#if FULL_SYSTEM 1532235SN/A profileEvent = NULL; 154180SN/A if (params->profile) 155180SN/A profileEvent = new ProfileEvent(this, params->profile); 156180SN/A 1576029Ssteve.reinhardt@amd.com kernelStats = new Kernel::Statistics(system); 158180SN/A#endif 159180SN/A 1602SN/A} 1612864Sktlim@umich.edu 1622864Sktlim@umich.eduBaseCPU::Params::Params() 1632864Sktlim@umich.edu{ 1642864Sktlim@umich.edu#if FULL_SYSTEM 1652864Sktlim@umich.edu profile = false; 1662864Sktlim@umich.edu#endif 1672864Sktlim@umich.edu} 1682864Sktlim@umich.edu 1692864Sktlim@umich.eduvoid 1703548Sgblack@eecs.umich.eduBaseCPU::enableFunctionTrace() 1712864Sktlim@umich.edu{ 1722864Sktlim@umich.edu functionTracingEnabled = true; 1732864Sktlim@umich.edu} 1742864Sktlim@umich.edu 1752864Sktlim@umich.eduBaseCPU::~BaseCPU() 1762864Sktlim@umich.edu{ 1772864Sktlim@umich.edu#if FULL_SYSTEM 1782862Sktlim@umich.edu if (kernelStats) 1792862Sktlim@umich.edu delete kernelStats; 1802862Sktlim@umich.edu#endif 1812862Sktlim@umich.edu} 1822862Sktlim@umich.edu 1832862Sktlim@umich.eduvoid 1842862Sktlim@umich.eduBaseCPU::init() 1852862Sktlim@umich.edu{ 1865714Shsul@eecs.umich.edu if (!params->deferRegistration) 1875715Shsul@eecs.umich.edu registerExecContexts(); 1885714Shsul@eecs.umich.edu} 1892862Sktlim@umich.edu 1902862Sktlim@umich.eduvoid 1912862Sktlim@umich.eduBaseCPU::startup() 1922683Sktlim@umich.edu{ 193217SN/A#if FULL_SYSTEM 1942862Sktlim@umich.edu if (!params->deferRegistration && profileEvent) 1956315Sgblack@eecs.umich.edu profileEvent->schedule(curTick); 1966316Sgblack@eecs.umich.edu#endif 1977720Sgblack@eecs.umich.edu} 198223SN/A 1996677SBrad.Beckmann@amd.com 2006677SBrad.Beckmann@amd.comvoid 2016677SBrad.Beckmann@amd.comBaseCPU::regStats() 2026677SBrad.Beckmann@amd.com{ 2036678Sgblack@eecs.umich.edu using namespace Stats; 204217SN/A 205217SN/A numCycles 206217SN/A .name(name() + ".numCycles") 207217SN/A .desc("number of cpu cycles simulated") 2082683Sktlim@umich.edu ; 209217SN/A 2102862Sktlim@umich.edu int size = execContexts.size(); 2116315Sgblack@eecs.umich.edu if (size > 1) { 2126316Sgblack@eecs.umich.edu for (int i = 0; i < size; ++i) { 2137720Sgblack@eecs.umich.edu stringstream namestr; 214223SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 2156677SBrad.Beckmann@amd.com execContexts[i]->regStats(namestr.str()); 2166677SBrad.Beckmann@amd.com } 2176677SBrad.Beckmann@amd.com } else if (size == 1) 2186677SBrad.Beckmann@amd.com execContexts[0]->regStats(name()); 2196678Sgblack@eecs.umich.edu 220217SN/A#if FULL_SYSTEM 221217SN/A if (kernelStats) 2222683Sktlim@umich.edu kernelStats->regStats(name() + ".kern"); 2232683Sktlim@umich.edu#endif 2242683Sktlim@umich.edu} 2252683Sktlim@umich.edu 2262683Sktlim@umich.edu 2272683Sktlim@umich.eduvoid 2282683Sktlim@umich.eduBaseCPU::registerExecContexts() 2292683Sktlim@umich.edu{ 230217SN/A for (int i = 0; i < execContexts.size(); ++i) { 231217SN/A ExecContext *xc = execContexts[i]; 2322683Sktlim@umich.edu#if FULL_SYSTEM 2332SN/A int id = params->cpu_id; 2342680SN/A if (id != -1) 2352SN/A id += i; 2362SN/A 2377823Ssteve.reinhardt@amd.com xc->setCpuId(system->registerExecContext(xc, id)); 2382188SN/A#else 2394400Srdreslin@umich.edu xc->setCpuId(xc->getProcessPtr()->registerExecContext(xc)); 2405715Shsul@eecs.umich.edu#endif 2415543Ssaidi@eecs.umich.edu } 2424400Srdreslin@umich.edu} 2432290SN/A 2442680SN/A 2452290SN/Avoid 2462290SN/ABaseCPU::switchOut(Sampler *sampler) 2475715Shsul@eecs.umich.edu{ 248393SN/A panic("This CPU doesn't support sampling!"); 249393SN/A} 250393SN/A 2512683Sktlim@umich.eduvoid 252393SN/ABaseCPU::takeOverFrom(BaseCPU *oldCPU) 2532680SN/A{ 254393SN/A assert(execContexts.size() == oldCPU->execContexts.size()); 255393SN/A 2567823Ssteve.reinhardt@amd.com for (int i = 0; i < execContexts.size(); ++i) { 2577823Ssteve.reinhardt@amd.com ExecContext *newXC = execContexts[i]; 2582188SN/A ExecContext *oldXC = oldCPU->execContexts[i]; 2591858SN/A 2602SN/A newXC->takeOverFrom(oldXC); 2615704Snate@binkert.org assert(newXC->readCpuId() == oldXC->readCpuId()); 2622680SN/A#if FULL_SYSTEM 2632SN/A system->replaceExecContext(newXC, newXC->readCpuId()); 2642SN/A#else 2652SN/A assert(newXC->getProcessPtr() == oldXC->getProcessPtr()); 2662188SN/A newXC->getProcessPtr()->replaceExecContext(newXC, newXC->readCpuId()); 2672680SN/A#endif 2685715Shsul@eecs.umich.edu } 2692SN/A 2702SN/A#if FULL_SYSTEM 271393SN/A for (int i = 0; i < TheISA::NumInterruptLevels; ++i) 272393SN/A interrupts[i] = oldCPU->interrupts[i]; 2732683Sktlim@umich.edu intstatus = oldCPU->intstatus; 274393SN/A 2752680SN/A for (int i = 0; i < execContexts.size(); ++i) 276393SN/A execContexts[i]->profileClear(); 277393SN/A 2782680SN/A if (profileEvent) 2795715Shsul@eecs.umich.edu profileEvent->schedule(curTick); 280393SN/A#endif 281393SN/A} 282393SN/A 283393SN/A 2842683Sktlim@umich.edu#if FULL_SYSTEM 2852SN/ABaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, int _interval) 2862330SN/A : Event(&mainEventQueue), cpu(_cpu), interval(_interval) 2872341SN/A{ } 2882341SN/A 2892330SN/Avoid 2902SN/ABaseCPU::ProfileEvent::process() 291716SN/A{ 292716SN/A for (int i = 0, size = cpu->execContexts.size(); i < size; ++i) { 2932683Sktlim@umich.edu ExecContext *xc = cpu->execContexts[i]; 2942190SN/A xc->profileSample(); 2952680SN/A } 2962190SN/A 2972190SN/A schedule(curTick + interval); 298} 299 300void 301BaseCPU::post_interrupt(int int_num, int index) 302{ 303 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 304 305 if (int_num < 0 || int_num >= TheISA::NumInterruptLevels) 306 panic("int_num out of bounds\n"); 307 308 if (index < 0 || index >= sizeof(uint64_t) * 8) 309 panic("int_num out of bounds\n"); 310 311 checkInterrupts = true; 312 interrupts[int_num] |= 1 << index; 313 intstatus |= (ULL(1) << int_num); 314} 315 316void 317BaseCPU::clear_interrupt(int int_num, int index) 318{ 319 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 320 321 if (int_num < 0 || int_num >= TheISA::NumInterruptLevels) 322 panic("int_num out of bounds\n"); 323 324 if (index < 0 || index >= sizeof(uint64_t) * 8) 325 panic("int_num out of bounds\n"); 326 327 interrupts[int_num] &= ~(1 << index); 328 if (interrupts[int_num] == 0) 329 intstatus &= ~(ULL(1) << int_num); 330} 331 332void 333BaseCPU::clear_interrupts() 334{ 335 DPRINTF(Interrupt, "Interrupts all cleared\n"); 336 337 memset(interrupts, 0, sizeof(interrupts)); 338 intstatus = 0; 339} 340 341 342void 343BaseCPU::serialize(std::ostream &os) 344{ 345 SERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels); 346 SERIALIZE_SCALAR(intstatus); 347 348#if FULL_SYSTEM 349 if (kernelStats) 350 kernelStats->serialize(os); 351#endif 352 353} 354 355void 356BaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 357{ 358 UNSERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels); 359 UNSERIALIZE_SCALAR(intstatus); 360 361#if FULL_SYSTEM 362 if (kernelStats) 363 kernelStats->unserialize(cp, section); 364#endif 365} 366 367#endif // FULL_SYSTEM 368 369void 370BaseCPU::traceFunctionsInternal(Addr pc) 371{ 372 if (!debugSymbolTable) 373 return; 374 375 // if pc enters different function, print new function symbol and 376 // update saved range. Otherwise do nothing. 377 if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 378 string sym_str; 379 bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 380 currentFunctionStart, 381 currentFunctionEnd); 382 383 if (!found) { 384 // no symbol found: use addr as label 385 sym_str = csprintf("0x%x", pc); 386 currentFunctionStart = pc; 387 currentFunctionEnd = pc + 1; 388 } 389 390 ccprintf(*functionTraceStream, " (%d)\n%d: %s", 391 curTick - functionEntryTick, curTick, sym_str); 392 functionEntryTick = curTick; 393 } 394} 395 396 397DEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU) 398