base.cc revision 1752
1/* 2 * Copyright (c) 2002-2004 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <iostream> 30#include <string> 31#include <sstream> 32 33#include "base/cprintf.hh" 34#include "base/loader/symtab.hh" 35#include "base/misc.hh" 36#include "base/output.hh" 37#include "cpu/base.hh" 38#include "cpu/exec_context.hh" 39#include "cpu/sampler/sampler.hh" 40#include "sim/param.hh" 41#include "sim/sim_events.hh" 42 43#include "base/trace.hh" 44 45using namespace std; 46 47vector<BaseCPU *> BaseCPU::cpuList; 48 49// This variable reflects the max number of threads in any CPU. Be 50// careful to only use it once all the CPUs that you care about have 51// been initialized 52int maxThreadsPerCPU = 1; 53 54#ifdef FULL_SYSTEM 55BaseCPU::BaseCPU(Params *p) 56 : SimObject(p->name), clock(p->clock), checkInterrupts(true), 57 params(p), number_of_threads(p->numberOfThreads), system(p->system) 58#else 59BaseCPU::BaseCPU(Params *p) 60 : SimObject(p->name), clock(p->clock), params(p), 61 number_of_threads(p->numberOfThreads) 62#endif 63{ 64 DPRINTF(FullCPU, "BaseCPU: Creating object, mem address %#x.\n", this); 65 66 // add self to global list of CPUs 67 cpuList.push_back(this); 68 69 DPRINTF(FullCPU, "BaseCPU: CPU added to cpuList, mem address %#x.\n", 70 this); 71 72 if (number_of_threads > maxThreadsPerCPU) 73 maxThreadsPerCPU = number_of_threads; 74 75 // allocate per-thread instruction-based event queues 76 comInstEventQueue = new EventQueue *[number_of_threads]; 77 for (int i = 0; i < number_of_threads; ++i) 78 comInstEventQueue[i] = new EventQueue("instruction-based event queue"); 79 80 // 81 // set up instruction-count-based termination events, if any 82 // 83 if (p->max_insts_any_thread != 0) 84 for (int i = 0; i < number_of_threads; ++i) 85 new SimExitEvent(comInstEventQueue[i], p->max_insts_any_thread, 86 "a thread reached the max instruction count"); 87 88 if (p->max_insts_all_threads != 0) { 89 // allocate & initialize shared downcounter: each event will 90 // decrement this when triggered; simulation will terminate 91 // when counter reaches 0 92 int *counter = new int; 93 *counter = number_of_threads; 94 for (int i = 0; i < number_of_threads; ++i) 95 new CountedExitEvent(comInstEventQueue[i], 96 "all threads reached the max instruction count", 97 p->max_insts_all_threads, *counter); 98 } 99 100 // allocate per-thread load-based event queues 101 comLoadEventQueue = new EventQueue *[number_of_threads]; 102 for (int i = 0; i < number_of_threads; ++i) 103 comLoadEventQueue[i] = new EventQueue("load-based event queue"); 104 105 // 106 // set up instruction-count-based termination events, if any 107 // 108 if (p->max_loads_any_thread != 0) 109 for (int i = 0; i < number_of_threads; ++i) 110 new SimExitEvent(comLoadEventQueue[i], p->max_loads_any_thread, 111 "a thread reached the max load count"); 112 113 if (p->max_loads_all_threads != 0) { 114 // allocate & initialize shared downcounter: each event will 115 // decrement this when triggered; simulation will terminate 116 // when counter reaches 0 117 int *counter = new int; 118 *counter = number_of_threads; 119 for (int i = 0; i < number_of_threads; ++i) 120 new CountedExitEvent(comLoadEventQueue[i], 121 "all threads reached the max load count", 122 p->max_loads_all_threads, *counter); 123 } 124 125#ifdef FULL_SYSTEM 126 memset(interrupts, 0, sizeof(interrupts)); 127 intstatus = 0; 128#endif 129 130 functionTracingEnabled = false; 131 if (p->functionTrace) { 132 functionTraceStream = simout.find(csprintf("ftrace.%s", name())); 133 currentFunctionStart = currentFunctionEnd = 0; 134 functionEntryTick = p->functionTraceStart; 135 136 if (p->functionTraceStart == 0) { 137 functionTracingEnabled = true; 138 } else { 139 Event *e = 140 new EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace>(this, 141 true); 142 e->schedule(p->functionTraceStart); 143 } 144 } 145} 146 147 148void 149BaseCPU::enableFunctionTrace() 150{ 151 functionTracingEnabled = true; 152} 153 154BaseCPU::~BaseCPU() 155{ 156} 157 158void 159BaseCPU::init() 160{ 161 if (!params->deferRegistration) 162 registerExecContexts(); 163} 164 165void 166BaseCPU::regStats() 167{ 168 using namespace Stats; 169 170 numCycles 171 .name(name() + ".numCycles") 172 .desc("number of cpu cycles simulated") 173 ; 174 175 int size = execContexts.size(); 176 if (size > 1) { 177 for (int i = 0; i < size; ++i) { 178 stringstream namestr; 179 ccprintf(namestr, "%s.ctx%d", name(), i); 180 execContexts[i]->regStats(namestr.str()); 181 } 182 } else if (size == 1) 183 execContexts[0]->regStats(name()); 184} 185 186 187void 188BaseCPU::registerExecContexts() 189{ 190 for (int i = 0; i < execContexts.size(); ++i) { 191 ExecContext *xc = execContexts[i]; 192 int cpu_id; 193 194#ifdef FULL_SYSTEM 195 cpu_id = system->registerExecContext(xc); 196#else 197 cpu_id = xc->process->registerExecContext(xc); 198#endif 199 200 xc->cpu_id = cpu_id; 201 } 202} 203 204 205void 206BaseCPU::switchOut(Sampler *sampler) 207{ 208 panic("This CPU doesn't support sampling!"); 209} 210 211void 212BaseCPU::takeOverFrom(BaseCPU *oldCPU) 213{ 214 assert(execContexts.size() == oldCPU->execContexts.size()); 215 216 for (int i = 0; i < execContexts.size(); ++i) { 217 ExecContext *newXC = execContexts[i]; 218 ExecContext *oldXC = oldCPU->execContexts[i]; 219 220 newXC->takeOverFrom(oldXC); 221 assert(newXC->cpu_id == oldXC->cpu_id); 222#ifdef FULL_SYSTEM 223 system->replaceExecContext(newXC, newXC->cpu_id); 224#else 225 assert(newXC->process == oldXC->process); 226 newXC->process->replaceExecContext(newXC, newXC->cpu_id); 227#endif 228 } 229 230#ifdef FULL_SYSTEM 231 for (int i = 0; i < NumInterruptLevels; ++i) 232 interrupts[i] = oldCPU->interrupts[i]; 233 intstatus = oldCPU->intstatus; 234#endif 235} 236 237 238#ifdef FULL_SYSTEM 239void 240BaseCPU::post_interrupt(int int_num, int index) 241{ 242 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 243 244 if (int_num < 0 || int_num >= NumInterruptLevels) 245 panic("int_num out of bounds\n"); 246 247 if (index < 0 || index >= sizeof(uint64_t) * 8) 248 panic("int_num out of bounds\n"); 249 250 checkInterrupts = true; 251 interrupts[int_num] |= 1 << index; 252 intstatus |= (ULL(1) << int_num); 253} 254 255void 256BaseCPU::clear_interrupt(int int_num, int index) 257{ 258 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 259 260 if (int_num < 0 || int_num >= NumInterruptLevels) 261 panic("int_num out of bounds\n"); 262 263 if (index < 0 || index >= sizeof(uint64_t) * 8) 264 panic("int_num out of bounds\n"); 265 266 interrupts[int_num] &= ~(1 << index); 267 if (interrupts[int_num] == 0) 268 intstatus &= ~(ULL(1) << int_num); 269} 270 271void 272BaseCPU::clear_interrupts() 273{ 274 DPRINTF(Interrupt, "Interrupts all cleared\n"); 275 276 memset(interrupts, 0, sizeof(interrupts)); 277 intstatus = 0; 278} 279 280 281void 282BaseCPU::serialize(std::ostream &os) 283{ 284 SERIALIZE_ARRAY(interrupts, NumInterruptLevels); 285 SERIALIZE_SCALAR(intstatus); 286} 287 288void 289BaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 290{ 291 UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels); 292 UNSERIALIZE_SCALAR(intstatus); 293} 294 295#endif // FULL_SYSTEM 296 297void 298BaseCPU::traceFunctionsInternal(Addr pc) 299{ 300 if (!debugSymbolTable) 301 return; 302 303 // if pc enters different function, print new function symbol and 304 // update saved range. Otherwise do nothing. 305 if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 306 string sym_str; 307 bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 308 currentFunctionStart, 309 currentFunctionEnd); 310 311 if (!found) { 312 // no symbol found: use addr as label 313 sym_str = csprintf("0x%x", pc); 314 currentFunctionStart = pc; 315 currentFunctionEnd = pc + 1; 316 } 317 318 ccprintf(*functionTraceStream, " (%d)\n%d: %s", 319 curTick - functionEntryTick, curTick, sym_str); 320 functionEntryTick = curTick; 321 } 322} 323 324 325DEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU) 326