base.cc revision 12277
12SN/A/* 212276Sanouk.vanlaer@arm.com * Copyright (c) 2011-2012,2016-2017 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 169983Sstever@gmail.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 179983Sstever@gmail.com * Copyright (c) 2013 Mark D. Hill and David A. Wood 182SN/A * All rights reserved. 192SN/A * 202SN/A * Redistribution and use in source and binary forms, with or without 212SN/A * modification, are permitted provided that the following conditions are 222SN/A * met: redistributions of source code must retain the above copyright 232SN/A * notice, this list of conditions and the following disclaimer; 242SN/A * redistributions in binary form must reproduce the above copyright 252SN/A * notice, this list of conditions and the following disclaimer in the 262SN/A * documentation and/or other materials provided with the distribution; 272SN/A * neither the name of the copyright holders nor the names of its 282SN/A * contributors may be used to endorse or promote products derived from 292SN/A * this software without specific prior written permission. 302SN/A * 312SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 322SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 332SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 342SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 352SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 362SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 372SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 382SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 392SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 402SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 412SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 422665Ssaidi@eecs.umich.edu * 432665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 442665Ssaidi@eecs.umich.edu * Nathan Binkert 457897Shestness@cs.utexas.edu * Rick Strong 462SN/A */ 472SN/A 4811793Sbrandon.potter@amd.com#include "cpu/base.hh" 4911793Sbrandon.potter@amd.com 501388SN/A#include <iostream> 518229Snate@binkert.org#include <sstream> 522SN/A#include <string> 532SN/A 547781SAli.Saidi@ARM.com#include "arch/tlb.hh" 5511793Sbrandon.potter@amd.com#include "base/cprintf.hh" 568229Snate@binkert.org#include "base/loader/symtab.hh" 571191SN/A#include "base/misc.hh" 581388SN/A#include "base/output.hh" 595529Snate@binkert.org#include "base/trace.hh" 6010529Smorr@cs.wisc.edu#include "cpu/checker/cpu.hh" 612651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 628229Snate@binkert.org#include "cpu/profile.hh" 632680Sktlim@umich.edu#include "cpu/thread_context.hh" 6410529Smorr@cs.wisc.edu#include "debug/Mwait.hh" 658232Snate@binkert.org#include "debug/SyscallVerbose.hh" 6610529Smorr@cs.wisc.edu#include "mem/page_table.hh" 675529Snate@binkert.org#include "params/BaseCPU.hh" 6811526Sdavid.guillen@arm.com#include "sim/clocked_object.hh" 698779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 702190SN/A#include "sim/process.hh" 7156SN/A#include "sim/sim_events.hh" 728229Snate@binkert.org#include "sim/sim_exit.hh" 732190SN/A#include "sim/system.hh" 742SN/A 752359SN/A// Hack 762359SN/A#include "sim/stat_control.hh" 772359SN/A 782SN/Ausing namespace std; 792SN/A 802SN/Avector<BaseCPU *> BaseCPU::cpuList; 812SN/A 822SN/A// This variable reflects the max number of threads in any CPU. Be 832SN/A// careful to only use it once all the CPUs that you care about have 842SN/A// been initialized 852SN/Aint maxThreadsPerCPU = 1; 862SN/A 875606Snate@binkert.orgCPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 886144Sksewell@umich.edu : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 896144Sksewell@umich.edu cpu(_cpu), _repeatEvent(true) 903126Sktlim@umich.edu{ 916144Sksewell@umich.edu if (_interval) 927823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 933126Sktlim@umich.edu} 943126Sktlim@umich.edu 952356SN/Avoid 962356SN/ACPUProgressEvent::process() 972356SN/A{ 988834Satgutier@umich.edu Counter temp = cpu->totalOps(); 9910786Smalek.musleh@gmail.com 10010786Smalek.musleh@gmail.com if (_repeatEvent) 10110786Smalek.musleh@gmail.com cpu->schedule(this, curTick() + _interval); 10210786Smalek.musleh@gmail.com 10311321Ssteve.reinhardt@amd.com if (cpu->switchedOut()) { 10410786Smalek.musleh@gmail.com return; 10510786Smalek.musleh@gmail.com } 10610786Smalek.musleh@gmail.com 1072356SN/A#ifndef NDEBUG 1089179Sandreas.hansson@arm.com double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod()); 1092367SN/A 1106144Sksewell@umich.edu DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 1116144Sksewell@umich.edu "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 1126144Sksewell@umich.edu ipc); 1132356SN/A ipc = 0.0; 1142367SN/A#else 1156144Sksewell@umich.edu cprintf("%lli: %s progress event, total committed:%i, progress insts " 1167823Ssteve.reinhardt@amd.com "committed: %lli\n", curTick(), cpu->name(), temp, 1176144Sksewell@umich.edu temp - lastNumInst); 1182367SN/A#endif 1192356SN/A lastNumInst = temp; 1202356SN/A} 1212356SN/A 1222356SN/Aconst char * 1235336Shines@cs.fsu.eduCPUProgressEvent::description() const 1242356SN/A{ 1254873Sstever@eecs.umich.edu return "CPU Progress"; 1262356SN/A} 1272356SN/A 1288876Sandreas.hansson@arm.comBaseCPU::BaseCPU(Params *p, bool is_checker) 12910190Sakash.bagdia@arm.com : MemObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id), 1308832SAli.Saidi@ARM.com _instMasterId(p->system->getMasterId(name() + ".inst")), 1318832SAli.Saidi@ARM.com _dataMasterId(p->system->getMasterId(name() + ".data")), 13211050Sandreas.hansson@arm.com _taskId(ContextSwitchTaskId::Unknown), _pid(invldPid), 1339814Sandreas.hansson@arm.com _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()), 1349220Shestness@cs.wisc.edu interrupts(p->interrupts), profileEvent(NULL), 13510529Smorr@cs.wisc.edu numThreads(p->numThreads), system(p->system), 13610537Sandreas.hansson@arm.com functionTraceStream(nullptr), currentFunctionStart(0), 13710537Sandreas.hansson@arm.com currentFunctionEnd(0), functionEntryTick(0), 13811877Sbrandon.potter@amd.com addressMonitor(p->numThreads), 13912276Sanouk.vanlaer@arm.com syscallRetryLatency(p->syscallRetryLatency), 14012276Sanouk.vanlaer@arm.com pwrGatingLatency(p->pwr_gating_latency), 14112277Sjose.marinho@arm.com powerGatingOnIdle(p->power_gating_on_idle), 14212276Sanouk.vanlaer@arm.com enterPwrGatingEvent([this]{ enterPwrGating(); }, name()) 1432SN/A{ 1445712Shsul@eecs.umich.edu // if Python did not provide a valid ID, do it here 1455712Shsul@eecs.umich.edu if (_cpuId == -1 ) { 1465712Shsul@eecs.umich.edu _cpuId = cpuList.size(); 1475712Shsul@eecs.umich.edu } 1485712Shsul@eecs.umich.edu 1492SN/A // add self to global list of CPUs 1502SN/A cpuList.push_back(this); 1512SN/A 15210190Sakash.bagdia@arm.com DPRINTF(SyscallVerbose, "Constructing CPU with id %d, socket id %d\n", 15310190Sakash.bagdia@arm.com _cpuId, _socketId); 1545712Shsul@eecs.umich.edu 1556221Snate@binkert.org if (numThreads > maxThreadsPerCPU) 1566221Snate@binkert.org maxThreadsPerCPU = numThreads; 1572SN/A 1582SN/A // allocate per-thread instruction-based event queues 1596221Snate@binkert.org comInstEventQueue = new EventQueue *[numThreads]; 1606221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1616221Snate@binkert.org comInstEventQueue[tid] = 1626221Snate@binkert.org new EventQueue("instruction-based event queue"); 1632SN/A 1642SN/A // 1652SN/A // set up instruction-count-based termination events, if any 1662SN/A // 1675606Snate@binkert.org if (p->max_insts_any_thread != 0) { 1685606Snate@binkert.org const char *cause = "a thread reached the max instruction count"; 1699749Sandreas@sandberg.pp.se for (ThreadID tid = 0; tid < numThreads; ++tid) 1709749Sandreas@sandberg.pp.se scheduleInstStop(tid, p->max_insts_any_thread, cause); 1715606Snate@binkert.org } 1722SN/A 1739647Sdam.sunwoo@arm.com // Set up instruction-count-based termination events for SimPoints 1749647Sdam.sunwoo@arm.com // Typically, there are more than one action points. 1759647Sdam.sunwoo@arm.com // Simulation.py is responsible to take the necessary actions upon 1769647Sdam.sunwoo@arm.com // exitting the simulation loop. 1779647Sdam.sunwoo@arm.com if (!p->simpoint_start_insts.empty()) { 1789647Sdam.sunwoo@arm.com const char *cause = "simpoint starting point found"; 1799749Sandreas@sandberg.pp.se for (size_t i = 0; i < p->simpoint_start_insts.size(); ++i) 1809749Sandreas@sandberg.pp.se scheduleInstStop(0, p->simpoint_start_insts[i], cause); 1819647Sdam.sunwoo@arm.com } 1829647Sdam.sunwoo@arm.com 1831400SN/A if (p->max_insts_all_threads != 0) { 1845606Snate@binkert.org const char *cause = "all threads reached the max instruction count"; 1855606Snate@binkert.org 1862SN/A // allocate & initialize shared downcounter: each event will 1872SN/A // decrement this when triggered; simulation will terminate 1882SN/A // when counter reaches 0 1892SN/A int *counter = new int; 1906221Snate@binkert.org *counter = numThreads; 1916221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1925606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1936670Shsul@eecs.umich.edu comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 1945606Snate@binkert.org } 1952SN/A } 1962SN/A 197124SN/A // allocate per-thread load-based event queues 1986221Snate@binkert.org comLoadEventQueue = new EventQueue *[numThreads]; 1996221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 2006221Snate@binkert.org comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 201124SN/A 202124SN/A // 203124SN/A // set up instruction-count-based termination events, if any 204124SN/A // 2055606Snate@binkert.org if (p->max_loads_any_thread != 0) { 2065606Snate@binkert.org const char *cause = "a thread reached the max load count"; 2079749Sandreas@sandberg.pp.se for (ThreadID tid = 0; tid < numThreads; ++tid) 2089749Sandreas@sandberg.pp.se scheduleLoadStop(tid, p->max_loads_any_thread, cause); 2095606Snate@binkert.org } 210124SN/A 2111400SN/A if (p->max_loads_all_threads != 0) { 2125606Snate@binkert.org const char *cause = "all threads reached the max load count"; 213124SN/A // allocate & initialize shared downcounter: each event will 214124SN/A // decrement this when triggered; simulation will terminate 215124SN/A // when counter reaches 0 216124SN/A int *counter = new int; 2176221Snate@binkert.org *counter = numThreads; 2186221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 2195606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 2206221Snate@binkert.org comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 2215606Snate@binkert.org } 222124SN/A } 223124SN/A 2241191SN/A functionTracingEnabled = false; 2255529Snate@binkert.org if (p->function_trace) { 2268634Schris.emmons@arm.com const string fname = csprintf("ftrace.%s", name()); 22711359Sandreas@sandberg.pp.se functionTraceStream = simout.findOrCreate(fname)->stream(); 2288634Schris.emmons@arm.com 2291191SN/A currentFunctionStart = currentFunctionEnd = 0; 2305529Snate@binkert.org functionEntryTick = p->function_trace_start; 2311191SN/A 2325529Snate@binkert.org if (p->function_trace_start == 0) { 2331191SN/A functionTracingEnabled = true; 2341191SN/A } else { 23512085Sspwilson2@wisc.edu Event *event = new EventFunctionWrapper( 23612085Sspwilson2@wisc.edu [this]{ enableFunctionTrace(); }, name(), true); 2375606Snate@binkert.org schedule(event, p->function_trace_start); 2381191SN/A } 2391191SN/A } 2408876Sandreas.hansson@arm.com 2418876Sandreas.hansson@arm.com // The interrupts should always be present unless this CPU is 2428876Sandreas.hansson@arm.com // switched in later or in case it is a checker CPU 2439433SAndreas.Sandberg@ARM.com if (!params()->switched_out && !is_checker) { 24411221Sandreas.sandberg@arm.com fatal_if(interrupts.size() != numThreads, 24511221Sandreas.sandberg@arm.com "CPU %s has %i interrupt controllers, but is expecting one " 24611221Sandreas.sandberg@arm.com "per thread (%i)\n", 24711221Sandreas.sandberg@arm.com name(), interrupts.size(), numThreads); 24811221Sandreas.sandberg@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) 24911221Sandreas.sandberg@arm.com interrupts[tid]->setCPU(this); 2508876Sandreas.hansson@arm.com } 2515810Sgblack@eecs.umich.edu 2528779Sgblack@eecs.umich.edu if (FullSystem) { 2538779Sgblack@eecs.umich.edu if (params()->profile) 25412127Sspwilson2@wisc.edu profileEvent = new EventFunctionWrapper( 25512127Sspwilson2@wisc.edu [this]{ processProfileEvent(); }, 25612127Sspwilson2@wisc.edu name()); 2578779Sgblack@eecs.umich.edu } 2585529Snate@binkert.org tracer = params()->tracer; 2599384SAndreas.Sandberg@arm.com 2609384SAndreas.Sandberg@arm.com if (params()->isa.size() != numThreads) { 2619384SAndreas.Sandberg@arm.com fatal("Number of ISAs (%i) assigned to the CPU does not equal number " 2629384SAndreas.Sandberg@arm.com "of threads (%i).\n", params()->isa.size(), numThreads); 2639384SAndreas.Sandberg@arm.com } 2641917SN/A} 2651191SN/A 2661191SN/Avoid 2671191SN/ABaseCPU::enableFunctionTrace() 2681191SN/A{ 2691191SN/A functionTracingEnabled = true; 2701191SN/A} 2711191SN/A 2721191SN/ABaseCPU::~BaseCPU() 2731191SN/A{ 2749086Sandreas.hansson@arm.com delete profileEvent; 2759086Sandreas.hansson@arm.com delete[] comLoadEventQueue; 2769086Sandreas.hansson@arm.com delete[] comInstEventQueue; 2771191SN/A} 2781191SN/A 2791129SN/Avoid 28011148Smitch.hayenga@arm.comBaseCPU::armMonitor(ThreadID tid, Addr address) 28110529Smorr@cs.wisc.edu{ 28211148Smitch.hayenga@arm.com assert(tid < numThreads); 28311148Smitch.hayenga@arm.com AddressMonitor &monitor = addressMonitor[tid]; 28411148Smitch.hayenga@arm.com 28511148Smitch.hayenga@arm.com monitor.armed = true; 28611148Smitch.hayenga@arm.com monitor.vAddr = address; 28711148Smitch.hayenga@arm.com monitor.pAddr = 0x0; 28811148Smitch.hayenga@arm.com DPRINTF(Mwait,"[tid:%d] Armed monitor (vAddr=0x%lx)\n", tid, address); 28910529Smorr@cs.wisc.edu} 29010529Smorr@cs.wisc.edu 29110529Smorr@cs.wisc.edubool 29211148Smitch.hayenga@arm.comBaseCPU::mwait(ThreadID tid, PacketPtr pkt) 29310529Smorr@cs.wisc.edu{ 29411148Smitch.hayenga@arm.com assert(tid < numThreads); 29511148Smitch.hayenga@arm.com AddressMonitor &monitor = addressMonitor[tid]; 29611148Smitch.hayenga@arm.com 29711325Ssteve.reinhardt@amd.com if (!monitor.gotWakeup) { 29810529Smorr@cs.wisc.edu int block_size = cacheLineSize(); 29910529Smorr@cs.wisc.edu uint64_t mask = ~((uint64_t)(block_size - 1)); 30010529Smorr@cs.wisc.edu 30110529Smorr@cs.wisc.edu assert(pkt->req->hasPaddr()); 30211148Smitch.hayenga@arm.com monitor.pAddr = pkt->getAddr() & mask; 30311148Smitch.hayenga@arm.com monitor.waiting = true; 30410529Smorr@cs.wisc.edu 30511148Smitch.hayenga@arm.com DPRINTF(Mwait,"[tid:%d] mwait called (vAddr=0x%lx, " 30611148Smitch.hayenga@arm.com "line's paddr=0x%lx)\n", tid, monitor.vAddr, monitor.pAddr); 30710529Smorr@cs.wisc.edu return true; 30810529Smorr@cs.wisc.edu } else { 30911148Smitch.hayenga@arm.com monitor.gotWakeup = false; 31010529Smorr@cs.wisc.edu return false; 31110529Smorr@cs.wisc.edu } 31210529Smorr@cs.wisc.edu} 31310529Smorr@cs.wisc.edu 31410529Smorr@cs.wisc.eduvoid 31511148Smitch.hayenga@arm.comBaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, TheISA::TLB *dtb) 31610529Smorr@cs.wisc.edu{ 31711148Smitch.hayenga@arm.com assert(tid < numThreads); 31811148Smitch.hayenga@arm.com AddressMonitor &monitor = addressMonitor[tid]; 31911148Smitch.hayenga@arm.com 32010529Smorr@cs.wisc.edu Request req; 32111148Smitch.hayenga@arm.com Addr addr = monitor.vAddr; 32210529Smorr@cs.wisc.edu int block_size = cacheLineSize(); 32310529Smorr@cs.wisc.edu uint64_t mask = ~((uint64_t)(block_size - 1)); 32410529Smorr@cs.wisc.edu int size = block_size; 32510529Smorr@cs.wisc.edu 32610529Smorr@cs.wisc.edu //The address of the next line if it crosses a cache line boundary. 32710529Smorr@cs.wisc.edu Addr secondAddr = roundDown(addr + size - 1, block_size); 32810529Smorr@cs.wisc.edu 32910529Smorr@cs.wisc.edu if (secondAddr > addr) 33010529Smorr@cs.wisc.edu size = secondAddr - addr; 33110529Smorr@cs.wisc.edu 33210529Smorr@cs.wisc.edu req.setVirt(0, addr, size, 0x0, dataMasterId(), tc->instAddr()); 33310529Smorr@cs.wisc.edu 33410529Smorr@cs.wisc.edu // translate to physical address 33510529Smorr@cs.wisc.edu Fault fault = dtb->translateAtomic(&req, tc, BaseTLB::Read); 33610529Smorr@cs.wisc.edu assert(fault == NoFault); 33710529Smorr@cs.wisc.edu 33811148Smitch.hayenga@arm.com monitor.pAddr = req.getPaddr() & mask; 33911148Smitch.hayenga@arm.com monitor.waiting = true; 34010529Smorr@cs.wisc.edu 34111148Smitch.hayenga@arm.com DPRINTF(Mwait,"[tid:%d] mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n", 34211148Smitch.hayenga@arm.com tid, monitor.vAddr, monitor.pAddr); 34310529Smorr@cs.wisc.edu} 34410529Smorr@cs.wisc.edu 34510529Smorr@cs.wisc.eduvoid 3461129SN/ABaseCPU::init() 3471129SN/A{ 3489523SAndreas.Sandberg@ARM.com if (!params()->switched_out) { 3492680Sktlim@umich.edu registerThreadContexts(); 3509523SAndreas.Sandberg@ARM.com 3519523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 3529523SAndreas.Sandberg@ARM.com } 3531129SN/A} 354180SN/A 3552SN/Avoid 3561917SN/ABaseCPU::startup() 3571917SN/A{ 3588779Sgblack@eecs.umich.edu if (FullSystem) { 3599433SAndreas.Sandberg@ARM.com if (!params()->switched_out && profileEvent) 3608779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 3618779Sgblack@eecs.umich.edu } 3622356SN/A 3635529Snate@binkert.org if (params()->progress_interval) { 3649179Sandreas.hansson@arm.com new CPUProgressEvent(this, params()->progress_interval); 3652356SN/A } 36611526Sdavid.guillen@arm.com 36712276Sanouk.vanlaer@arm.com if (_switchedOut) 36812276Sanouk.vanlaer@arm.com ClockedObject::pwrState(Enums::PwrState::OFF); 36912276Sanouk.vanlaer@arm.com 37011526Sdavid.guillen@arm.com // Assumption CPU start to operate instantaneously without any latency 37111526Sdavid.guillen@arm.com if (ClockedObject::pwrState() == Enums::PwrState::UNDEFINED) 37211526Sdavid.guillen@arm.com ClockedObject::pwrState(Enums::PwrState::ON); 37311526Sdavid.guillen@arm.com 3741917SN/A} 3751917SN/A 37610464SAndreas.Sandberg@ARM.comProbePoints::PMUUPtr 37710464SAndreas.Sandberg@ARM.comBaseCPU::pmuProbePoint(const char *name) 37810464SAndreas.Sandberg@ARM.com{ 37910464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ptr; 38010464SAndreas.Sandberg@ARM.com ptr.reset(new ProbePoints::PMU(getProbeManager(), name)); 38110464SAndreas.Sandberg@ARM.com 38210464SAndreas.Sandberg@ARM.com return ptr; 38310464SAndreas.Sandberg@ARM.com} 38410464SAndreas.Sandberg@ARM.com 38510464SAndreas.Sandberg@ARM.comvoid 38610464SAndreas.Sandberg@ARM.comBaseCPU::regProbePoints() 38710464SAndreas.Sandberg@ARM.com{ 38810464SAndreas.Sandberg@ARM.com ppCycles = pmuProbePoint("Cycles"); 38910464SAndreas.Sandberg@ARM.com 39010464SAndreas.Sandberg@ARM.com ppRetiredInsts = pmuProbePoint("RetiredInsts"); 39110464SAndreas.Sandberg@ARM.com ppRetiredLoads = pmuProbePoint("RetiredLoads"); 39210464SAndreas.Sandberg@ARM.com ppRetiredStores = pmuProbePoint("RetiredStores"); 39310464SAndreas.Sandberg@ARM.com ppRetiredBranches = pmuProbePoint("RetiredBranches"); 39410464SAndreas.Sandberg@ARM.com} 39510464SAndreas.Sandberg@ARM.com 39610464SAndreas.Sandberg@ARM.comvoid 39710464SAndreas.Sandberg@ARM.comBaseCPU::probeInstCommit(const StaticInstPtr &inst) 39810464SAndreas.Sandberg@ARM.com{ 39910464SAndreas.Sandberg@ARM.com if (!inst->isMicroop() || inst->isLastMicroop()) 40010464SAndreas.Sandberg@ARM.com ppRetiredInsts->notify(1); 40110464SAndreas.Sandberg@ARM.com 40210464SAndreas.Sandberg@ARM.com 40310464SAndreas.Sandberg@ARM.com if (inst->isLoad()) 40410464SAndreas.Sandberg@ARM.com ppRetiredLoads->notify(1); 40510464SAndreas.Sandberg@ARM.com 40610464SAndreas.Sandberg@ARM.com if (inst->isStore()) 40710643Snikos.nikoleris@gmail.com ppRetiredStores->notify(1); 40810464SAndreas.Sandberg@ARM.com 40910464SAndreas.Sandberg@ARM.com if (inst->isControl()) 41010464SAndreas.Sandberg@ARM.com ppRetiredBranches->notify(1); 41110464SAndreas.Sandberg@ARM.com} 4121917SN/A 4131917SN/Avoid 4142SN/ABaseCPU::regStats() 4152SN/A{ 41611522Sstephan.diestelhorst@arm.com MemObject::regStats(); 41711522Sstephan.diestelhorst@arm.com 418729SN/A using namespace Stats; 419707SN/A 420707SN/A numCycles 421707SN/A .name(name() + ".numCycles") 422707SN/A .desc("number of cpu cycles simulated") 423707SN/A ; 424707SN/A 4257914SBrad.Beckmann@amd.com numWorkItemsStarted 4267914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsStarted") 4277914SBrad.Beckmann@amd.com .desc("number of work items this cpu started") 4287914SBrad.Beckmann@amd.com ; 4297914SBrad.Beckmann@amd.com 4307914SBrad.Beckmann@amd.com numWorkItemsCompleted 4317914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsCompleted") 4327914SBrad.Beckmann@amd.com .desc("number of work items this cpu completed") 4337914SBrad.Beckmann@amd.com ; 4347914SBrad.Beckmann@amd.com 4352680Sktlim@umich.edu int size = threadContexts.size(); 4362SN/A if (size > 1) { 4372SN/A for (int i = 0; i < size; ++i) { 4382SN/A stringstream namestr; 4392SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 4402680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 4412SN/A } 4422SN/A } else if (size == 1) 4432680Sktlim@umich.edu threadContexts[0]->regStats(name()); 4442SN/A} 4452SN/A 4469294Sandreas.hansson@arm.comBaseMasterPort & 4479294Sandreas.hansson@arm.comBaseCPU::getMasterPort(const string &if_name, PortID idx) 4488850Sandreas.hansson@arm.com{ 4498850Sandreas.hansson@arm.com // Get the right port based on name. This applies to all the 4508850Sandreas.hansson@arm.com // subclasses of the base CPU and relies on their implementation 4518850Sandreas.hansson@arm.com // of getDataPort and getInstPort. In all cases there methods 4529608Sandreas.hansson@arm.com // return a MasterPort pointer. 4538850Sandreas.hansson@arm.com if (if_name == "dcache_port") 4548922Swilliam.wang@arm.com return getDataPort(); 4558850Sandreas.hansson@arm.com else if (if_name == "icache_port") 4568922Swilliam.wang@arm.com return getInstPort(); 4578850Sandreas.hansson@arm.com else 4588922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 4598850Sandreas.hansson@arm.com} 4608850Sandreas.hansson@arm.com 461180SN/Avoid 4622680Sktlim@umich.eduBaseCPU::registerThreadContexts() 463180SN/A{ 46411146Smitch.hayenga@arm.com assert(system->multiThread || numThreads == 1); 46511146Smitch.hayenga@arm.com 4666221Snate@binkert.org ThreadID size = threadContexts.size(); 4676221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 4686221Snate@binkert.org ThreadContext *tc = threadContexts[tid]; 4692378SN/A 47011146Smitch.hayenga@arm.com if (system->multiThread) { 47111146Smitch.hayenga@arm.com tc->setContextId(system->registerThreadContext(tc)); 47211146Smitch.hayenga@arm.com } else { 4735718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc, _cpuId)); 47411146Smitch.hayenga@arm.com } 4758779Sgblack@eecs.umich.edu 4768779Sgblack@eecs.umich.edu if (!FullSystem) 4778779Sgblack@eecs.umich.edu tc->getProcessPtr()->assignThreadContext(tc->contextId()); 478180SN/A } 479180SN/A} 480180SN/A 48112276Sanouk.vanlaer@arm.comvoid 48212276Sanouk.vanlaer@arm.comBaseCPU::deschedulePowerGatingEvent() 48312276Sanouk.vanlaer@arm.com{ 48412276Sanouk.vanlaer@arm.com if (enterPwrGatingEvent.scheduled()){ 48512276Sanouk.vanlaer@arm.com deschedule(enterPwrGatingEvent); 48612276Sanouk.vanlaer@arm.com } 48712276Sanouk.vanlaer@arm.com} 48812276Sanouk.vanlaer@arm.com 48912276Sanouk.vanlaer@arm.comvoid 49012276Sanouk.vanlaer@arm.comBaseCPU::schedulePowerGatingEvent() 49112276Sanouk.vanlaer@arm.com{ 49212276Sanouk.vanlaer@arm.com for (auto tc : threadContexts) { 49312276Sanouk.vanlaer@arm.com if (tc->status() == ThreadContext::Active) 49412276Sanouk.vanlaer@arm.com return; 49512276Sanouk.vanlaer@arm.com } 49612276Sanouk.vanlaer@arm.com 49712277Sjose.marinho@arm.com if (ClockedObject::pwrState() == Enums::PwrState::CLK_GATED && 49812277Sjose.marinho@arm.com powerGatingOnIdle) { 49912276Sanouk.vanlaer@arm.com assert(!enterPwrGatingEvent.scheduled()); 50012276Sanouk.vanlaer@arm.com // Schedule a power gating event when clock gated for the specified 50112276Sanouk.vanlaer@arm.com // amount of time 50212276Sanouk.vanlaer@arm.com schedule(enterPwrGatingEvent, clockEdge(pwrGatingLatency)); 50312276Sanouk.vanlaer@arm.com } 50412276Sanouk.vanlaer@arm.com} 505180SN/A 5064000Ssaidi@eecs.umich.eduint 5074000Ssaidi@eecs.umich.eduBaseCPU::findContext(ThreadContext *tc) 5084000Ssaidi@eecs.umich.edu{ 5096221Snate@binkert.org ThreadID size = threadContexts.size(); 5106221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 5116221Snate@binkert.org if (tc == threadContexts[tid]) 5126221Snate@binkert.org return tid; 5134000Ssaidi@eecs.umich.edu } 5144000Ssaidi@eecs.umich.edu return 0; 5154000Ssaidi@eecs.umich.edu} 5164000Ssaidi@eecs.umich.edu 517180SN/Avoid 51811526Sdavid.guillen@arm.comBaseCPU::activateContext(ThreadID thread_num) 51911526Sdavid.guillen@arm.com{ 52012276Sanouk.vanlaer@arm.com // Squash enter power gating event while cpu gets activated 52112276Sanouk.vanlaer@arm.com if (enterPwrGatingEvent.scheduled()) 52212276Sanouk.vanlaer@arm.com deschedule(enterPwrGatingEvent); 52312276Sanouk.vanlaer@arm.com 52411526Sdavid.guillen@arm.com // For any active thread running, update CPU power state to active (ON) 52511526Sdavid.guillen@arm.com ClockedObject::pwrState(Enums::PwrState::ON); 52611526Sdavid.guillen@arm.com} 52711526Sdavid.guillen@arm.com 52811526Sdavid.guillen@arm.comvoid 52911526Sdavid.guillen@arm.comBaseCPU::suspendContext(ThreadID thread_num) 53011526Sdavid.guillen@arm.com{ 53111526Sdavid.guillen@arm.com // Check if all threads are suspended 53211526Sdavid.guillen@arm.com for (auto t : threadContexts) { 53311526Sdavid.guillen@arm.com if (t->status() != ThreadContext::Suspended) { 53411526Sdavid.guillen@arm.com return; 53511526Sdavid.guillen@arm.com } 53611526Sdavid.guillen@arm.com } 53711526Sdavid.guillen@arm.com 53811526Sdavid.guillen@arm.com // All CPU threads suspended, enter lower power state for the CPU 53911526Sdavid.guillen@arm.com ClockedObject::pwrState(Enums::PwrState::CLK_GATED); 54012276Sanouk.vanlaer@arm.com 54112277Sjose.marinho@arm.com // If pwrGatingLatency is set to 0 then this mechanism is disabled 54212277Sjose.marinho@arm.com if (powerGatingOnIdle) { 54312277Sjose.marinho@arm.com // Schedule power gating event when clock gated for pwrGatingLatency 54412277Sjose.marinho@arm.com // cycles 54512277Sjose.marinho@arm.com schedule(enterPwrGatingEvent, clockEdge(pwrGatingLatency)); 54612277Sjose.marinho@arm.com } 54712276Sanouk.vanlaer@arm.com} 54812276Sanouk.vanlaer@arm.com 54912276Sanouk.vanlaer@arm.comvoid 55012276Sanouk.vanlaer@arm.comBaseCPU::enterPwrGating(void) 55112276Sanouk.vanlaer@arm.com{ 55212276Sanouk.vanlaer@arm.com ClockedObject::pwrState(Enums::PwrState::OFF); 55311526Sdavid.guillen@arm.com} 55411526Sdavid.guillen@arm.com 55511526Sdavid.guillen@arm.comvoid 5562798Sktlim@umich.eduBaseCPU::switchOut() 557180SN/A{ 5589430SAndreas.Sandberg@ARM.com assert(!_switchedOut); 5599430SAndreas.Sandberg@ARM.com _switchedOut = true; 5602359SN/A if (profileEvent && profileEvent->scheduled()) 5615606Snate@binkert.org deschedule(profileEvent); 5629446SAndreas.Sandberg@ARM.com 5639446SAndreas.Sandberg@ARM.com // Flush all TLBs in the CPU to avoid having stale translations if 5649446SAndreas.Sandberg@ARM.com // it gets switched in later. 5659446SAndreas.Sandberg@ARM.com flushTLBs(); 56612276Sanouk.vanlaer@arm.com 56712276Sanouk.vanlaer@arm.com // Go to the power gating state 56812276Sanouk.vanlaer@arm.com ClockedObject::pwrState(Enums::PwrState::OFF); 569180SN/A} 570180SN/A 571180SN/Avoid 5728737Skoansin.tan@gmail.comBaseCPU::takeOverFrom(BaseCPU *oldCPU) 573180SN/A{ 5742680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 5759152Satgutier@umich.edu assert(_cpuId == oldCPU->cpuId()); 5769430SAndreas.Sandberg@ARM.com assert(_switchedOut); 5779430SAndreas.Sandberg@ARM.com assert(oldCPU != this); 5789332Sdam.sunwoo@arm.com _pid = oldCPU->getPid(); 5799332Sdam.sunwoo@arm.com _taskId = oldCPU->taskId(); 58012276Sanouk.vanlaer@arm.com // Take over the power state of the switchedOut CPU 58112276Sanouk.vanlaer@arm.com ClockedObject::pwrState(oldCPU->pwrState()); 5829430SAndreas.Sandberg@ARM.com _switchedOut = false; 5835712Shsul@eecs.umich.edu 5846221Snate@binkert.org ThreadID size = threadContexts.size(); 5856221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 5862680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 5872680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 588180SN/A 5892680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 5902651Ssaidi@eecs.umich.edu 5912680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 5922651Ssaidi@eecs.umich.edu 5935714Shsul@eecs.umich.edu assert(newTC->contextId() == oldTC->contextId()); 5945715Shsul@eecs.umich.edu assert(newTC->threadId() == oldTC->threadId()); 5955714Shsul@eecs.umich.edu system->replaceThreadContext(newTC, newTC->contextId()); 5962359SN/A 5975875Ssteve.reinhardt@amd.com /* This code no longer works since the zero register (e.g., 5985875Ssteve.reinhardt@amd.com * r31 on Alpha) doesn't necessarily contain zero at this 5995875Ssteve.reinhardt@amd.com * point. 6005875Ssteve.reinhardt@amd.com if (DTRACE(Context)) 6015217Ssaidi@eecs.umich.edu ThreadContext::compare(oldTC, newTC); 6025875Ssteve.reinhardt@amd.com */ 6037781SAli.Saidi@ARM.com 6049294Sandreas.hansson@arm.com BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort(); 6059294Sandreas.hansson@arm.com BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort(); 6069294Sandreas.hansson@arm.com BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort(); 6079294Sandreas.hansson@arm.com BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort(); 6087781SAli.Saidi@ARM.com 6097781SAli.Saidi@ARM.com // Move over any table walker ports if they exist 6109178Sandreas.hansson@arm.com if (new_itb_port) { 6119178Sandreas.hansson@arm.com assert(!new_itb_port->isConnected()); 6127781SAli.Saidi@ARM.com assert(old_itb_port); 6139178Sandreas.hansson@arm.com assert(old_itb_port->isConnected()); 6149294Sandreas.hansson@arm.com BaseSlavePort &slavePort = old_itb_port->getSlavePort(); 6159178Sandreas.hansson@arm.com old_itb_port->unbind(); 6168922Swilliam.wang@arm.com new_itb_port->bind(slavePort); 6177781SAli.Saidi@ARM.com } 6189178Sandreas.hansson@arm.com if (new_dtb_port) { 6199178Sandreas.hansson@arm.com assert(!new_dtb_port->isConnected()); 6207781SAli.Saidi@ARM.com assert(old_dtb_port); 6219178Sandreas.hansson@arm.com assert(old_dtb_port->isConnected()); 6229294Sandreas.hansson@arm.com BaseSlavePort &slavePort = old_dtb_port->getSlavePort(); 6239178Sandreas.hansson@arm.com old_dtb_port->unbind(); 6248922Swilliam.wang@arm.com new_dtb_port->bind(slavePort); 6257781SAli.Saidi@ARM.com } 62610194SGeoffrey.Blake@arm.com newTC->getITBPtr()->takeOverFrom(oldTC->getITBPtr()); 62710194SGeoffrey.Blake@arm.com newTC->getDTBPtr()->takeOverFrom(oldTC->getDTBPtr()); 6288733Sgeoffrey.blake@arm.com 6298887Sgeoffrey.blake@arm.com // Checker whether or not we have to transfer CheckerCPU 6308887Sgeoffrey.blake@arm.com // objects over in the switch 6318887Sgeoffrey.blake@arm.com CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr(); 6328887Sgeoffrey.blake@arm.com CheckerCPU *newChecker = newTC->getCheckerCpuPtr(); 6338887Sgeoffrey.blake@arm.com if (oldChecker && newChecker) { 6349294Sandreas.hansson@arm.com BaseMasterPort *old_checker_itb_port = 6358922Swilliam.wang@arm.com oldChecker->getITBPtr()->getMasterPort(); 6369294Sandreas.hansson@arm.com BaseMasterPort *old_checker_dtb_port = 6378922Swilliam.wang@arm.com oldChecker->getDTBPtr()->getMasterPort(); 6389294Sandreas.hansson@arm.com BaseMasterPort *new_checker_itb_port = 6398922Swilliam.wang@arm.com newChecker->getITBPtr()->getMasterPort(); 6409294Sandreas.hansson@arm.com BaseMasterPort *new_checker_dtb_port = 6418922Swilliam.wang@arm.com newChecker->getDTBPtr()->getMasterPort(); 6428733Sgeoffrey.blake@arm.com 64310194SGeoffrey.Blake@arm.com newChecker->getITBPtr()->takeOverFrom(oldChecker->getITBPtr()); 64410194SGeoffrey.Blake@arm.com newChecker->getDTBPtr()->takeOverFrom(oldChecker->getDTBPtr()); 64510194SGeoffrey.Blake@arm.com 6468887Sgeoffrey.blake@arm.com // Move over any table walker ports if they exist for checker 6479178Sandreas.hansson@arm.com if (new_checker_itb_port) { 6489178Sandreas.hansson@arm.com assert(!new_checker_itb_port->isConnected()); 6498887Sgeoffrey.blake@arm.com assert(old_checker_itb_port); 6509178Sandreas.hansson@arm.com assert(old_checker_itb_port->isConnected()); 6519294Sandreas.hansson@arm.com BaseSlavePort &slavePort = 6529294Sandreas.hansson@arm.com old_checker_itb_port->getSlavePort(); 6539178Sandreas.hansson@arm.com old_checker_itb_port->unbind(); 6548922Swilliam.wang@arm.com new_checker_itb_port->bind(slavePort); 6558887Sgeoffrey.blake@arm.com } 6569178Sandreas.hansson@arm.com if (new_checker_dtb_port) { 6579178Sandreas.hansson@arm.com assert(!new_checker_dtb_port->isConnected()); 6588887Sgeoffrey.blake@arm.com assert(old_checker_dtb_port); 6599178Sandreas.hansson@arm.com assert(old_checker_dtb_port->isConnected()); 6609294Sandreas.hansson@arm.com BaseSlavePort &slavePort = 6619294Sandreas.hansson@arm.com old_checker_dtb_port->getSlavePort(); 6629178Sandreas.hansson@arm.com old_checker_dtb_port->unbind(); 6638922Swilliam.wang@arm.com new_checker_dtb_port->bind(slavePort); 6648887Sgeoffrey.blake@arm.com } 6658733Sgeoffrey.blake@arm.com } 666180SN/A } 667605SN/A 6683520Sgblack@eecs.umich.edu interrupts = oldCPU->interrupts; 66911150Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 67011150Smitch.hayenga@arm.com interrupts[tid]->setCPU(this); 67111150Smitch.hayenga@arm.com } 67211150Smitch.hayenga@arm.com oldCPU->interrupts.clear(); 6732254SN/A 6748779Sgblack@eecs.umich.edu if (FullSystem) { 6758779Sgblack@eecs.umich.edu for (ThreadID i = 0; i < size; ++i) 6768779Sgblack@eecs.umich.edu threadContexts[i]->profileClear(); 6772254SN/A 6788779Sgblack@eecs.umich.edu if (profileEvent) 6798779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 6808779Sgblack@eecs.umich.edu } 6814192Sktlim@umich.edu 6829178Sandreas.hansson@arm.com // All CPUs have an instruction and a data port, and the new CPU's 6839178Sandreas.hansson@arm.com // ports are dangling while the old CPU has its ports connected 6849178Sandreas.hansson@arm.com // already. Unbind the old CPU and then bind the ports of the one 6859178Sandreas.hansson@arm.com // we are switching to. 6869178Sandreas.hansson@arm.com assert(!getInstPort().isConnected()); 6879178Sandreas.hansson@arm.com assert(oldCPU->getInstPort().isConnected()); 6889294Sandreas.hansson@arm.com BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort(); 6899178Sandreas.hansson@arm.com oldCPU->getInstPort().unbind(); 6909178Sandreas.hansson@arm.com getInstPort().bind(inst_peer_port); 6914192Sktlim@umich.edu 6929178Sandreas.hansson@arm.com assert(!getDataPort().isConnected()); 6939178Sandreas.hansson@arm.com assert(oldCPU->getDataPort().isConnected()); 6949294Sandreas.hansson@arm.com BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort(); 6959178Sandreas.hansson@arm.com oldCPU->getDataPort().unbind(); 6969178Sandreas.hansson@arm.com getDataPort().bind(data_peer_port); 697180SN/A} 698180SN/A 6999446SAndreas.Sandberg@ARM.comvoid 7009446SAndreas.Sandberg@ARM.comBaseCPU::flushTLBs() 7019446SAndreas.Sandberg@ARM.com{ 7029446SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < threadContexts.size(); ++i) { 7039446SAndreas.Sandberg@ARM.com ThreadContext &tc(*threadContexts[i]); 7049446SAndreas.Sandberg@ARM.com CheckerCPU *checker(tc.getCheckerCpuPtr()); 7059446SAndreas.Sandberg@ARM.com 7069446SAndreas.Sandberg@ARM.com tc.getITBPtr()->flushAll(); 7079446SAndreas.Sandberg@ARM.com tc.getDTBPtr()->flushAll(); 7089446SAndreas.Sandberg@ARM.com if (checker) { 7099446SAndreas.Sandberg@ARM.com checker->getITBPtr()->flushAll(); 7109446SAndreas.Sandberg@ARM.com checker->getDTBPtr()->flushAll(); 7119446SAndreas.Sandberg@ARM.com } 7129446SAndreas.Sandberg@ARM.com } 7139446SAndreas.Sandberg@ARM.com} 7149446SAndreas.Sandberg@ARM.com 71512127Sspwilson2@wisc.eduvoid 71612127Sspwilson2@wisc.eduBaseCPU::processProfileEvent() 71712127Sspwilson2@wisc.edu{ 71812127Sspwilson2@wisc.edu ThreadID size = threadContexts.size(); 719180SN/A 72012127Sspwilson2@wisc.edu for (ThreadID i = 0; i < size; ++i) 72112127Sspwilson2@wisc.edu threadContexts[i]->profileSample(); 7221917SN/A 72312127Sspwilson2@wisc.edu schedule(profileEvent, curTick() + params()->profile); 7241917SN/A} 7251917SN/A 7262SN/Avoid 72710905Sandreas.sandberg@arm.comBaseCPU::serialize(CheckpointOut &cp) const 728921SN/A{ 7294000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(instCnt); 7309332Sdam.sunwoo@arm.com 7319448SAndreas.Sandberg@ARM.com if (!_switchedOut) { 7329448SAndreas.Sandberg@ARM.com /* Unlike _pid, _taskId is not serialized, as they are dynamically 7339448SAndreas.Sandberg@ARM.com * assigned unique ids that are only meaningful for the duration of 7349448SAndreas.Sandberg@ARM.com * a specific run. We will need to serialize the entire taskMap in 7359448SAndreas.Sandberg@ARM.com * system. */ 7369448SAndreas.Sandberg@ARM.com SERIALIZE_SCALAR(_pid); 7379332Sdam.sunwoo@arm.com 7389448SAndreas.Sandberg@ARM.com // Serialize the threads, this is done by the CPU implementation. 7399448SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < numThreads; ++i) { 74010905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("xc.%i", i)); 74111150Smitch.hayenga@arm.com interrupts[i]->serialize(cp); 74210905Sandreas.sandberg@arm.com serializeThread(cp, i); 7439448SAndreas.Sandberg@ARM.com } 7449448SAndreas.Sandberg@ARM.com } 745921SN/A} 746921SN/A 747921SN/Avoid 74810905Sandreas.sandberg@arm.comBaseCPU::unserialize(CheckpointIn &cp) 749921SN/A{ 7504000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(instCnt); 7519448SAndreas.Sandberg@ARM.com 7529448SAndreas.Sandberg@ARM.com if (!_switchedOut) { 7539448SAndreas.Sandberg@ARM.com UNSERIALIZE_SCALAR(_pid); 7549448SAndreas.Sandberg@ARM.com 7559448SAndreas.Sandberg@ARM.com // Unserialize the threads, this is done by the CPU implementation. 75610905Sandreas.sandberg@arm.com for (ThreadID i = 0; i < numThreads; ++i) { 75710905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("xc.%i", i)); 75811150Smitch.hayenga@arm.com interrupts[i]->unserialize(cp); 75910905Sandreas.sandberg@arm.com unserializeThread(cp, i); 76010905Sandreas.sandberg@arm.com } 7619448SAndreas.Sandberg@ARM.com } 762921SN/A} 763921SN/A 7641191SN/Avoid 7659749Sandreas@sandberg.pp.seBaseCPU::scheduleInstStop(ThreadID tid, Counter insts, const char *cause) 7669749Sandreas@sandberg.pp.se{ 7679749Sandreas@sandberg.pp.se const Tick now(comInstEventQueue[tid]->getCurTick()); 7689983Sstever@gmail.com Event *event(new LocalSimLoopExitEvent(cause, 0)); 7699749Sandreas@sandberg.pp.se 7709749Sandreas@sandberg.pp.se comInstEventQueue[tid]->schedule(event, now + insts); 7719749Sandreas@sandberg.pp.se} 7729749Sandreas@sandberg.pp.se 77311415SGeoffrey.Blake@arm.comuint64_t 77411415SGeoffrey.Blake@arm.comBaseCPU::getCurrentInstCount(ThreadID tid) 77511415SGeoffrey.Blake@arm.com{ 77611415SGeoffrey.Blake@arm.com return Tick(comInstEventQueue[tid]->getCurTick()); 77711415SGeoffrey.Blake@arm.com} 77811415SGeoffrey.Blake@arm.com 77910529Smorr@cs.wisc.eduAddressMonitor::AddressMonitor() { 78010529Smorr@cs.wisc.edu armed = false; 78110529Smorr@cs.wisc.edu waiting = false; 78210529Smorr@cs.wisc.edu gotWakeup = false; 78310529Smorr@cs.wisc.edu} 78410529Smorr@cs.wisc.edu 78510529Smorr@cs.wisc.edubool AddressMonitor::doMonitor(PacketPtr pkt) { 78610529Smorr@cs.wisc.edu assert(pkt->req->hasPaddr()); 78711321Ssteve.reinhardt@amd.com if (armed && waiting) { 78811321Ssteve.reinhardt@amd.com if (pAddr == pkt->getAddr()) { 78910529Smorr@cs.wisc.edu DPRINTF(Mwait,"pAddr=0x%lx invalidated: waking up core\n", 79010529Smorr@cs.wisc.edu pkt->getAddr()); 79110529Smorr@cs.wisc.edu waiting = false; 79210529Smorr@cs.wisc.edu return true; 79310529Smorr@cs.wisc.edu } 79410529Smorr@cs.wisc.edu } 79510529Smorr@cs.wisc.edu return false; 79610529Smorr@cs.wisc.edu} 79710529Smorr@cs.wisc.edu 7989749Sandreas@sandberg.pp.sevoid 7999749Sandreas@sandberg.pp.seBaseCPU::scheduleLoadStop(ThreadID tid, Counter loads, const char *cause) 8009749Sandreas@sandberg.pp.se{ 8019749Sandreas@sandberg.pp.se const Tick now(comLoadEventQueue[tid]->getCurTick()); 8029983Sstever@gmail.com Event *event(new LocalSimLoopExitEvent(cause, 0)); 8039749Sandreas@sandberg.pp.se 8049749Sandreas@sandberg.pp.se comLoadEventQueue[tid]->schedule(event, now + loads); 8059749Sandreas@sandberg.pp.se} 8069749Sandreas@sandberg.pp.se 8079749Sandreas@sandberg.pp.se 8089749Sandreas@sandberg.pp.sevoid 8091191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 8101191SN/A{ 8111191SN/A if (!debugSymbolTable) 8121191SN/A return; 8131191SN/A 8141191SN/A // if pc enters different function, print new function symbol and 8151191SN/A // update saved range. Otherwise do nothing. 8161191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 8171191SN/A string sym_str; 8181191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 8191191SN/A currentFunctionStart, 8201191SN/A currentFunctionEnd); 8211191SN/A 8221191SN/A if (!found) { 8231191SN/A // no symbol found: use addr as label 8241191SN/A sym_str = csprintf("0x%x", pc); 8251191SN/A currentFunctionStart = pc; 8261191SN/A currentFunctionEnd = pc + 1; 8271191SN/A } 8281191SN/A 8291191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 8307823Ssteve.reinhardt@amd.com curTick() - functionEntryTick, curTick(), sym_str); 8317823Ssteve.reinhardt@amd.com functionEntryTick = curTick(); 8321191SN/A } 8331191SN/A} 83412122Sjose.marinho@arm.com 83512122Sjose.marinho@arm.combool 83612122Sjose.marinho@arm.comBaseCPU::waitForRemoteGDB() const 83712122Sjose.marinho@arm.com{ 83812122Sjose.marinho@arm.com return params()->wait_for_remote_gdb; 83912122Sjose.marinho@arm.com} 840