base.cc revision 12276
12SN/A/* 212276Sanouk.vanlaer@arm.com * Copyright (c) 2011-2012,2016-2017 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 169983Sstever@gmail.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 179983Sstever@gmail.com * Copyright (c) 2013 Mark D. Hill and David A. Wood 182SN/A * All rights reserved. 192SN/A * 202SN/A * Redistribution and use in source and binary forms, with or without 212SN/A * modification, are permitted provided that the following conditions are 222SN/A * met: redistributions of source code must retain the above copyright 232SN/A * notice, this list of conditions and the following disclaimer; 242SN/A * redistributions in binary form must reproduce the above copyright 252SN/A * notice, this list of conditions and the following disclaimer in the 262SN/A * documentation and/or other materials provided with the distribution; 272SN/A * neither the name of the copyright holders nor the names of its 282SN/A * contributors may be used to endorse or promote products derived from 292SN/A * this software without specific prior written permission. 302SN/A * 312SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 322SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 332SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 342SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 352SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 362SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 372SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 382SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 392SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 402SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 412SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 422665Ssaidi@eecs.umich.edu * 432665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 442665Ssaidi@eecs.umich.edu * Nathan Binkert 457897Shestness@cs.utexas.edu * Rick Strong 462SN/A */ 472SN/A 4811793Sbrandon.potter@amd.com#include "cpu/base.hh" 4911793Sbrandon.potter@amd.com 501388SN/A#include <iostream> 518229Snate@binkert.org#include <sstream> 522SN/A#include <string> 532SN/A 547781SAli.Saidi@ARM.com#include "arch/tlb.hh" 5511793Sbrandon.potter@amd.com#include "base/cprintf.hh" 568229Snate@binkert.org#include "base/loader/symtab.hh" 571191SN/A#include "base/misc.hh" 581388SN/A#include "base/output.hh" 595529Snate@binkert.org#include "base/trace.hh" 6010529Smorr@cs.wisc.edu#include "cpu/checker/cpu.hh" 612651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 628229Snate@binkert.org#include "cpu/profile.hh" 632680Sktlim@umich.edu#include "cpu/thread_context.hh" 6410529Smorr@cs.wisc.edu#include "debug/Mwait.hh" 658232Snate@binkert.org#include "debug/SyscallVerbose.hh" 6610529Smorr@cs.wisc.edu#include "mem/page_table.hh" 675529Snate@binkert.org#include "params/BaseCPU.hh" 6811526Sdavid.guillen@arm.com#include "sim/clocked_object.hh" 698779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 702190SN/A#include "sim/process.hh" 7156SN/A#include "sim/sim_events.hh" 728229Snate@binkert.org#include "sim/sim_exit.hh" 732190SN/A#include "sim/system.hh" 742SN/A 752359SN/A// Hack 762359SN/A#include "sim/stat_control.hh" 772359SN/A 782SN/Ausing namespace std; 792SN/A 802SN/Avector<BaseCPU *> BaseCPU::cpuList; 812SN/A 822SN/A// This variable reflects the max number of threads in any CPU. Be 832SN/A// careful to only use it once all the CPUs that you care about have 842SN/A// been initialized 852SN/Aint maxThreadsPerCPU = 1; 862SN/A 875606Snate@binkert.orgCPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 886144Sksewell@umich.edu : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 896144Sksewell@umich.edu cpu(_cpu), _repeatEvent(true) 903126Sktlim@umich.edu{ 916144Sksewell@umich.edu if (_interval) 927823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 933126Sktlim@umich.edu} 943126Sktlim@umich.edu 952356SN/Avoid 962356SN/ACPUProgressEvent::process() 972356SN/A{ 988834Satgutier@umich.edu Counter temp = cpu->totalOps(); 9910786Smalek.musleh@gmail.com 10010786Smalek.musleh@gmail.com if (_repeatEvent) 10110786Smalek.musleh@gmail.com cpu->schedule(this, curTick() + _interval); 10210786Smalek.musleh@gmail.com 10311321Ssteve.reinhardt@amd.com if (cpu->switchedOut()) { 10410786Smalek.musleh@gmail.com return; 10510786Smalek.musleh@gmail.com } 10610786Smalek.musleh@gmail.com 1072356SN/A#ifndef NDEBUG 1089179Sandreas.hansson@arm.com double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod()); 1092367SN/A 1106144Sksewell@umich.edu DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 1116144Sksewell@umich.edu "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 1126144Sksewell@umich.edu ipc); 1132356SN/A ipc = 0.0; 1142367SN/A#else 1156144Sksewell@umich.edu cprintf("%lli: %s progress event, total committed:%i, progress insts " 1167823Ssteve.reinhardt@amd.com "committed: %lli\n", curTick(), cpu->name(), temp, 1176144Sksewell@umich.edu temp - lastNumInst); 1182367SN/A#endif 1192356SN/A lastNumInst = temp; 1202356SN/A} 1212356SN/A 1222356SN/Aconst char * 1235336Shines@cs.fsu.eduCPUProgressEvent::description() const 1242356SN/A{ 1254873Sstever@eecs.umich.edu return "CPU Progress"; 1262356SN/A} 1272356SN/A 1288876Sandreas.hansson@arm.comBaseCPU::BaseCPU(Params *p, bool is_checker) 12910190Sakash.bagdia@arm.com : MemObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id), 1308832SAli.Saidi@ARM.com _instMasterId(p->system->getMasterId(name() + ".inst")), 1318832SAli.Saidi@ARM.com _dataMasterId(p->system->getMasterId(name() + ".data")), 13211050Sandreas.hansson@arm.com _taskId(ContextSwitchTaskId::Unknown), _pid(invldPid), 1339814Sandreas.hansson@arm.com _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()), 1349220Shestness@cs.wisc.edu interrupts(p->interrupts), profileEvent(NULL), 13510529Smorr@cs.wisc.edu numThreads(p->numThreads), system(p->system), 13610537Sandreas.hansson@arm.com functionTraceStream(nullptr), currentFunctionStart(0), 13710537Sandreas.hansson@arm.com currentFunctionEnd(0), functionEntryTick(0), 13811877Sbrandon.potter@amd.com addressMonitor(p->numThreads), 13912276Sanouk.vanlaer@arm.com syscallRetryLatency(p->syscallRetryLatency), 14012276Sanouk.vanlaer@arm.com pwrGatingLatency(p->pwr_gating_latency), 14112276Sanouk.vanlaer@arm.com enterPwrGatingEvent([this]{ enterPwrGating(); }, name()) 1422SN/A{ 1435712Shsul@eecs.umich.edu // if Python did not provide a valid ID, do it here 1445712Shsul@eecs.umich.edu if (_cpuId == -1 ) { 1455712Shsul@eecs.umich.edu _cpuId = cpuList.size(); 1465712Shsul@eecs.umich.edu } 1475712Shsul@eecs.umich.edu 1482SN/A // add self to global list of CPUs 1492SN/A cpuList.push_back(this); 1502SN/A 15110190Sakash.bagdia@arm.com DPRINTF(SyscallVerbose, "Constructing CPU with id %d, socket id %d\n", 15210190Sakash.bagdia@arm.com _cpuId, _socketId); 1535712Shsul@eecs.umich.edu 1546221Snate@binkert.org if (numThreads > maxThreadsPerCPU) 1556221Snate@binkert.org maxThreadsPerCPU = numThreads; 1562SN/A 1572SN/A // allocate per-thread instruction-based event queues 1586221Snate@binkert.org comInstEventQueue = new EventQueue *[numThreads]; 1596221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1606221Snate@binkert.org comInstEventQueue[tid] = 1616221Snate@binkert.org new EventQueue("instruction-based event queue"); 1622SN/A 1632SN/A // 1642SN/A // set up instruction-count-based termination events, if any 1652SN/A // 1665606Snate@binkert.org if (p->max_insts_any_thread != 0) { 1675606Snate@binkert.org const char *cause = "a thread reached the max instruction count"; 1689749Sandreas@sandberg.pp.se for (ThreadID tid = 0; tid < numThreads; ++tid) 1699749Sandreas@sandberg.pp.se scheduleInstStop(tid, p->max_insts_any_thread, cause); 1705606Snate@binkert.org } 1712SN/A 1729647Sdam.sunwoo@arm.com // Set up instruction-count-based termination events for SimPoints 1739647Sdam.sunwoo@arm.com // Typically, there are more than one action points. 1749647Sdam.sunwoo@arm.com // Simulation.py is responsible to take the necessary actions upon 1759647Sdam.sunwoo@arm.com // exitting the simulation loop. 1769647Sdam.sunwoo@arm.com if (!p->simpoint_start_insts.empty()) { 1779647Sdam.sunwoo@arm.com const char *cause = "simpoint starting point found"; 1789749Sandreas@sandberg.pp.se for (size_t i = 0; i < p->simpoint_start_insts.size(); ++i) 1799749Sandreas@sandberg.pp.se scheduleInstStop(0, p->simpoint_start_insts[i], cause); 1809647Sdam.sunwoo@arm.com } 1819647Sdam.sunwoo@arm.com 1821400SN/A if (p->max_insts_all_threads != 0) { 1835606Snate@binkert.org const char *cause = "all threads reached the max instruction count"; 1845606Snate@binkert.org 1852SN/A // allocate & initialize shared downcounter: each event will 1862SN/A // decrement this when triggered; simulation will terminate 1872SN/A // when counter reaches 0 1882SN/A int *counter = new int; 1896221Snate@binkert.org *counter = numThreads; 1906221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1915606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1926670Shsul@eecs.umich.edu comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 1935606Snate@binkert.org } 1942SN/A } 1952SN/A 196124SN/A // allocate per-thread load-based event queues 1976221Snate@binkert.org comLoadEventQueue = new EventQueue *[numThreads]; 1986221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1996221Snate@binkert.org comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 200124SN/A 201124SN/A // 202124SN/A // set up instruction-count-based termination events, if any 203124SN/A // 2045606Snate@binkert.org if (p->max_loads_any_thread != 0) { 2055606Snate@binkert.org const char *cause = "a thread reached the max load count"; 2069749Sandreas@sandberg.pp.se for (ThreadID tid = 0; tid < numThreads; ++tid) 2079749Sandreas@sandberg.pp.se scheduleLoadStop(tid, p->max_loads_any_thread, cause); 2085606Snate@binkert.org } 209124SN/A 2101400SN/A if (p->max_loads_all_threads != 0) { 2115606Snate@binkert.org const char *cause = "all threads reached the max load count"; 212124SN/A // allocate & initialize shared downcounter: each event will 213124SN/A // decrement this when triggered; simulation will terminate 214124SN/A // when counter reaches 0 215124SN/A int *counter = new int; 2166221Snate@binkert.org *counter = numThreads; 2176221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 2185606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 2196221Snate@binkert.org comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 2205606Snate@binkert.org } 221124SN/A } 222124SN/A 2231191SN/A functionTracingEnabled = false; 2245529Snate@binkert.org if (p->function_trace) { 2258634Schris.emmons@arm.com const string fname = csprintf("ftrace.%s", name()); 22611359Sandreas@sandberg.pp.se functionTraceStream = simout.findOrCreate(fname)->stream(); 2278634Schris.emmons@arm.com 2281191SN/A currentFunctionStart = currentFunctionEnd = 0; 2295529Snate@binkert.org functionEntryTick = p->function_trace_start; 2301191SN/A 2315529Snate@binkert.org if (p->function_trace_start == 0) { 2321191SN/A functionTracingEnabled = true; 2331191SN/A } else { 23412085Sspwilson2@wisc.edu Event *event = new EventFunctionWrapper( 23512085Sspwilson2@wisc.edu [this]{ enableFunctionTrace(); }, name(), true); 2365606Snate@binkert.org schedule(event, p->function_trace_start); 2371191SN/A } 2381191SN/A } 2398876Sandreas.hansson@arm.com 2408876Sandreas.hansson@arm.com // The interrupts should always be present unless this CPU is 2418876Sandreas.hansson@arm.com // switched in later or in case it is a checker CPU 2429433SAndreas.Sandberg@ARM.com if (!params()->switched_out && !is_checker) { 24311221Sandreas.sandberg@arm.com fatal_if(interrupts.size() != numThreads, 24411221Sandreas.sandberg@arm.com "CPU %s has %i interrupt controllers, but is expecting one " 24511221Sandreas.sandberg@arm.com "per thread (%i)\n", 24611221Sandreas.sandberg@arm.com name(), interrupts.size(), numThreads); 24711221Sandreas.sandberg@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) 24811221Sandreas.sandberg@arm.com interrupts[tid]->setCPU(this); 2498876Sandreas.hansson@arm.com } 2505810Sgblack@eecs.umich.edu 2518779Sgblack@eecs.umich.edu if (FullSystem) { 2528779Sgblack@eecs.umich.edu if (params()->profile) 25312127Sspwilson2@wisc.edu profileEvent = new EventFunctionWrapper( 25412127Sspwilson2@wisc.edu [this]{ processProfileEvent(); }, 25512127Sspwilson2@wisc.edu name()); 2568779Sgblack@eecs.umich.edu } 2575529Snate@binkert.org tracer = params()->tracer; 2589384SAndreas.Sandberg@arm.com 2599384SAndreas.Sandberg@arm.com if (params()->isa.size() != numThreads) { 2609384SAndreas.Sandberg@arm.com fatal("Number of ISAs (%i) assigned to the CPU does not equal number " 2619384SAndreas.Sandberg@arm.com "of threads (%i).\n", params()->isa.size(), numThreads); 2629384SAndreas.Sandberg@arm.com } 2631917SN/A} 2641191SN/A 2651191SN/Avoid 2661191SN/ABaseCPU::enableFunctionTrace() 2671191SN/A{ 2681191SN/A functionTracingEnabled = true; 2691191SN/A} 2701191SN/A 2711191SN/ABaseCPU::~BaseCPU() 2721191SN/A{ 2739086Sandreas.hansson@arm.com delete profileEvent; 2749086Sandreas.hansson@arm.com delete[] comLoadEventQueue; 2759086Sandreas.hansson@arm.com delete[] comInstEventQueue; 2761191SN/A} 2771191SN/A 2781129SN/Avoid 27911148Smitch.hayenga@arm.comBaseCPU::armMonitor(ThreadID tid, Addr address) 28010529Smorr@cs.wisc.edu{ 28111148Smitch.hayenga@arm.com assert(tid < numThreads); 28211148Smitch.hayenga@arm.com AddressMonitor &monitor = addressMonitor[tid]; 28311148Smitch.hayenga@arm.com 28411148Smitch.hayenga@arm.com monitor.armed = true; 28511148Smitch.hayenga@arm.com monitor.vAddr = address; 28611148Smitch.hayenga@arm.com monitor.pAddr = 0x0; 28711148Smitch.hayenga@arm.com DPRINTF(Mwait,"[tid:%d] Armed monitor (vAddr=0x%lx)\n", tid, address); 28810529Smorr@cs.wisc.edu} 28910529Smorr@cs.wisc.edu 29010529Smorr@cs.wisc.edubool 29111148Smitch.hayenga@arm.comBaseCPU::mwait(ThreadID tid, PacketPtr pkt) 29210529Smorr@cs.wisc.edu{ 29311148Smitch.hayenga@arm.com assert(tid < numThreads); 29411148Smitch.hayenga@arm.com AddressMonitor &monitor = addressMonitor[tid]; 29511148Smitch.hayenga@arm.com 29611325Ssteve.reinhardt@amd.com if (!monitor.gotWakeup) { 29710529Smorr@cs.wisc.edu int block_size = cacheLineSize(); 29810529Smorr@cs.wisc.edu uint64_t mask = ~((uint64_t)(block_size - 1)); 29910529Smorr@cs.wisc.edu 30010529Smorr@cs.wisc.edu assert(pkt->req->hasPaddr()); 30111148Smitch.hayenga@arm.com monitor.pAddr = pkt->getAddr() & mask; 30211148Smitch.hayenga@arm.com monitor.waiting = true; 30310529Smorr@cs.wisc.edu 30411148Smitch.hayenga@arm.com DPRINTF(Mwait,"[tid:%d] mwait called (vAddr=0x%lx, " 30511148Smitch.hayenga@arm.com "line's paddr=0x%lx)\n", tid, monitor.vAddr, monitor.pAddr); 30610529Smorr@cs.wisc.edu return true; 30710529Smorr@cs.wisc.edu } else { 30811148Smitch.hayenga@arm.com monitor.gotWakeup = false; 30910529Smorr@cs.wisc.edu return false; 31010529Smorr@cs.wisc.edu } 31110529Smorr@cs.wisc.edu} 31210529Smorr@cs.wisc.edu 31310529Smorr@cs.wisc.eduvoid 31411148Smitch.hayenga@arm.comBaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, TheISA::TLB *dtb) 31510529Smorr@cs.wisc.edu{ 31611148Smitch.hayenga@arm.com assert(tid < numThreads); 31711148Smitch.hayenga@arm.com AddressMonitor &monitor = addressMonitor[tid]; 31811148Smitch.hayenga@arm.com 31910529Smorr@cs.wisc.edu Request req; 32011148Smitch.hayenga@arm.com Addr addr = monitor.vAddr; 32110529Smorr@cs.wisc.edu int block_size = cacheLineSize(); 32210529Smorr@cs.wisc.edu uint64_t mask = ~((uint64_t)(block_size - 1)); 32310529Smorr@cs.wisc.edu int size = block_size; 32410529Smorr@cs.wisc.edu 32510529Smorr@cs.wisc.edu //The address of the next line if it crosses a cache line boundary. 32610529Smorr@cs.wisc.edu Addr secondAddr = roundDown(addr + size - 1, block_size); 32710529Smorr@cs.wisc.edu 32810529Smorr@cs.wisc.edu if (secondAddr > addr) 32910529Smorr@cs.wisc.edu size = secondAddr - addr; 33010529Smorr@cs.wisc.edu 33110529Smorr@cs.wisc.edu req.setVirt(0, addr, size, 0x0, dataMasterId(), tc->instAddr()); 33210529Smorr@cs.wisc.edu 33310529Smorr@cs.wisc.edu // translate to physical address 33410529Smorr@cs.wisc.edu Fault fault = dtb->translateAtomic(&req, tc, BaseTLB::Read); 33510529Smorr@cs.wisc.edu assert(fault == NoFault); 33610529Smorr@cs.wisc.edu 33711148Smitch.hayenga@arm.com monitor.pAddr = req.getPaddr() & mask; 33811148Smitch.hayenga@arm.com monitor.waiting = true; 33910529Smorr@cs.wisc.edu 34011148Smitch.hayenga@arm.com DPRINTF(Mwait,"[tid:%d] mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n", 34111148Smitch.hayenga@arm.com tid, monitor.vAddr, monitor.pAddr); 34210529Smorr@cs.wisc.edu} 34310529Smorr@cs.wisc.edu 34410529Smorr@cs.wisc.eduvoid 3451129SN/ABaseCPU::init() 3461129SN/A{ 3479523SAndreas.Sandberg@ARM.com if (!params()->switched_out) { 3482680Sktlim@umich.edu registerThreadContexts(); 3499523SAndreas.Sandberg@ARM.com 3509523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 3519523SAndreas.Sandberg@ARM.com } 3521129SN/A} 353180SN/A 3542SN/Avoid 3551917SN/ABaseCPU::startup() 3561917SN/A{ 3578779Sgblack@eecs.umich.edu if (FullSystem) { 3589433SAndreas.Sandberg@ARM.com if (!params()->switched_out && profileEvent) 3598779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 3608779Sgblack@eecs.umich.edu } 3612356SN/A 3625529Snate@binkert.org if (params()->progress_interval) { 3639179Sandreas.hansson@arm.com new CPUProgressEvent(this, params()->progress_interval); 3642356SN/A } 36511526Sdavid.guillen@arm.com 36612276Sanouk.vanlaer@arm.com if (_switchedOut) 36712276Sanouk.vanlaer@arm.com ClockedObject::pwrState(Enums::PwrState::OFF); 36812276Sanouk.vanlaer@arm.com 36911526Sdavid.guillen@arm.com // Assumption CPU start to operate instantaneously without any latency 37011526Sdavid.guillen@arm.com if (ClockedObject::pwrState() == Enums::PwrState::UNDEFINED) 37111526Sdavid.guillen@arm.com ClockedObject::pwrState(Enums::PwrState::ON); 37211526Sdavid.guillen@arm.com 3731917SN/A} 3741917SN/A 37510464SAndreas.Sandberg@ARM.comProbePoints::PMUUPtr 37610464SAndreas.Sandberg@ARM.comBaseCPU::pmuProbePoint(const char *name) 37710464SAndreas.Sandberg@ARM.com{ 37810464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ptr; 37910464SAndreas.Sandberg@ARM.com ptr.reset(new ProbePoints::PMU(getProbeManager(), name)); 38010464SAndreas.Sandberg@ARM.com 38110464SAndreas.Sandberg@ARM.com return ptr; 38210464SAndreas.Sandberg@ARM.com} 38310464SAndreas.Sandberg@ARM.com 38410464SAndreas.Sandberg@ARM.comvoid 38510464SAndreas.Sandberg@ARM.comBaseCPU::regProbePoints() 38610464SAndreas.Sandberg@ARM.com{ 38710464SAndreas.Sandberg@ARM.com ppCycles = pmuProbePoint("Cycles"); 38810464SAndreas.Sandberg@ARM.com 38910464SAndreas.Sandberg@ARM.com ppRetiredInsts = pmuProbePoint("RetiredInsts"); 39010464SAndreas.Sandberg@ARM.com ppRetiredLoads = pmuProbePoint("RetiredLoads"); 39110464SAndreas.Sandberg@ARM.com ppRetiredStores = pmuProbePoint("RetiredStores"); 39210464SAndreas.Sandberg@ARM.com ppRetiredBranches = pmuProbePoint("RetiredBranches"); 39310464SAndreas.Sandberg@ARM.com} 39410464SAndreas.Sandberg@ARM.com 39510464SAndreas.Sandberg@ARM.comvoid 39610464SAndreas.Sandberg@ARM.comBaseCPU::probeInstCommit(const StaticInstPtr &inst) 39710464SAndreas.Sandberg@ARM.com{ 39810464SAndreas.Sandberg@ARM.com if (!inst->isMicroop() || inst->isLastMicroop()) 39910464SAndreas.Sandberg@ARM.com ppRetiredInsts->notify(1); 40010464SAndreas.Sandberg@ARM.com 40110464SAndreas.Sandberg@ARM.com 40210464SAndreas.Sandberg@ARM.com if (inst->isLoad()) 40310464SAndreas.Sandberg@ARM.com ppRetiredLoads->notify(1); 40410464SAndreas.Sandberg@ARM.com 40510464SAndreas.Sandberg@ARM.com if (inst->isStore()) 40610643Snikos.nikoleris@gmail.com ppRetiredStores->notify(1); 40710464SAndreas.Sandberg@ARM.com 40810464SAndreas.Sandberg@ARM.com if (inst->isControl()) 40910464SAndreas.Sandberg@ARM.com ppRetiredBranches->notify(1); 41010464SAndreas.Sandberg@ARM.com} 4111917SN/A 4121917SN/Avoid 4132SN/ABaseCPU::regStats() 4142SN/A{ 41511522Sstephan.diestelhorst@arm.com MemObject::regStats(); 41611522Sstephan.diestelhorst@arm.com 417729SN/A using namespace Stats; 418707SN/A 419707SN/A numCycles 420707SN/A .name(name() + ".numCycles") 421707SN/A .desc("number of cpu cycles simulated") 422707SN/A ; 423707SN/A 4247914SBrad.Beckmann@amd.com numWorkItemsStarted 4257914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsStarted") 4267914SBrad.Beckmann@amd.com .desc("number of work items this cpu started") 4277914SBrad.Beckmann@amd.com ; 4287914SBrad.Beckmann@amd.com 4297914SBrad.Beckmann@amd.com numWorkItemsCompleted 4307914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsCompleted") 4317914SBrad.Beckmann@amd.com .desc("number of work items this cpu completed") 4327914SBrad.Beckmann@amd.com ; 4337914SBrad.Beckmann@amd.com 4342680Sktlim@umich.edu int size = threadContexts.size(); 4352SN/A if (size > 1) { 4362SN/A for (int i = 0; i < size; ++i) { 4372SN/A stringstream namestr; 4382SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 4392680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 4402SN/A } 4412SN/A } else if (size == 1) 4422680Sktlim@umich.edu threadContexts[0]->regStats(name()); 4432SN/A} 4442SN/A 4459294Sandreas.hansson@arm.comBaseMasterPort & 4469294Sandreas.hansson@arm.comBaseCPU::getMasterPort(const string &if_name, PortID idx) 4478850Sandreas.hansson@arm.com{ 4488850Sandreas.hansson@arm.com // Get the right port based on name. This applies to all the 4498850Sandreas.hansson@arm.com // subclasses of the base CPU and relies on their implementation 4508850Sandreas.hansson@arm.com // of getDataPort and getInstPort. In all cases there methods 4519608Sandreas.hansson@arm.com // return a MasterPort pointer. 4528850Sandreas.hansson@arm.com if (if_name == "dcache_port") 4538922Swilliam.wang@arm.com return getDataPort(); 4548850Sandreas.hansson@arm.com else if (if_name == "icache_port") 4558922Swilliam.wang@arm.com return getInstPort(); 4568850Sandreas.hansson@arm.com else 4578922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 4588850Sandreas.hansson@arm.com} 4598850Sandreas.hansson@arm.com 460180SN/Avoid 4612680Sktlim@umich.eduBaseCPU::registerThreadContexts() 462180SN/A{ 46311146Smitch.hayenga@arm.com assert(system->multiThread || numThreads == 1); 46411146Smitch.hayenga@arm.com 4656221Snate@binkert.org ThreadID size = threadContexts.size(); 4666221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 4676221Snate@binkert.org ThreadContext *tc = threadContexts[tid]; 4682378SN/A 46911146Smitch.hayenga@arm.com if (system->multiThread) { 47011146Smitch.hayenga@arm.com tc->setContextId(system->registerThreadContext(tc)); 47111146Smitch.hayenga@arm.com } else { 4725718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc, _cpuId)); 47311146Smitch.hayenga@arm.com } 4748779Sgblack@eecs.umich.edu 4758779Sgblack@eecs.umich.edu if (!FullSystem) 4768779Sgblack@eecs.umich.edu tc->getProcessPtr()->assignThreadContext(tc->contextId()); 477180SN/A } 478180SN/A} 479180SN/A 48012276Sanouk.vanlaer@arm.comvoid 48112276Sanouk.vanlaer@arm.comBaseCPU::deschedulePowerGatingEvent() 48212276Sanouk.vanlaer@arm.com{ 48312276Sanouk.vanlaer@arm.com if (enterPwrGatingEvent.scheduled()){ 48412276Sanouk.vanlaer@arm.com deschedule(enterPwrGatingEvent); 48512276Sanouk.vanlaer@arm.com } 48612276Sanouk.vanlaer@arm.com} 48712276Sanouk.vanlaer@arm.com 48812276Sanouk.vanlaer@arm.comvoid 48912276Sanouk.vanlaer@arm.comBaseCPU::schedulePowerGatingEvent() 49012276Sanouk.vanlaer@arm.com{ 49112276Sanouk.vanlaer@arm.com for (auto tc : threadContexts) { 49212276Sanouk.vanlaer@arm.com if (tc->status() == ThreadContext::Active) 49312276Sanouk.vanlaer@arm.com return; 49412276Sanouk.vanlaer@arm.com } 49512276Sanouk.vanlaer@arm.com 49612276Sanouk.vanlaer@arm.com if (ClockedObject::pwrState() == Enums::PwrState::CLK_GATED) { 49712276Sanouk.vanlaer@arm.com assert(!enterPwrGatingEvent.scheduled()); 49812276Sanouk.vanlaer@arm.com // Schedule a power gating event when clock gated for the specified 49912276Sanouk.vanlaer@arm.com // amount of time 50012276Sanouk.vanlaer@arm.com schedule(enterPwrGatingEvent, clockEdge(pwrGatingLatency)); 50112276Sanouk.vanlaer@arm.com } 50212276Sanouk.vanlaer@arm.com} 503180SN/A 5044000Ssaidi@eecs.umich.eduint 5054000Ssaidi@eecs.umich.eduBaseCPU::findContext(ThreadContext *tc) 5064000Ssaidi@eecs.umich.edu{ 5076221Snate@binkert.org ThreadID size = threadContexts.size(); 5086221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 5096221Snate@binkert.org if (tc == threadContexts[tid]) 5106221Snate@binkert.org return tid; 5114000Ssaidi@eecs.umich.edu } 5124000Ssaidi@eecs.umich.edu return 0; 5134000Ssaidi@eecs.umich.edu} 5144000Ssaidi@eecs.umich.edu 515180SN/Avoid 51611526Sdavid.guillen@arm.comBaseCPU::activateContext(ThreadID thread_num) 51711526Sdavid.guillen@arm.com{ 51812276Sanouk.vanlaer@arm.com // Squash enter power gating event while cpu gets activated 51912276Sanouk.vanlaer@arm.com if (enterPwrGatingEvent.scheduled()) 52012276Sanouk.vanlaer@arm.com deschedule(enterPwrGatingEvent); 52112276Sanouk.vanlaer@arm.com 52211526Sdavid.guillen@arm.com // For any active thread running, update CPU power state to active (ON) 52311526Sdavid.guillen@arm.com ClockedObject::pwrState(Enums::PwrState::ON); 52411526Sdavid.guillen@arm.com} 52511526Sdavid.guillen@arm.com 52611526Sdavid.guillen@arm.comvoid 52711526Sdavid.guillen@arm.comBaseCPU::suspendContext(ThreadID thread_num) 52811526Sdavid.guillen@arm.com{ 52911526Sdavid.guillen@arm.com // Check if all threads are suspended 53011526Sdavid.guillen@arm.com for (auto t : threadContexts) { 53111526Sdavid.guillen@arm.com if (t->status() != ThreadContext::Suspended) { 53211526Sdavid.guillen@arm.com return; 53311526Sdavid.guillen@arm.com } 53411526Sdavid.guillen@arm.com } 53511526Sdavid.guillen@arm.com 53611526Sdavid.guillen@arm.com // All CPU threads suspended, enter lower power state for the CPU 53711526Sdavid.guillen@arm.com ClockedObject::pwrState(Enums::PwrState::CLK_GATED); 53812276Sanouk.vanlaer@arm.com 53912276Sanouk.vanlaer@arm.com //Schedule power gating event when clock gated for a configurable cycles 54012276Sanouk.vanlaer@arm.com schedule(enterPwrGatingEvent, clockEdge(pwrGatingLatency)); 54112276Sanouk.vanlaer@arm.com} 54212276Sanouk.vanlaer@arm.com 54312276Sanouk.vanlaer@arm.comvoid 54412276Sanouk.vanlaer@arm.comBaseCPU::enterPwrGating(void) 54512276Sanouk.vanlaer@arm.com{ 54612276Sanouk.vanlaer@arm.com ClockedObject::pwrState(Enums::PwrState::OFF); 54711526Sdavid.guillen@arm.com} 54811526Sdavid.guillen@arm.com 54911526Sdavid.guillen@arm.comvoid 5502798Sktlim@umich.eduBaseCPU::switchOut() 551180SN/A{ 5529430SAndreas.Sandberg@ARM.com assert(!_switchedOut); 5539430SAndreas.Sandberg@ARM.com _switchedOut = true; 5542359SN/A if (profileEvent && profileEvent->scheduled()) 5555606Snate@binkert.org deschedule(profileEvent); 5569446SAndreas.Sandberg@ARM.com 5579446SAndreas.Sandberg@ARM.com // Flush all TLBs in the CPU to avoid having stale translations if 5589446SAndreas.Sandberg@ARM.com // it gets switched in later. 5599446SAndreas.Sandberg@ARM.com flushTLBs(); 56012276Sanouk.vanlaer@arm.com 56112276Sanouk.vanlaer@arm.com // Go to the power gating state 56212276Sanouk.vanlaer@arm.com ClockedObject::pwrState(Enums::PwrState::OFF); 563180SN/A} 564180SN/A 565180SN/Avoid 5668737Skoansin.tan@gmail.comBaseCPU::takeOverFrom(BaseCPU *oldCPU) 567180SN/A{ 5682680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 5699152Satgutier@umich.edu assert(_cpuId == oldCPU->cpuId()); 5709430SAndreas.Sandberg@ARM.com assert(_switchedOut); 5719430SAndreas.Sandberg@ARM.com assert(oldCPU != this); 5729332Sdam.sunwoo@arm.com _pid = oldCPU->getPid(); 5739332Sdam.sunwoo@arm.com _taskId = oldCPU->taskId(); 57412276Sanouk.vanlaer@arm.com // Take over the power state of the switchedOut CPU 57512276Sanouk.vanlaer@arm.com ClockedObject::pwrState(oldCPU->pwrState()); 5769430SAndreas.Sandberg@ARM.com _switchedOut = false; 5775712Shsul@eecs.umich.edu 5786221Snate@binkert.org ThreadID size = threadContexts.size(); 5796221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 5802680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 5812680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 582180SN/A 5832680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 5842651Ssaidi@eecs.umich.edu 5852680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 5862651Ssaidi@eecs.umich.edu 5875714Shsul@eecs.umich.edu assert(newTC->contextId() == oldTC->contextId()); 5885715Shsul@eecs.umich.edu assert(newTC->threadId() == oldTC->threadId()); 5895714Shsul@eecs.umich.edu system->replaceThreadContext(newTC, newTC->contextId()); 5902359SN/A 5915875Ssteve.reinhardt@amd.com /* This code no longer works since the zero register (e.g., 5925875Ssteve.reinhardt@amd.com * r31 on Alpha) doesn't necessarily contain zero at this 5935875Ssteve.reinhardt@amd.com * point. 5945875Ssteve.reinhardt@amd.com if (DTRACE(Context)) 5955217Ssaidi@eecs.umich.edu ThreadContext::compare(oldTC, newTC); 5965875Ssteve.reinhardt@amd.com */ 5977781SAli.Saidi@ARM.com 5989294Sandreas.hansson@arm.com BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort(); 5999294Sandreas.hansson@arm.com BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort(); 6009294Sandreas.hansson@arm.com BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort(); 6019294Sandreas.hansson@arm.com BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort(); 6027781SAli.Saidi@ARM.com 6037781SAli.Saidi@ARM.com // Move over any table walker ports if they exist 6049178Sandreas.hansson@arm.com if (new_itb_port) { 6059178Sandreas.hansson@arm.com assert(!new_itb_port->isConnected()); 6067781SAli.Saidi@ARM.com assert(old_itb_port); 6079178Sandreas.hansson@arm.com assert(old_itb_port->isConnected()); 6089294Sandreas.hansson@arm.com BaseSlavePort &slavePort = old_itb_port->getSlavePort(); 6099178Sandreas.hansson@arm.com old_itb_port->unbind(); 6108922Swilliam.wang@arm.com new_itb_port->bind(slavePort); 6117781SAli.Saidi@ARM.com } 6129178Sandreas.hansson@arm.com if (new_dtb_port) { 6139178Sandreas.hansson@arm.com assert(!new_dtb_port->isConnected()); 6147781SAli.Saidi@ARM.com assert(old_dtb_port); 6159178Sandreas.hansson@arm.com assert(old_dtb_port->isConnected()); 6169294Sandreas.hansson@arm.com BaseSlavePort &slavePort = old_dtb_port->getSlavePort(); 6179178Sandreas.hansson@arm.com old_dtb_port->unbind(); 6188922Swilliam.wang@arm.com new_dtb_port->bind(slavePort); 6197781SAli.Saidi@ARM.com } 62010194SGeoffrey.Blake@arm.com newTC->getITBPtr()->takeOverFrom(oldTC->getITBPtr()); 62110194SGeoffrey.Blake@arm.com newTC->getDTBPtr()->takeOverFrom(oldTC->getDTBPtr()); 6228733Sgeoffrey.blake@arm.com 6238887Sgeoffrey.blake@arm.com // Checker whether or not we have to transfer CheckerCPU 6248887Sgeoffrey.blake@arm.com // objects over in the switch 6258887Sgeoffrey.blake@arm.com CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr(); 6268887Sgeoffrey.blake@arm.com CheckerCPU *newChecker = newTC->getCheckerCpuPtr(); 6278887Sgeoffrey.blake@arm.com if (oldChecker && newChecker) { 6289294Sandreas.hansson@arm.com BaseMasterPort *old_checker_itb_port = 6298922Swilliam.wang@arm.com oldChecker->getITBPtr()->getMasterPort(); 6309294Sandreas.hansson@arm.com BaseMasterPort *old_checker_dtb_port = 6318922Swilliam.wang@arm.com oldChecker->getDTBPtr()->getMasterPort(); 6329294Sandreas.hansson@arm.com BaseMasterPort *new_checker_itb_port = 6338922Swilliam.wang@arm.com newChecker->getITBPtr()->getMasterPort(); 6349294Sandreas.hansson@arm.com BaseMasterPort *new_checker_dtb_port = 6358922Swilliam.wang@arm.com newChecker->getDTBPtr()->getMasterPort(); 6368733Sgeoffrey.blake@arm.com 63710194SGeoffrey.Blake@arm.com newChecker->getITBPtr()->takeOverFrom(oldChecker->getITBPtr()); 63810194SGeoffrey.Blake@arm.com newChecker->getDTBPtr()->takeOverFrom(oldChecker->getDTBPtr()); 63910194SGeoffrey.Blake@arm.com 6408887Sgeoffrey.blake@arm.com // Move over any table walker ports if they exist for checker 6419178Sandreas.hansson@arm.com if (new_checker_itb_port) { 6429178Sandreas.hansson@arm.com assert(!new_checker_itb_port->isConnected()); 6438887Sgeoffrey.blake@arm.com assert(old_checker_itb_port); 6449178Sandreas.hansson@arm.com assert(old_checker_itb_port->isConnected()); 6459294Sandreas.hansson@arm.com BaseSlavePort &slavePort = 6469294Sandreas.hansson@arm.com old_checker_itb_port->getSlavePort(); 6479178Sandreas.hansson@arm.com old_checker_itb_port->unbind(); 6488922Swilliam.wang@arm.com new_checker_itb_port->bind(slavePort); 6498887Sgeoffrey.blake@arm.com } 6509178Sandreas.hansson@arm.com if (new_checker_dtb_port) { 6519178Sandreas.hansson@arm.com assert(!new_checker_dtb_port->isConnected()); 6528887Sgeoffrey.blake@arm.com assert(old_checker_dtb_port); 6539178Sandreas.hansson@arm.com assert(old_checker_dtb_port->isConnected()); 6549294Sandreas.hansson@arm.com BaseSlavePort &slavePort = 6559294Sandreas.hansson@arm.com old_checker_dtb_port->getSlavePort(); 6569178Sandreas.hansson@arm.com old_checker_dtb_port->unbind(); 6578922Swilliam.wang@arm.com new_checker_dtb_port->bind(slavePort); 6588887Sgeoffrey.blake@arm.com } 6598733Sgeoffrey.blake@arm.com } 660180SN/A } 661605SN/A 6623520Sgblack@eecs.umich.edu interrupts = oldCPU->interrupts; 66311150Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 66411150Smitch.hayenga@arm.com interrupts[tid]->setCPU(this); 66511150Smitch.hayenga@arm.com } 66611150Smitch.hayenga@arm.com oldCPU->interrupts.clear(); 6672254SN/A 6688779Sgblack@eecs.umich.edu if (FullSystem) { 6698779Sgblack@eecs.umich.edu for (ThreadID i = 0; i < size; ++i) 6708779Sgblack@eecs.umich.edu threadContexts[i]->profileClear(); 6712254SN/A 6728779Sgblack@eecs.umich.edu if (profileEvent) 6738779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 6748779Sgblack@eecs.umich.edu } 6754192Sktlim@umich.edu 6769178Sandreas.hansson@arm.com // All CPUs have an instruction and a data port, and the new CPU's 6779178Sandreas.hansson@arm.com // ports are dangling while the old CPU has its ports connected 6789178Sandreas.hansson@arm.com // already. Unbind the old CPU and then bind the ports of the one 6799178Sandreas.hansson@arm.com // we are switching to. 6809178Sandreas.hansson@arm.com assert(!getInstPort().isConnected()); 6819178Sandreas.hansson@arm.com assert(oldCPU->getInstPort().isConnected()); 6829294Sandreas.hansson@arm.com BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort(); 6839178Sandreas.hansson@arm.com oldCPU->getInstPort().unbind(); 6849178Sandreas.hansson@arm.com getInstPort().bind(inst_peer_port); 6854192Sktlim@umich.edu 6869178Sandreas.hansson@arm.com assert(!getDataPort().isConnected()); 6879178Sandreas.hansson@arm.com assert(oldCPU->getDataPort().isConnected()); 6889294Sandreas.hansson@arm.com BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort(); 6899178Sandreas.hansson@arm.com oldCPU->getDataPort().unbind(); 6909178Sandreas.hansson@arm.com getDataPort().bind(data_peer_port); 691180SN/A} 692180SN/A 6939446SAndreas.Sandberg@ARM.comvoid 6949446SAndreas.Sandberg@ARM.comBaseCPU::flushTLBs() 6959446SAndreas.Sandberg@ARM.com{ 6969446SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < threadContexts.size(); ++i) { 6979446SAndreas.Sandberg@ARM.com ThreadContext &tc(*threadContexts[i]); 6989446SAndreas.Sandberg@ARM.com CheckerCPU *checker(tc.getCheckerCpuPtr()); 6999446SAndreas.Sandberg@ARM.com 7009446SAndreas.Sandberg@ARM.com tc.getITBPtr()->flushAll(); 7019446SAndreas.Sandberg@ARM.com tc.getDTBPtr()->flushAll(); 7029446SAndreas.Sandberg@ARM.com if (checker) { 7039446SAndreas.Sandberg@ARM.com checker->getITBPtr()->flushAll(); 7049446SAndreas.Sandberg@ARM.com checker->getDTBPtr()->flushAll(); 7059446SAndreas.Sandberg@ARM.com } 7069446SAndreas.Sandberg@ARM.com } 7079446SAndreas.Sandberg@ARM.com} 7089446SAndreas.Sandberg@ARM.com 70912127Sspwilson2@wisc.eduvoid 71012127Sspwilson2@wisc.eduBaseCPU::processProfileEvent() 71112127Sspwilson2@wisc.edu{ 71212127Sspwilson2@wisc.edu ThreadID size = threadContexts.size(); 713180SN/A 71412127Sspwilson2@wisc.edu for (ThreadID i = 0; i < size; ++i) 71512127Sspwilson2@wisc.edu threadContexts[i]->profileSample(); 7161917SN/A 71712127Sspwilson2@wisc.edu schedule(profileEvent, curTick() + params()->profile); 7181917SN/A} 7191917SN/A 7202SN/Avoid 72110905Sandreas.sandberg@arm.comBaseCPU::serialize(CheckpointOut &cp) const 722921SN/A{ 7234000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(instCnt); 7249332Sdam.sunwoo@arm.com 7259448SAndreas.Sandberg@ARM.com if (!_switchedOut) { 7269448SAndreas.Sandberg@ARM.com /* Unlike _pid, _taskId is not serialized, as they are dynamically 7279448SAndreas.Sandberg@ARM.com * assigned unique ids that are only meaningful for the duration of 7289448SAndreas.Sandberg@ARM.com * a specific run. We will need to serialize the entire taskMap in 7299448SAndreas.Sandberg@ARM.com * system. */ 7309448SAndreas.Sandberg@ARM.com SERIALIZE_SCALAR(_pid); 7319332Sdam.sunwoo@arm.com 7329448SAndreas.Sandberg@ARM.com // Serialize the threads, this is done by the CPU implementation. 7339448SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < numThreads; ++i) { 73410905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("xc.%i", i)); 73511150Smitch.hayenga@arm.com interrupts[i]->serialize(cp); 73610905Sandreas.sandberg@arm.com serializeThread(cp, i); 7379448SAndreas.Sandberg@ARM.com } 7389448SAndreas.Sandberg@ARM.com } 739921SN/A} 740921SN/A 741921SN/Avoid 74210905Sandreas.sandberg@arm.comBaseCPU::unserialize(CheckpointIn &cp) 743921SN/A{ 7444000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(instCnt); 7459448SAndreas.Sandberg@ARM.com 7469448SAndreas.Sandberg@ARM.com if (!_switchedOut) { 7479448SAndreas.Sandberg@ARM.com UNSERIALIZE_SCALAR(_pid); 7489448SAndreas.Sandberg@ARM.com 7499448SAndreas.Sandberg@ARM.com // Unserialize the threads, this is done by the CPU implementation. 75010905Sandreas.sandberg@arm.com for (ThreadID i = 0; i < numThreads; ++i) { 75110905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("xc.%i", i)); 75211150Smitch.hayenga@arm.com interrupts[i]->unserialize(cp); 75310905Sandreas.sandberg@arm.com unserializeThread(cp, i); 75410905Sandreas.sandberg@arm.com } 7559448SAndreas.Sandberg@ARM.com } 756921SN/A} 757921SN/A 7581191SN/Avoid 7599749Sandreas@sandberg.pp.seBaseCPU::scheduleInstStop(ThreadID tid, Counter insts, const char *cause) 7609749Sandreas@sandberg.pp.se{ 7619749Sandreas@sandberg.pp.se const Tick now(comInstEventQueue[tid]->getCurTick()); 7629983Sstever@gmail.com Event *event(new LocalSimLoopExitEvent(cause, 0)); 7639749Sandreas@sandberg.pp.se 7649749Sandreas@sandberg.pp.se comInstEventQueue[tid]->schedule(event, now + insts); 7659749Sandreas@sandberg.pp.se} 7669749Sandreas@sandberg.pp.se 76711415SGeoffrey.Blake@arm.comuint64_t 76811415SGeoffrey.Blake@arm.comBaseCPU::getCurrentInstCount(ThreadID tid) 76911415SGeoffrey.Blake@arm.com{ 77011415SGeoffrey.Blake@arm.com return Tick(comInstEventQueue[tid]->getCurTick()); 77111415SGeoffrey.Blake@arm.com} 77211415SGeoffrey.Blake@arm.com 77310529Smorr@cs.wisc.eduAddressMonitor::AddressMonitor() { 77410529Smorr@cs.wisc.edu armed = false; 77510529Smorr@cs.wisc.edu waiting = false; 77610529Smorr@cs.wisc.edu gotWakeup = false; 77710529Smorr@cs.wisc.edu} 77810529Smorr@cs.wisc.edu 77910529Smorr@cs.wisc.edubool AddressMonitor::doMonitor(PacketPtr pkt) { 78010529Smorr@cs.wisc.edu assert(pkt->req->hasPaddr()); 78111321Ssteve.reinhardt@amd.com if (armed && waiting) { 78211321Ssteve.reinhardt@amd.com if (pAddr == pkt->getAddr()) { 78310529Smorr@cs.wisc.edu DPRINTF(Mwait,"pAddr=0x%lx invalidated: waking up core\n", 78410529Smorr@cs.wisc.edu pkt->getAddr()); 78510529Smorr@cs.wisc.edu waiting = false; 78610529Smorr@cs.wisc.edu return true; 78710529Smorr@cs.wisc.edu } 78810529Smorr@cs.wisc.edu } 78910529Smorr@cs.wisc.edu return false; 79010529Smorr@cs.wisc.edu} 79110529Smorr@cs.wisc.edu 7929749Sandreas@sandberg.pp.sevoid 7939749Sandreas@sandberg.pp.seBaseCPU::scheduleLoadStop(ThreadID tid, Counter loads, const char *cause) 7949749Sandreas@sandberg.pp.se{ 7959749Sandreas@sandberg.pp.se const Tick now(comLoadEventQueue[tid]->getCurTick()); 7969983Sstever@gmail.com Event *event(new LocalSimLoopExitEvent(cause, 0)); 7979749Sandreas@sandberg.pp.se 7989749Sandreas@sandberg.pp.se comLoadEventQueue[tid]->schedule(event, now + loads); 7999749Sandreas@sandberg.pp.se} 8009749Sandreas@sandberg.pp.se 8019749Sandreas@sandberg.pp.se 8029749Sandreas@sandberg.pp.sevoid 8031191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 8041191SN/A{ 8051191SN/A if (!debugSymbolTable) 8061191SN/A return; 8071191SN/A 8081191SN/A // if pc enters different function, print new function symbol and 8091191SN/A // update saved range. Otherwise do nothing. 8101191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 8111191SN/A string sym_str; 8121191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 8131191SN/A currentFunctionStart, 8141191SN/A currentFunctionEnd); 8151191SN/A 8161191SN/A if (!found) { 8171191SN/A // no symbol found: use addr as label 8181191SN/A sym_str = csprintf("0x%x", pc); 8191191SN/A currentFunctionStart = pc; 8201191SN/A currentFunctionEnd = pc + 1; 8211191SN/A } 8221191SN/A 8231191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 8247823Ssteve.reinhardt@amd.com curTick() - functionEntryTick, curTick(), sym_str); 8257823Ssteve.reinhardt@amd.com functionEntryTick = curTick(); 8261191SN/A } 8271191SN/A} 82812122Sjose.marinho@arm.com 82912122Sjose.marinho@arm.combool 83012122Sjose.marinho@arm.comBaseCPU::waitForRemoteGDB() const 83112122Sjose.marinho@arm.com{ 83212122Sjose.marinho@arm.com return params()->wait_for_remote_gdb; 83312122Sjose.marinho@arm.com} 834