base.cc revision 10905
12SN/A/* 28922Swilliam.wang@arm.com * Copyright (c) 2011-2012 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 169983Sstever@gmail.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 179983Sstever@gmail.com * Copyright (c) 2013 Mark D. Hill and David A. Wood 182SN/A * All rights reserved. 192SN/A * 202SN/A * Redistribution and use in source and binary forms, with or without 212SN/A * modification, are permitted provided that the following conditions are 222SN/A * met: redistributions of source code must retain the above copyright 232SN/A * notice, this list of conditions and the following disclaimer; 242SN/A * redistributions in binary form must reproduce the above copyright 252SN/A * notice, this list of conditions and the following disclaimer in the 262SN/A * documentation and/or other materials provided with the distribution; 272SN/A * neither the name of the copyright holders nor the names of its 282SN/A * contributors may be used to endorse or promote products derived from 292SN/A * this software without specific prior written permission. 302SN/A * 312SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 322SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 332SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 342SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 352SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 362SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 372SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 382SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 392SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 402SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 412SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 422665Ssaidi@eecs.umich.edu * 432665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 442665Ssaidi@eecs.umich.edu * Nathan Binkert 457897Shestness@cs.utexas.edu * Rick Strong 462SN/A */ 472SN/A 481388SN/A#include <iostream> 498229Snate@binkert.org#include <sstream> 502SN/A#include <string> 512SN/A 527781SAli.Saidi@ARM.com#include "arch/tlb.hh" 538229Snate@binkert.org#include "base/loader/symtab.hh" 541191SN/A#include "base/cprintf.hh" 551191SN/A#include "base/misc.hh" 561388SN/A#include "base/output.hh" 575529Snate@binkert.org#include "base/trace.hh" 5810529Smorr@cs.wisc.edu#include "cpu/checker/cpu.hh" 591717SN/A#include "cpu/base.hh" 602651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 618229Snate@binkert.org#include "cpu/profile.hh" 622680Sktlim@umich.edu#include "cpu/thread_context.hh" 6310529Smorr@cs.wisc.edu#include "debug/Mwait.hh" 648232Snate@binkert.org#include "debug/SyscallVerbose.hh" 6510529Smorr@cs.wisc.edu#include "mem/page_table.hh" 665529Snate@binkert.org#include "params/BaseCPU.hh" 678779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 682190SN/A#include "sim/process.hh" 6956SN/A#include "sim/sim_events.hh" 708229Snate@binkert.org#include "sim/sim_exit.hh" 712190SN/A#include "sim/system.hh" 722SN/A 732359SN/A// Hack 742359SN/A#include "sim/stat_control.hh" 752359SN/A 762SN/Ausing namespace std; 772SN/A 782SN/Avector<BaseCPU *> BaseCPU::cpuList; 792SN/A 802SN/A// This variable reflects the max number of threads in any CPU. Be 812SN/A// careful to only use it once all the CPUs that you care about have 822SN/A// been initialized 832SN/Aint maxThreadsPerCPU = 1; 842SN/A 855606Snate@binkert.orgCPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 866144Sksewell@umich.edu : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 876144Sksewell@umich.edu cpu(_cpu), _repeatEvent(true) 883126Sktlim@umich.edu{ 896144Sksewell@umich.edu if (_interval) 907823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 913126Sktlim@umich.edu} 923126Sktlim@umich.edu 932356SN/Avoid 942356SN/ACPUProgressEvent::process() 952356SN/A{ 968834Satgutier@umich.edu Counter temp = cpu->totalOps(); 9710786Smalek.musleh@gmail.com 9810786Smalek.musleh@gmail.com if (_repeatEvent) 9910786Smalek.musleh@gmail.com cpu->schedule(this, curTick() + _interval); 10010786Smalek.musleh@gmail.com 10110786Smalek.musleh@gmail.com if(cpu->switchedOut()) { 10210786Smalek.musleh@gmail.com return; 10310786Smalek.musleh@gmail.com } 10410786Smalek.musleh@gmail.com 1052356SN/A#ifndef NDEBUG 1069179Sandreas.hansson@arm.com double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod()); 1072367SN/A 1086144Sksewell@umich.edu DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 1096144Sksewell@umich.edu "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 1106144Sksewell@umich.edu ipc); 1112356SN/A ipc = 0.0; 1122367SN/A#else 1136144Sksewell@umich.edu cprintf("%lli: %s progress event, total committed:%i, progress insts " 1147823Ssteve.reinhardt@amd.com "committed: %lli\n", curTick(), cpu->name(), temp, 1156144Sksewell@umich.edu temp - lastNumInst); 1162367SN/A#endif 1172356SN/A lastNumInst = temp; 1182356SN/A} 1192356SN/A 1202356SN/Aconst char * 1215336Shines@cs.fsu.eduCPUProgressEvent::description() const 1222356SN/A{ 1234873Sstever@eecs.umich.edu return "CPU Progress"; 1242356SN/A} 1252356SN/A 1268876Sandreas.hansson@arm.comBaseCPU::BaseCPU(Params *p, bool is_checker) 12710190Sakash.bagdia@arm.com : MemObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id), 1288832SAli.Saidi@ARM.com _instMasterId(p->system->getMasterId(name() + ".inst")), 1298832SAli.Saidi@ARM.com _dataMasterId(p->system->getMasterId(name() + ".data")), 1309332Sdam.sunwoo@arm.com _taskId(ContextSwitchTaskId::Unknown), _pid(Request::invldPid), 1319814Sandreas.hansson@arm.com _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()), 1329220Shestness@cs.wisc.edu interrupts(p->interrupts), profileEvent(NULL), 13310529Smorr@cs.wisc.edu numThreads(p->numThreads), system(p->system), 13410537Sandreas.hansson@arm.com functionTraceStream(nullptr), currentFunctionStart(0), 13510537Sandreas.hansson@arm.com currentFunctionEnd(0), functionEntryTick(0), 13610529Smorr@cs.wisc.edu addressMonitor() 1372SN/A{ 1385712Shsul@eecs.umich.edu // if Python did not provide a valid ID, do it here 1395712Shsul@eecs.umich.edu if (_cpuId == -1 ) { 1405712Shsul@eecs.umich.edu _cpuId = cpuList.size(); 1415712Shsul@eecs.umich.edu } 1425712Shsul@eecs.umich.edu 1432SN/A // add self to global list of CPUs 1442SN/A cpuList.push_back(this); 1452SN/A 14610190Sakash.bagdia@arm.com DPRINTF(SyscallVerbose, "Constructing CPU with id %d, socket id %d\n", 14710190Sakash.bagdia@arm.com _cpuId, _socketId); 1485712Shsul@eecs.umich.edu 1496221Snate@binkert.org if (numThreads > maxThreadsPerCPU) 1506221Snate@binkert.org maxThreadsPerCPU = numThreads; 1512SN/A 1522SN/A // allocate per-thread instruction-based event queues 1536221Snate@binkert.org comInstEventQueue = new EventQueue *[numThreads]; 1546221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1556221Snate@binkert.org comInstEventQueue[tid] = 1566221Snate@binkert.org new EventQueue("instruction-based event queue"); 1572SN/A 1582SN/A // 1592SN/A // set up instruction-count-based termination events, if any 1602SN/A // 1615606Snate@binkert.org if (p->max_insts_any_thread != 0) { 1625606Snate@binkert.org const char *cause = "a thread reached the max instruction count"; 1639749Sandreas@sandberg.pp.se for (ThreadID tid = 0; tid < numThreads; ++tid) 1649749Sandreas@sandberg.pp.se scheduleInstStop(tid, p->max_insts_any_thread, cause); 1655606Snate@binkert.org } 1662SN/A 1679647Sdam.sunwoo@arm.com // Set up instruction-count-based termination events for SimPoints 1689647Sdam.sunwoo@arm.com // Typically, there are more than one action points. 1699647Sdam.sunwoo@arm.com // Simulation.py is responsible to take the necessary actions upon 1709647Sdam.sunwoo@arm.com // exitting the simulation loop. 1719647Sdam.sunwoo@arm.com if (!p->simpoint_start_insts.empty()) { 1729647Sdam.sunwoo@arm.com const char *cause = "simpoint starting point found"; 1739749Sandreas@sandberg.pp.se for (size_t i = 0; i < p->simpoint_start_insts.size(); ++i) 1749749Sandreas@sandberg.pp.se scheduleInstStop(0, p->simpoint_start_insts[i], cause); 1759647Sdam.sunwoo@arm.com } 1769647Sdam.sunwoo@arm.com 1771400SN/A if (p->max_insts_all_threads != 0) { 1785606Snate@binkert.org const char *cause = "all threads reached the max instruction count"; 1795606Snate@binkert.org 1802SN/A // allocate & initialize shared downcounter: each event will 1812SN/A // decrement this when triggered; simulation will terminate 1822SN/A // when counter reaches 0 1832SN/A int *counter = new int; 1846221Snate@binkert.org *counter = numThreads; 1856221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1865606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1876670Shsul@eecs.umich.edu comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 1885606Snate@binkert.org } 1892SN/A } 1902SN/A 191124SN/A // allocate per-thread load-based event queues 1926221Snate@binkert.org comLoadEventQueue = new EventQueue *[numThreads]; 1936221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1946221Snate@binkert.org comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 195124SN/A 196124SN/A // 197124SN/A // set up instruction-count-based termination events, if any 198124SN/A // 1995606Snate@binkert.org if (p->max_loads_any_thread != 0) { 2005606Snate@binkert.org const char *cause = "a thread reached the max load count"; 2019749Sandreas@sandberg.pp.se for (ThreadID tid = 0; tid < numThreads; ++tid) 2029749Sandreas@sandberg.pp.se scheduleLoadStop(tid, p->max_loads_any_thread, cause); 2035606Snate@binkert.org } 204124SN/A 2051400SN/A if (p->max_loads_all_threads != 0) { 2065606Snate@binkert.org const char *cause = "all threads reached the max load count"; 207124SN/A // allocate & initialize shared downcounter: each event will 208124SN/A // decrement this when triggered; simulation will terminate 209124SN/A // when counter reaches 0 210124SN/A int *counter = new int; 2116221Snate@binkert.org *counter = numThreads; 2126221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 2135606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 2146221Snate@binkert.org comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 2155606Snate@binkert.org } 216124SN/A } 217124SN/A 2181191SN/A functionTracingEnabled = false; 2195529Snate@binkert.org if (p->function_trace) { 2208634Schris.emmons@arm.com const string fname = csprintf("ftrace.%s", name()); 2218634Schris.emmons@arm.com functionTraceStream = simout.find(fname); 2228634Schris.emmons@arm.com if (!functionTraceStream) 2238634Schris.emmons@arm.com functionTraceStream = simout.create(fname); 2248634Schris.emmons@arm.com 2251191SN/A currentFunctionStart = currentFunctionEnd = 0; 2265529Snate@binkert.org functionEntryTick = p->function_trace_start; 2271191SN/A 2285529Snate@binkert.org if (p->function_trace_start == 0) { 2291191SN/A functionTracingEnabled = true; 2301191SN/A } else { 2315606Snate@binkert.org typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap; 2325606Snate@binkert.org Event *event = new wrap(this, true); 2335606Snate@binkert.org schedule(event, p->function_trace_start); 2341191SN/A } 2351191SN/A } 2368876Sandreas.hansson@arm.com 2378876Sandreas.hansson@arm.com // The interrupts should always be present unless this CPU is 2388876Sandreas.hansson@arm.com // switched in later or in case it is a checker CPU 2399433SAndreas.Sandberg@ARM.com if (!params()->switched_out && !is_checker) { 2408876Sandreas.hansson@arm.com if (interrupts) { 2418876Sandreas.hansson@arm.com interrupts->setCPU(this); 2428876Sandreas.hansson@arm.com } else { 2438876Sandreas.hansson@arm.com fatal("CPU %s has no interrupt controller.\n" 2448876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 2458876Sandreas.hansson@arm.com } 2468876Sandreas.hansson@arm.com } 2475810Sgblack@eecs.umich.edu 2488779Sgblack@eecs.umich.edu if (FullSystem) { 2498779Sgblack@eecs.umich.edu if (params()->profile) 2508779Sgblack@eecs.umich.edu profileEvent = new ProfileEvent(this, params()->profile); 2518779Sgblack@eecs.umich.edu } 2525529Snate@binkert.org tracer = params()->tracer; 2539384SAndreas.Sandberg@arm.com 2549384SAndreas.Sandberg@arm.com if (params()->isa.size() != numThreads) { 2559384SAndreas.Sandberg@arm.com fatal("Number of ISAs (%i) assigned to the CPU does not equal number " 2569384SAndreas.Sandberg@arm.com "of threads (%i).\n", params()->isa.size(), numThreads); 2579384SAndreas.Sandberg@arm.com } 2581917SN/A} 2591191SN/A 2601191SN/Avoid 2611191SN/ABaseCPU::enableFunctionTrace() 2621191SN/A{ 2631191SN/A functionTracingEnabled = true; 2641191SN/A} 2651191SN/A 2661191SN/ABaseCPU::~BaseCPU() 2671191SN/A{ 2689086Sandreas.hansson@arm.com delete profileEvent; 2699086Sandreas.hansson@arm.com delete[] comLoadEventQueue; 2709086Sandreas.hansson@arm.com delete[] comInstEventQueue; 2711191SN/A} 2721191SN/A 2731129SN/Avoid 27410529Smorr@cs.wisc.eduBaseCPU::armMonitor(Addr address) 27510529Smorr@cs.wisc.edu{ 27610529Smorr@cs.wisc.edu addressMonitor.armed = true; 27710529Smorr@cs.wisc.edu addressMonitor.vAddr = address; 27810529Smorr@cs.wisc.edu addressMonitor.pAddr = 0x0; 27910529Smorr@cs.wisc.edu DPRINTF(Mwait,"Armed monitor (vAddr=0x%lx)\n", address); 28010529Smorr@cs.wisc.edu} 28110529Smorr@cs.wisc.edu 28210529Smorr@cs.wisc.edubool 28310529Smorr@cs.wisc.eduBaseCPU::mwait(PacketPtr pkt) 28410529Smorr@cs.wisc.edu{ 28510529Smorr@cs.wisc.edu if(addressMonitor.gotWakeup == false) { 28610529Smorr@cs.wisc.edu int block_size = cacheLineSize(); 28710529Smorr@cs.wisc.edu uint64_t mask = ~((uint64_t)(block_size - 1)); 28810529Smorr@cs.wisc.edu 28910529Smorr@cs.wisc.edu assert(pkt->req->hasPaddr()); 29010529Smorr@cs.wisc.edu addressMonitor.pAddr = pkt->getAddr() & mask; 29110529Smorr@cs.wisc.edu addressMonitor.waiting = true; 29210529Smorr@cs.wisc.edu 29310529Smorr@cs.wisc.edu DPRINTF(Mwait,"mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n", 29410529Smorr@cs.wisc.edu addressMonitor.vAddr, addressMonitor.pAddr); 29510529Smorr@cs.wisc.edu return true; 29610529Smorr@cs.wisc.edu } else { 29710529Smorr@cs.wisc.edu addressMonitor.gotWakeup = false; 29810529Smorr@cs.wisc.edu return false; 29910529Smorr@cs.wisc.edu } 30010529Smorr@cs.wisc.edu} 30110529Smorr@cs.wisc.edu 30210529Smorr@cs.wisc.eduvoid 30310529Smorr@cs.wisc.eduBaseCPU::mwaitAtomic(ThreadContext *tc, TheISA::TLB *dtb) 30410529Smorr@cs.wisc.edu{ 30510529Smorr@cs.wisc.edu Request req; 30610529Smorr@cs.wisc.edu Addr addr = addressMonitor.vAddr; 30710529Smorr@cs.wisc.edu int block_size = cacheLineSize(); 30810529Smorr@cs.wisc.edu uint64_t mask = ~((uint64_t)(block_size - 1)); 30910529Smorr@cs.wisc.edu int size = block_size; 31010529Smorr@cs.wisc.edu 31110529Smorr@cs.wisc.edu //The address of the next line if it crosses a cache line boundary. 31210529Smorr@cs.wisc.edu Addr secondAddr = roundDown(addr + size - 1, block_size); 31310529Smorr@cs.wisc.edu 31410529Smorr@cs.wisc.edu if (secondAddr > addr) 31510529Smorr@cs.wisc.edu size = secondAddr - addr; 31610529Smorr@cs.wisc.edu 31710529Smorr@cs.wisc.edu req.setVirt(0, addr, size, 0x0, dataMasterId(), tc->instAddr()); 31810529Smorr@cs.wisc.edu 31910529Smorr@cs.wisc.edu // translate to physical address 32010529Smorr@cs.wisc.edu Fault fault = dtb->translateAtomic(&req, tc, BaseTLB::Read); 32110529Smorr@cs.wisc.edu assert(fault == NoFault); 32210529Smorr@cs.wisc.edu 32310529Smorr@cs.wisc.edu addressMonitor.pAddr = req.getPaddr() & mask; 32410529Smorr@cs.wisc.edu addressMonitor.waiting = true; 32510529Smorr@cs.wisc.edu 32610529Smorr@cs.wisc.edu DPRINTF(Mwait,"mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n", 32710529Smorr@cs.wisc.edu addressMonitor.vAddr, addressMonitor.pAddr); 32810529Smorr@cs.wisc.edu} 32910529Smorr@cs.wisc.edu 33010529Smorr@cs.wisc.eduvoid 3311129SN/ABaseCPU::init() 3321129SN/A{ 3339523SAndreas.Sandberg@ARM.com if (!params()->switched_out) { 3342680Sktlim@umich.edu registerThreadContexts(); 3359523SAndreas.Sandberg@ARM.com 3369523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 3379523SAndreas.Sandberg@ARM.com } 3381129SN/A} 339180SN/A 3402SN/Avoid 3411917SN/ABaseCPU::startup() 3421917SN/A{ 3438779Sgblack@eecs.umich.edu if (FullSystem) { 3449433SAndreas.Sandberg@ARM.com if (!params()->switched_out && profileEvent) 3458779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 3468779Sgblack@eecs.umich.edu } 3472356SN/A 3485529Snate@binkert.org if (params()->progress_interval) { 3499179Sandreas.hansson@arm.com new CPUProgressEvent(this, params()->progress_interval); 3502356SN/A } 3511917SN/A} 3521917SN/A 35310464SAndreas.Sandberg@ARM.comProbePoints::PMUUPtr 35410464SAndreas.Sandberg@ARM.comBaseCPU::pmuProbePoint(const char *name) 35510464SAndreas.Sandberg@ARM.com{ 35610464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ptr; 35710464SAndreas.Sandberg@ARM.com ptr.reset(new ProbePoints::PMU(getProbeManager(), name)); 35810464SAndreas.Sandberg@ARM.com 35910464SAndreas.Sandberg@ARM.com return ptr; 36010464SAndreas.Sandberg@ARM.com} 36110464SAndreas.Sandberg@ARM.com 36210464SAndreas.Sandberg@ARM.comvoid 36310464SAndreas.Sandberg@ARM.comBaseCPU::regProbePoints() 36410464SAndreas.Sandberg@ARM.com{ 36510464SAndreas.Sandberg@ARM.com ppCycles = pmuProbePoint("Cycles"); 36610464SAndreas.Sandberg@ARM.com 36710464SAndreas.Sandberg@ARM.com ppRetiredInsts = pmuProbePoint("RetiredInsts"); 36810464SAndreas.Sandberg@ARM.com ppRetiredLoads = pmuProbePoint("RetiredLoads"); 36910464SAndreas.Sandberg@ARM.com ppRetiredStores = pmuProbePoint("RetiredStores"); 37010464SAndreas.Sandberg@ARM.com ppRetiredBranches = pmuProbePoint("RetiredBranches"); 37110464SAndreas.Sandberg@ARM.com} 37210464SAndreas.Sandberg@ARM.com 37310464SAndreas.Sandberg@ARM.comvoid 37410464SAndreas.Sandberg@ARM.comBaseCPU::probeInstCommit(const StaticInstPtr &inst) 37510464SAndreas.Sandberg@ARM.com{ 37610464SAndreas.Sandberg@ARM.com if (!inst->isMicroop() || inst->isLastMicroop()) 37710464SAndreas.Sandberg@ARM.com ppRetiredInsts->notify(1); 37810464SAndreas.Sandberg@ARM.com 37910464SAndreas.Sandberg@ARM.com 38010464SAndreas.Sandberg@ARM.com if (inst->isLoad()) 38110464SAndreas.Sandberg@ARM.com ppRetiredLoads->notify(1); 38210464SAndreas.Sandberg@ARM.com 38310464SAndreas.Sandberg@ARM.com if (inst->isStore()) 38410643Snikos.nikoleris@gmail.com ppRetiredStores->notify(1); 38510464SAndreas.Sandberg@ARM.com 38610464SAndreas.Sandberg@ARM.com if (inst->isControl()) 38710464SAndreas.Sandberg@ARM.com ppRetiredBranches->notify(1); 38810464SAndreas.Sandberg@ARM.com} 3891917SN/A 3901917SN/Avoid 3912SN/ABaseCPU::regStats() 3922SN/A{ 393729SN/A using namespace Stats; 394707SN/A 395707SN/A numCycles 396707SN/A .name(name() + ".numCycles") 397707SN/A .desc("number of cpu cycles simulated") 398707SN/A ; 399707SN/A 4007914SBrad.Beckmann@amd.com numWorkItemsStarted 4017914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsStarted") 4027914SBrad.Beckmann@amd.com .desc("number of work items this cpu started") 4037914SBrad.Beckmann@amd.com ; 4047914SBrad.Beckmann@amd.com 4057914SBrad.Beckmann@amd.com numWorkItemsCompleted 4067914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsCompleted") 4077914SBrad.Beckmann@amd.com .desc("number of work items this cpu completed") 4087914SBrad.Beckmann@amd.com ; 4097914SBrad.Beckmann@amd.com 4102680Sktlim@umich.edu int size = threadContexts.size(); 4112SN/A if (size > 1) { 4122SN/A for (int i = 0; i < size; ++i) { 4132SN/A stringstream namestr; 4142SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 4152680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 4162SN/A } 4172SN/A } else if (size == 1) 4182680Sktlim@umich.edu threadContexts[0]->regStats(name()); 4192SN/A} 4202SN/A 4219294Sandreas.hansson@arm.comBaseMasterPort & 4229294Sandreas.hansson@arm.comBaseCPU::getMasterPort(const string &if_name, PortID idx) 4238850Sandreas.hansson@arm.com{ 4248850Sandreas.hansson@arm.com // Get the right port based on name. This applies to all the 4258850Sandreas.hansson@arm.com // subclasses of the base CPU and relies on their implementation 4268850Sandreas.hansson@arm.com // of getDataPort and getInstPort. In all cases there methods 4279608Sandreas.hansson@arm.com // return a MasterPort pointer. 4288850Sandreas.hansson@arm.com if (if_name == "dcache_port") 4298922Swilliam.wang@arm.com return getDataPort(); 4308850Sandreas.hansson@arm.com else if (if_name == "icache_port") 4318922Swilliam.wang@arm.com return getInstPort(); 4328850Sandreas.hansson@arm.com else 4338922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 4348850Sandreas.hansson@arm.com} 4358850Sandreas.hansson@arm.com 436180SN/Avoid 4372680Sktlim@umich.eduBaseCPU::registerThreadContexts() 438180SN/A{ 4396221Snate@binkert.org ThreadID size = threadContexts.size(); 4406221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 4416221Snate@binkert.org ThreadContext *tc = threadContexts[tid]; 4422378SN/A 4435718Shsul@eecs.umich.edu /** This is so that contextId and cpuId match where there is a 4445718Shsul@eecs.umich.edu * 1cpu:1context relationship. Otherwise, the order of registration 4455718Shsul@eecs.umich.edu * could affect the assignment and cpu 1 could have context id 3, for 4465718Shsul@eecs.umich.edu * example. We may even want to do something like this for SMT so that 4475718Shsul@eecs.umich.edu * cpu 0 has the lowest thread contexts and cpu N has the highest, but 4485718Shsul@eecs.umich.edu * I'll just do this for now 4495718Shsul@eecs.umich.edu */ 4506221Snate@binkert.org if (numThreads == 1) 4515718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc, _cpuId)); 4525718Shsul@eecs.umich.edu else 4535718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc)); 4548779Sgblack@eecs.umich.edu 4558779Sgblack@eecs.umich.edu if (!FullSystem) 4568779Sgblack@eecs.umich.edu tc->getProcessPtr()->assignThreadContext(tc->contextId()); 457180SN/A } 458180SN/A} 459180SN/A 460180SN/A 4614000Ssaidi@eecs.umich.eduint 4624000Ssaidi@eecs.umich.eduBaseCPU::findContext(ThreadContext *tc) 4634000Ssaidi@eecs.umich.edu{ 4646221Snate@binkert.org ThreadID size = threadContexts.size(); 4656221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 4666221Snate@binkert.org if (tc == threadContexts[tid]) 4676221Snate@binkert.org return tid; 4684000Ssaidi@eecs.umich.edu } 4694000Ssaidi@eecs.umich.edu return 0; 4704000Ssaidi@eecs.umich.edu} 4714000Ssaidi@eecs.umich.edu 472180SN/Avoid 4732798Sktlim@umich.eduBaseCPU::switchOut() 474180SN/A{ 4759430SAndreas.Sandberg@ARM.com assert(!_switchedOut); 4769430SAndreas.Sandberg@ARM.com _switchedOut = true; 4772359SN/A if (profileEvent && profileEvent->scheduled()) 4785606Snate@binkert.org deschedule(profileEvent); 4799446SAndreas.Sandberg@ARM.com 4809446SAndreas.Sandberg@ARM.com // Flush all TLBs in the CPU to avoid having stale translations if 4819446SAndreas.Sandberg@ARM.com // it gets switched in later. 4829446SAndreas.Sandberg@ARM.com flushTLBs(); 483180SN/A} 484180SN/A 485180SN/Avoid 4868737Skoansin.tan@gmail.comBaseCPU::takeOverFrom(BaseCPU *oldCPU) 487180SN/A{ 4882680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 4899152Satgutier@umich.edu assert(_cpuId == oldCPU->cpuId()); 4909430SAndreas.Sandberg@ARM.com assert(_switchedOut); 4919430SAndreas.Sandberg@ARM.com assert(oldCPU != this); 4929332Sdam.sunwoo@arm.com _pid = oldCPU->getPid(); 4939332Sdam.sunwoo@arm.com _taskId = oldCPU->taskId(); 4949430SAndreas.Sandberg@ARM.com _switchedOut = false; 4955712Shsul@eecs.umich.edu 4966221Snate@binkert.org ThreadID size = threadContexts.size(); 4976221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 4982680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 4992680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 500180SN/A 5012680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 5022651Ssaidi@eecs.umich.edu 5032680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 5042651Ssaidi@eecs.umich.edu 5055714Shsul@eecs.umich.edu assert(newTC->contextId() == oldTC->contextId()); 5065715Shsul@eecs.umich.edu assert(newTC->threadId() == oldTC->threadId()); 5075714Shsul@eecs.umich.edu system->replaceThreadContext(newTC, newTC->contextId()); 5082359SN/A 5095875Ssteve.reinhardt@amd.com /* This code no longer works since the zero register (e.g., 5105875Ssteve.reinhardt@amd.com * r31 on Alpha) doesn't necessarily contain zero at this 5115875Ssteve.reinhardt@amd.com * point. 5125875Ssteve.reinhardt@amd.com if (DTRACE(Context)) 5135217Ssaidi@eecs.umich.edu ThreadContext::compare(oldTC, newTC); 5145875Ssteve.reinhardt@amd.com */ 5157781SAli.Saidi@ARM.com 5169294Sandreas.hansson@arm.com BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort(); 5179294Sandreas.hansson@arm.com BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort(); 5189294Sandreas.hansson@arm.com BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort(); 5199294Sandreas.hansson@arm.com BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort(); 5207781SAli.Saidi@ARM.com 5217781SAli.Saidi@ARM.com // Move over any table walker ports if they exist 5229178Sandreas.hansson@arm.com if (new_itb_port) { 5239178Sandreas.hansson@arm.com assert(!new_itb_port->isConnected()); 5247781SAli.Saidi@ARM.com assert(old_itb_port); 5259178Sandreas.hansson@arm.com assert(old_itb_port->isConnected()); 5269294Sandreas.hansson@arm.com BaseSlavePort &slavePort = old_itb_port->getSlavePort(); 5279178Sandreas.hansson@arm.com old_itb_port->unbind(); 5288922Swilliam.wang@arm.com new_itb_port->bind(slavePort); 5297781SAli.Saidi@ARM.com } 5309178Sandreas.hansson@arm.com if (new_dtb_port) { 5319178Sandreas.hansson@arm.com assert(!new_dtb_port->isConnected()); 5327781SAli.Saidi@ARM.com assert(old_dtb_port); 5339178Sandreas.hansson@arm.com assert(old_dtb_port->isConnected()); 5349294Sandreas.hansson@arm.com BaseSlavePort &slavePort = old_dtb_port->getSlavePort(); 5359178Sandreas.hansson@arm.com old_dtb_port->unbind(); 5368922Swilliam.wang@arm.com new_dtb_port->bind(slavePort); 5377781SAli.Saidi@ARM.com } 53810194SGeoffrey.Blake@arm.com newTC->getITBPtr()->takeOverFrom(oldTC->getITBPtr()); 53910194SGeoffrey.Blake@arm.com newTC->getDTBPtr()->takeOverFrom(oldTC->getDTBPtr()); 5408733Sgeoffrey.blake@arm.com 5418887Sgeoffrey.blake@arm.com // Checker whether or not we have to transfer CheckerCPU 5428887Sgeoffrey.blake@arm.com // objects over in the switch 5438887Sgeoffrey.blake@arm.com CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr(); 5448887Sgeoffrey.blake@arm.com CheckerCPU *newChecker = newTC->getCheckerCpuPtr(); 5458887Sgeoffrey.blake@arm.com if (oldChecker && newChecker) { 5469294Sandreas.hansson@arm.com BaseMasterPort *old_checker_itb_port = 5478922Swilliam.wang@arm.com oldChecker->getITBPtr()->getMasterPort(); 5489294Sandreas.hansson@arm.com BaseMasterPort *old_checker_dtb_port = 5498922Swilliam.wang@arm.com oldChecker->getDTBPtr()->getMasterPort(); 5509294Sandreas.hansson@arm.com BaseMasterPort *new_checker_itb_port = 5518922Swilliam.wang@arm.com newChecker->getITBPtr()->getMasterPort(); 5529294Sandreas.hansson@arm.com BaseMasterPort *new_checker_dtb_port = 5538922Swilliam.wang@arm.com newChecker->getDTBPtr()->getMasterPort(); 5548733Sgeoffrey.blake@arm.com 55510194SGeoffrey.Blake@arm.com newChecker->getITBPtr()->takeOverFrom(oldChecker->getITBPtr()); 55610194SGeoffrey.Blake@arm.com newChecker->getDTBPtr()->takeOverFrom(oldChecker->getDTBPtr()); 55710194SGeoffrey.Blake@arm.com 5588887Sgeoffrey.blake@arm.com // Move over any table walker ports if they exist for checker 5599178Sandreas.hansson@arm.com if (new_checker_itb_port) { 5609178Sandreas.hansson@arm.com assert(!new_checker_itb_port->isConnected()); 5618887Sgeoffrey.blake@arm.com assert(old_checker_itb_port); 5629178Sandreas.hansson@arm.com assert(old_checker_itb_port->isConnected()); 5639294Sandreas.hansson@arm.com BaseSlavePort &slavePort = 5649294Sandreas.hansson@arm.com old_checker_itb_port->getSlavePort(); 5659178Sandreas.hansson@arm.com old_checker_itb_port->unbind(); 5668922Swilliam.wang@arm.com new_checker_itb_port->bind(slavePort); 5678887Sgeoffrey.blake@arm.com } 5689178Sandreas.hansson@arm.com if (new_checker_dtb_port) { 5699178Sandreas.hansson@arm.com assert(!new_checker_dtb_port->isConnected()); 5708887Sgeoffrey.blake@arm.com assert(old_checker_dtb_port); 5719178Sandreas.hansson@arm.com assert(old_checker_dtb_port->isConnected()); 5729294Sandreas.hansson@arm.com BaseSlavePort &slavePort = 5739294Sandreas.hansson@arm.com old_checker_dtb_port->getSlavePort(); 5749178Sandreas.hansson@arm.com old_checker_dtb_port->unbind(); 5758922Swilliam.wang@arm.com new_checker_dtb_port->bind(slavePort); 5768887Sgeoffrey.blake@arm.com } 5778733Sgeoffrey.blake@arm.com } 578180SN/A } 579605SN/A 5803520Sgblack@eecs.umich.edu interrupts = oldCPU->interrupts; 5815810Sgblack@eecs.umich.edu interrupts->setCPU(this); 5829152Satgutier@umich.edu oldCPU->interrupts = NULL; 5832254SN/A 5848779Sgblack@eecs.umich.edu if (FullSystem) { 5858779Sgblack@eecs.umich.edu for (ThreadID i = 0; i < size; ++i) 5868779Sgblack@eecs.umich.edu threadContexts[i]->profileClear(); 5872254SN/A 5888779Sgblack@eecs.umich.edu if (profileEvent) 5898779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 5908779Sgblack@eecs.umich.edu } 5914192Sktlim@umich.edu 5929178Sandreas.hansson@arm.com // All CPUs have an instruction and a data port, and the new CPU's 5939178Sandreas.hansson@arm.com // ports are dangling while the old CPU has its ports connected 5949178Sandreas.hansson@arm.com // already. Unbind the old CPU and then bind the ports of the one 5959178Sandreas.hansson@arm.com // we are switching to. 5969178Sandreas.hansson@arm.com assert(!getInstPort().isConnected()); 5979178Sandreas.hansson@arm.com assert(oldCPU->getInstPort().isConnected()); 5989294Sandreas.hansson@arm.com BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort(); 5999178Sandreas.hansson@arm.com oldCPU->getInstPort().unbind(); 6009178Sandreas.hansson@arm.com getInstPort().bind(inst_peer_port); 6014192Sktlim@umich.edu 6029178Sandreas.hansson@arm.com assert(!getDataPort().isConnected()); 6039178Sandreas.hansson@arm.com assert(oldCPU->getDataPort().isConnected()); 6049294Sandreas.hansson@arm.com BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort(); 6059178Sandreas.hansson@arm.com oldCPU->getDataPort().unbind(); 6069178Sandreas.hansson@arm.com getDataPort().bind(data_peer_port); 607180SN/A} 608180SN/A 6099446SAndreas.Sandberg@ARM.comvoid 6109446SAndreas.Sandberg@ARM.comBaseCPU::flushTLBs() 6119446SAndreas.Sandberg@ARM.com{ 6129446SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < threadContexts.size(); ++i) { 6139446SAndreas.Sandberg@ARM.com ThreadContext &tc(*threadContexts[i]); 6149446SAndreas.Sandberg@ARM.com CheckerCPU *checker(tc.getCheckerCpuPtr()); 6159446SAndreas.Sandberg@ARM.com 6169446SAndreas.Sandberg@ARM.com tc.getITBPtr()->flushAll(); 6179446SAndreas.Sandberg@ARM.com tc.getDTBPtr()->flushAll(); 6189446SAndreas.Sandberg@ARM.com if (checker) { 6199446SAndreas.Sandberg@ARM.com checker->getITBPtr()->flushAll(); 6209446SAndreas.Sandberg@ARM.com checker->getDTBPtr()->flushAll(); 6219446SAndreas.Sandberg@ARM.com } 6229446SAndreas.Sandberg@ARM.com } 6239446SAndreas.Sandberg@ARM.com} 6249446SAndreas.Sandberg@ARM.com 625180SN/A 6265536Srstrong@hp.comBaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval) 6275606Snate@binkert.org : cpu(_cpu), interval(_interval) 6281917SN/A{ } 6291917SN/A 6301917SN/Avoid 6311917SN/ABaseCPU::ProfileEvent::process() 6321917SN/A{ 6336221Snate@binkert.org ThreadID size = cpu->threadContexts.size(); 6346221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 6352680Sktlim@umich.edu ThreadContext *tc = cpu->threadContexts[i]; 6362680Sktlim@umich.edu tc->profileSample(); 6371917SN/A } 6382254SN/A 6397823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + interval); 6401917SN/A} 6411917SN/A 6422SN/Avoid 64310905Sandreas.sandberg@arm.comBaseCPU::serialize(CheckpointOut &cp) const 644921SN/A{ 6454000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(instCnt); 6469332Sdam.sunwoo@arm.com 6479448SAndreas.Sandberg@ARM.com if (!_switchedOut) { 6489448SAndreas.Sandberg@ARM.com /* Unlike _pid, _taskId is not serialized, as they are dynamically 6499448SAndreas.Sandberg@ARM.com * assigned unique ids that are only meaningful for the duration of 6509448SAndreas.Sandberg@ARM.com * a specific run. We will need to serialize the entire taskMap in 6519448SAndreas.Sandberg@ARM.com * system. */ 6529448SAndreas.Sandberg@ARM.com SERIALIZE_SCALAR(_pid); 6539332Sdam.sunwoo@arm.com 65410905Sandreas.sandberg@arm.com interrupts->serialize(cp); 6559448SAndreas.Sandberg@ARM.com 6569448SAndreas.Sandberg@ARM.com // Serialize the threads, this is done by the CPU implementation. 6579448SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < numThreads; ++i) { 65810905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("xc.%i", i)); 65910905Sandreas.sandberg@arm.com serializeThread(cp, i); 6609448SAndreas.Sandberg@ARM.com } 6619448SAndreas.Sandberg@ARM.com } 662921SN/A} 663921SN/A 664921SN/Avoid 66510905Sandreas.sandberg@arm.comBaseCPU::unserialize(CheckpointIn &cp) 666921SN/A{ 6674000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(instCnt); 6689448SAndreas.Sandberg@ARM.com 6699448SAndreas.Sandberg@ARM.com if (!_switchedOut) { 6709448SAndreas.Sandberg@ARM.com UNSERIALIZE_SCALAR(_pid); 67110905Sandreas.sandberg@arm.com interrupts->unserialize(cp); 6729448SAndreas.Sandberg@ARM.com 6739448SAndreas.Sandberg@ARM.com // Unserialize the threads, this is done by the CPU implementation. 67410905Sandreas.sandberg@arm.com for (ThreadID i = 0; i < numThreads; ++i) { 67510905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("xc.%i", i)); 67610905Sandreas.sandberg@arm.com unserializeThread(cp, i); 67710905Sandreas.sandberg@arm.com } 6789448SAndreas.Sandberg@ARM.com } 679921SN/A} 680921SN/A 6811191SN/Avoid 6829749Sandreas@sandberg.pp.seBaseCPU::scheduleInstStop(ThreadID tid, Counter insts, const char *cause) 6839749Sandreas@sandberg.pp.se{ 6849749Sandreas@sandberg.pp.se const Tick now(comInstEventQueue[tid]->getCurTick()); 6859983Sstever@gmail.com Event *event(new LocalSimLoopExitEvent(cause, 0)); 6869749Sandreas@sandberg.pp.se 6879749Sandreas@sandberg.pp.se comInstEventQueue[tid]->schedule(event, now + insts); 6889749Sandreas@sandberg.pp.se} 6899749Sandreas@sandberg.pp.se 69010529Smorr@cs.wisc.eduAddressMonitor::AddressMonitor() { 69110529Smorr@cs.wisc.edu armed = false; 69210529Smorr@cs.wisc.edu waiting = false; 69310529Smorr@cs.wisc.edu gotWakeup = false; 69410529Smorr@cs.wisc.edu} 69510529Smorr@cs.wisc.edu 69610529Smorr@cs.wisc.edubool AddressMonitor::doMonitor(PacketPtr pkt) { 69710529Smorr@cs.wisc.edu assert(pkt->req->hasPaddr()); 69810529Smorr@cs.wisc.edu if(armed && waiting) { 69910529Smorr@cs.wisc.edu if(pAddr == pkt->getAddr()) { 70010529Smorr@cs.wisc.edu DPRINTF(Mwait,"pAddr=0x%lx invalidated: waking up core\n", 70110529Smorr@cs.wisc.edu pkt->getAddr()); 70210529Smorr@cs.wisc.edu waiting = false; 70310529Smorr@cs.wisc.edu return true; 70410529Smorr@cs.wisc.edu } 70510529Smorr@cs.wisc.edu } 70610529Smorr@cs.wisc.edu return false; 70710529Smorr@cs.wisc.edu} 70810529Smorr@cs.wisc.edu 7099749Sandreas@sandberg.pp.sevoid 7109749Sandreas@sandberg.pp.seBaseCPU::scheduleLoadStop(ThreadID tid, Counter loads, const char *cause) 7119749Sandreas@sandberg.pp.se{ 7129749Sandreas@sandberg.pp.se const Tick now(comLoadEventQueue[tid]->getCurTick()); 7139983Sstever@gmail.com Event *event(new LocalSimLoopExitEvent(cause, 0)); 7149749Sandreas@sandberg.pp.se 7159749Sandreas@sandberg.pp.se comLoadEventQueue[tid]->schedule(event, now + loads); 7169749Sandreas@sandberg.pp.se} 7179749Sandreas@sandberg.pp.se 7189749Sandreas@sandberg.pp.se 7199749Sandreas@sandberg.pp.sevoid 7201191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 7211191SN/A{ 7221191SN/A if (!debugSymbolTable) 7231191SN/A return; 7241191SN/A 7251191SN/A // if pc enters different function, print new function symbol and 7261191SN/A // update saved range. Otherwise do nothing. 7271191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 7281191SN/A string sym_str; 7291191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 7301191SN/A currentFunctionStart, 7311191SN/A currentFunctionEnd); 7321191SN/A 7331191SN/A if (!found) { 7341191SN/A // no symbol found: use addr as label 7351191SN/A sym_str = csprintf("0x%x", pc); 7361191SN/A currentFunctionStart = pc; 7371191SN/A currentFunctionEnd = pc + 1; 7381191SN/A } 7391191SN/A 7401191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 7417823Ssteve.reinhardt@amd.com curTick() - functionEntryTick, curTick(), sym_str); 7427823Ssteve.reinhardt@amd.com functionEntryTick = curTick(); 7431191SN/A } 7441191SN/A} 745