base.cc revision 10194
12SN/A/* 28922Swilliam.wang@arm.com * Copyright (c) 2011-2012 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 169983Sstever@gmail.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 179983Sstever@gmail.com * Copyright (c) 2013 Mark D. Hill and David A. Wood 182SN/A * All rights reserved. 192SN/A * 202SN/A * Redistribution and use in source and binary forms, with or without 212SN/A * modification, are permitted provided that the following conditions are 222SN/A * met: redistributions of source code must retain the above copyright 232SN/A * notice, this list of conditions and the following disclaimer; 242SN/A * redistributions in binary form must reproduce the above copyright 252SN/A * notice, this list of conditions and the following disclaimer in the 262SN/A * documentation and/or other materials provided with the distribution; 272SN/A * neither the name of the copyright holders nor the names of its 282SN/A * contributors may be used to endorse or promote products derived from 292SN/A * this software without specific prior written permission. 302SN/A * 312SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 322SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 332SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 342SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 352SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 362SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 372SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 382SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 392SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 402SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 412SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 422665Ssaidi@eecs.umich.edu * 432665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 442665Ssaidi@eecs.umich.edu * Nathan Binkert 457897Shestness@cs.utexas.edu * Rick Strong 462SN/A */ 472SN/A 481388SN/A#include <iostream> 498229Snate@binkert.org#include <sstream> 502SN/A#include <string> 512SN/A 527781SAli.Saidi@ARM.com#include "arch/tlb.hh" 538229Snate@binkert.org#include "base/loader/symtab.hh" 541191SN/A#include "base/cprintf.hh" 551191SN/A#include "base/misc.hh" 561388SN/A#include "base/output.hh" 575529Snate@binkert.org#include "base/trace.hh" 581717SN/A#include "cpu/base.hh" 598887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 602651Ssaidi@eecs.umich.edu#include "cpu/cpuevent.hh" 618229Snate@binkert.org#include "cpu/profile.hh" 622680Sktlim@umich.edu#include "cpu/thread_context.hh" 638232Snate@binkert.org#include "debug/SyscallVerbose.hh" 645529Snate@binkert.org#include "params/BaseCPU.hh" 658779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 662190SN/A#include "sim/process.hh" 6756SN/A#include "sim/sim_events.hh" 688229Snate@binkert.org#include "sim/sim_exit.hh" 692190SN/A#include "sim/system.hh" 702SN/A 712359SN/A// Hack 722359SN/A#include "sim/stat_control.hh" 732359SN/A 742SN/Ausing namespace std; 752SN/A 762SN/Avector<BaseCPU *> BaseCPU::cpuList; 772SN/A 782SN/A// This variable reflects the max number of threads in any CPU. Be 792SN/A// careful to only use it once all the CPUs that you care about have 802SN/A// been initialized 812SN/Aint maxThreadsPerCPU = 1; 822SN/A 835606Snate@binkert.orgCPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) 846144Sksewell@umich.edu : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0), 856144Sksewell@umich.edu cpu(_cpu), _repeatEvent(true) 863126Sktlim@umich.edu{ 876144Sksewell@umich.edu if (_interval) 887823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 893126Sktlim@umich.edu} 903126Sktlim@umich.edu 912356SN/Avoid 922356SN/ACPUProgressEvent::process() 932356SN/A{ 948834Satgutier@umich.edu Counter temp = cpu->totalOps(); 952356SN/A#ifndef NDEBUG 969179Sandreas.hansson@arm.com double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod()); 972367SN/A 986144Sksewell@umich.edu DPRINTFN("%s progress event, total committed:%i, progress insts committed: " 996144Sksewell@umich.edu "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst, 1006144Sksewell@umich.edu ipc); 1012356SN/A ipc = 0.0; 1022367SN/A#else 1036144Sksewell@umich.edu cprintf("%lli: %s progress event, total committed:%i, progress insts " 1047823Ssteve.reinhardt@amd.com "committed: %lli\n", curTick(), cpu->name(), temp, 1056144Sksewell@umich.edu temp - lastNumInst); 1062367SN/A#endif 1072356SN/A lastNumInst = temp; 1086144Sksewell@umich.edu 1096144Sksewell@umich.edu if (_repeatEvent) 1107823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + _interval); 1112356SN/A} 1122356SN/A 1132356SN/Aconst char * 1145336Shines@cs.fsu.eduCPUProgressEvent::description() const 1152356SN/A{ 1164873Sstever@eecs.umich.edu return "CPU Progress"; 1172356SN/A} 1182356SN/A 1198876Sandreas.hansson@arm.comBaseCPU::BaseCPU(Params *p, bool is_checker) 12010190Sakash.bagdia@arm.com : MemObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id), 1218832SAli.Saidi@ARM.com _instMasterId(p->system->getMasterId(name() + ".inst")), 1228832SAli.Saidi@ARM.com _dataMasterId(p->system->getMasterId(name() + ".data")), 1239332Sdam.sunwoo@arm.com _taskId(ContextSwitchTaskId::Unknown), _pid(Request::invldPid), 1249814Sandreas.hansson@arm.com _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()), 1259220Shestness@cs.wisc.edu interrupts(p->interrupts), profileEvent(NULL), 1269157Sandreas.hansson@arm.com numThreads(p->numThreads), system(p->system) 1272SN/A{ 1285712Shsul@eecs.umich.edu // if Python did not provide a valid ID, do it here 1295712Shsul@eecs.umich.edu if (_cpuId == -1 ) { 1305712Shsul@eecs.umich.edu _cpuId = cpuList.size(); 1315712Shsul@eecs.umich.edu } 1325712Shsul@eecs.umich.edu 1332SN/A // add self to global list of CPUs 1342SN/A cpuList.push_back(this); 1352SN/A 13610190Sakash.bagdia@arm.com DPRINTF(SyscallVerbose, "Constructing CPU with id %d, socket id %d\n", 13710190Sakash.bagdia@arm.com _cpuId, _socketId); 1385712Shsul@eecs.umich.edu 1396221Snate@binkert.org if (numThreads > maxThreadsPerCPU) 1406221Snate@binkert.org maxThreadsPerCPU = numThreads; 1412SN/A 1422SN/A // allocate per-thread instruction-based event queues 1436221Snate@binkert.org comInstEventQueue = new EventQueue *[numThreads]; 1446221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1456221Snate@binkert.org comInstEventQueue[tid] = 1466221Snate@binkert.org new EventQueue("instruction-based event queue"); 1472SN/A 1482SN/A // 1492SN/A // set up instruction-count-based termination events, if any 1502SN/A // 1515606Snate@binkert.org if (p->max_insts_any_thread != 0) { 1525606Snate@binkert.org const char *cause = "a thread reached the max instruction count"; 1539749Sandreas@sandberg.pp.se for (ThreadID tid = 0; tid < numThreads; ++tid) 1549749Sandreas@sandberg.pp.se scheduleInstStop(tid, p->max_insts_any_thread, cause); 1555606Snate@binkert.org } 1562SN/A 1579647Sdam.sunwoo@arm.com // Set up instruction-count-based termination events for SimPoints 1589647Sdam.sunwoo@arm.com // Typically, there are more than one action points. 1599647Sdam.sunwoo@arm.com // Simulation.py is responsible to take the necessary actions upon 1609647Sdam.sunwoo@arm.com // exitting the simulation loop. 1619647Sdam.sunwoo@arm.com if (!p->simpoint_start_insts.empty()) { 1629647Sdam.sunwoo@arm.com const char *cause = "simpoint starting point found"; 1639749Sandreas@sandberg.pp.se for (size_t i = 0; i < p->simpoint_start_insts.size(); ++i) 1649749Sandreas@sandberg.pp.se scheduleInstStop(0, p->simpoint_start_insts[i], cause); 1659647Sdam.sunwoo@arm.com } 1669647Sdam.sunwoo@arm.com 1671400SN/A if (p->max_insts_all_threads != 0) { 1685606Snate@binkert.org const char *cause = "all threads reached the max instruction count"; 1695606Snate@binkert.org 1702SN/A // allocate & initialize shared downcounter: each event will 1712SN/A // decrement this when triggered; simulation will terminate 1722SN/A // when counter reaches 0 1732SN/A int *counter = new int; 1746221Snate@binkert.org *counter = numThreads; 1756221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1765606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 1776670Shsul@eecs.umich.edu comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads); 1785606Snate@binkert.org } 1792SN/A } 1802SN/A 181124SN/A // allocate per-thread load-based event queues 1826221Snate@binkert.org comLoadEventQueue = new EventQueue *[numThreads]; 1836221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 1846221Snate@binkert.org comLoadEventQueue[tid] = new EventQueue("load-based event queue"); 185124SN/A 186124SN/A // 187124SN/A // set up instruction-count-based termination events, if any 188124SN/A // 1895606Snate@binkert.org if (p->max_loads_any_thread != 0) { 1905606Snate@binkert.org const char *cause = "a thread reached the max load count"; 1919749Sandreas@sandberg.pp.se for (ThreadID tid = 0; tid < numThreads; ++tid) 1929749Sandreas@sandberg.pp.se scheduleLoadStop(tid, p->max_loads_any_thread, cause); 1935606Snate@binkert.org } 194124SN/A 1951400SN/A if (p->max_loads_all_threads != 0) { 1965606Snate@binkert.org const char *cause = "all threads reached the max load count"; 197124SN/A // allocate & initialize shared downcounter: each event will 198124SN/A // decrement this when triggered; simulation will terminate 199124SN/A // when counter reaches 0 200124SN/A int *counter = new int; 2016221Snate@binkert.org *counter = numThreads; 2026221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 2035606Snate@binkert.org Event *event = new CountedExitEvent(cause, *counter); 2046221Snate@binkert.org comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads); 2055606Snate@binkert.org } 206124SN/A } 207124SN/A 2081191SN/A functionTracingEnabled = false; 2095529Snate@binkert.org if (p->function_trace) { 2108634Schris.emmons@arm.com const string fname = csprintf("ftrace.%s", name()); 2118634Schris.emmons@arm.com functionTraceStream = simout.find(fname); 2128634Schris.emmons@arm.com if (!functionTraceStream) 2138634Schris.emmons@arm.com functionTraceStream = simout.create(fname); 2148634Schris.emmons@arm.com 2151191SN/A currentFunctionStart = currentFunctionEnd = 0; 2165529Snate@binkert.org functionEntryTick = p->function_trace_start; 2171191SN/A 2185529Snate@binkert.org if (p->function_trace_start == 0) { 2191191SN/A functionTracingEnabled = true; 2201191SN/A } else { 2215606Snate@binkert.org typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap; 2225606Snate@binkert.org Event *event = new wrap(this, true); 2235606Snate@binkert.org schedule(event, p->function_trace_start); 2241191SN/A } 2251191SN/A } 2268876Sandreas.hansson@arm.com 2278876Sandreas.hansson@arm.com // The interrupts should always be present unless this CPU is 2288876Sandreas.hansson@arm.com // switched in later or in case it is a checker CPU 2299433SAndreas.Sandberg@ARM.com if (!params()->switched_out && !is_checker) { 2308876Sandreas.hansson@arm.com if (interrupts) { 2318876Sandreas.hansson@arm.com interrupts->setCPU(this); 2328876Sandreas.hansson@arm.com } else { 2338876Sandreas.hansson@arm.com fatal("CPU %s has no interrupt controller.\n" 2348876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 2358876Sandreas.hansson@arm.com } 2368876Sandreas.hansson@arm.com } 2375810Sgblack@eecs.umich.edu 2388779Sgblack@eecs.umich.edu if (FullSystem) { 2398779Sgblack@eecs.umich.edu if (params()->profile) 2408779Sgblack@eecs.umich.edu profileEvent = new ProfileEvent(this, params()->profile); 2418779Sgblack@eecs.umich.edu } 2425529Snate@binkert.org tracer = params()->tracer; 2439384SAndreas.Sandberg@arm.com 2449384SAndreas.Sandberg@arm.com if (params()->isa.size() != numThreads) { 2459384SAndreas.Sandberg@arm.com fatal("Number of ISAs (%i) assigned to the CPU does not equal number " 2469384SAndreas.Sandberg@arm.com "of threads (%i).\n", params()->isa.size(), numThreads); 2479384SAndreas.Sandberg@arm.com } 2481917SN/A} 2491191SN/A 2501191SN/Avoid 2511191SN/ABaseCPU::enableFunctionTrace() 2521191SN/A{ 2531191SN/A functionTracingEnabled = true; 2541191SN/A} 2551191SN/A 2561191SN/ABaseCPU::~BaseCPU() 2571191SN/A{ 2589086Sandreas.hansson@arm.com delete profileEvent; 2599086Sandreas.hansson@arm.com delete[] comLoadEventQueue; 2609086Sandreas.hansson@arm.com delete[] comInstEventQueue; 2611191SN/A} 2621191SN/A 2631129SN/Avoid 2641129SN/ABaseCPU::init() 2651129SN/A{ 2669523SAndreas.Sandberg@ARM.com if (!params()->switched_out) { 2672680Sktlim@umich.edu registerThreadContexts(); 2689523SAndreas.Sandberg@ARM.com 2699523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 2709523SAndreas.Sandberg@ARM.com } 2711129SN/A} 272180SN/A 2732SN/Avoid 2741917SN/ABaseCPU::startup() 2751917SN/A{ 2768779Sgblack@eecs.umich.edu if (FullSystem) { 2779433SAndreas.Sandberg@ARM.com if (!params()->switched_out && profileEvent) 2788779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 2798779Sgblack@eecs.umich.edu } 2802356SN/A 2815529Snate@binkert.org if (params()->progress_interval) { 2829179Sandreas.hansson@arm.com new CPUProgressEvent(this, params()->progress_interval); 2832356SN/A } 2841917SN/A} 2851917SN/A 2861917SN/A 2871917SN/Avoid 2882SN/ABaseCPU::regStats() 2892SN/A{ 290729SN/A using namespace Stats; 291707SN/A 292707SN/A numCycles 293707SN/A .name(name() + ".numCycles") 294707SN/A .desc("number of cpu cycles simulated") 295707SN/A ; 296707SN/A 2977914SBrad.Beckmann@amd.com numWorkItemsStarted 2987914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsStarted") 2997914SBrad.Beckmann@amd.com .desc("number of work items this cpu started") 3007914SBrad.Beckmann@amd.com ; 3017914SBrad.Beckmann@amd.com 3027914SBrad.Beckmann@amd.com numWorkItemsCompleted 3037914SBrad.Beckmann@amd.com .name(name() + ".numWorkItemsCompleted") 3047914SBrad.Beckmann@amd.com .desc("number of work items this cpu completed") 3057914SBrad.Beckmann@amd.com ; 3067914SBrad.Beckmann@amd.com 3072680Sktlim@umich.edu int size = threadContexts.size(); 3082SN/A if (size > 1) { 3092SN/A for (int i = 0; i < size; ++i) { 3102SN/A stringstream namestr; 3112SN/A ccprintf(namestr, "%s.ctx%d", name(), i); 3122680Sktlim@umich.edu threadContexts[i]->regStats(namestr.str()); 3132SN/A } 3142SN/A } else if (size == 1) 3152680Sktlim@umich.edu threadContexts[0]->regStats(name()); 3162SN/A} 3172SN/A 3189294Sandreas.hansson@arm.comBaseMasterPort & 3199294Sandreas.hansson@arm.comBaseCPU::getMasterPort(const string &if_name, PortID idx) 3208850Sandreas.hansson@arm.com{ 3218850Sandreas.hansson@arm.com // Get the right port based on name. This applies to all the 3228850Sandreas.hansson@arm.com // subclasses of the base CPU and relies on their implementation 3238850Sandreas.hansson@arm.com // of getDataPort and getInstPort. In all cases there methods 3249608Sandreas.hansson@arm.com // return a MasterPort pointer. 3258850Sandreas.hansson@arm.com if (if_name == "dcache_port") 3268922Swilliam.wang@arm.com return getDataPort(); 3278850Sandreas.hansson@arm.com else if (if_name == "icache_port") 3288922Swilliam.wang@arm.com return getInstPort(); 3298850Sandreas.hansson@arm.com else 3308922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 3318850Sandreas.hansson@arm.com} 3328850Sandreas.hansson@arm.com 333180SN/Avoid 3342680Sktlim@umich.eduBaseCPU::registerThreadContexts() 335180SN/A{ 3366221Snate@binkert.org ThreadID size = threadContexts.size(); 3376221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 3386221Snate@binkert.org ThreadContext *tc = threadContexts[tid]; 3392378SN/A 3405718Shsul@eecs.umich.edu /** This is so that contextId and cpuId match where there is a 3415718Shsul@eecs.umich.edu * 1cpu:1context relationship. Otherwise, the order of registration 3425718Shsul@eecs.umich.edu * could affect the assignment and cpu 1 could have context id 3, for 3435718Shsul@eecs.umich.edu * example. We may even want to do something like this for SMT so that 3445718Shsul@eecs.umich.edu * cpu 0 has the lowest thread contexts and cpu N has the highest, but 3455718Shsul@eecs.umich.edu * I'll just do this for now 3465718Shsul@eecs.umich.edu */ 3476221Snate@binkert.org if (numThreads == 1) 3485718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc, _cpuId)); 3495718Shsul@eecs.umich.edu else 3505718Shsul@eecs.umich.edu tc->setContextId(system->registerThreadContext(tc)); 3518779Sgblack@eecs.umich.edu 3528779Sgblack@eecs.umich.edu if (!FullSystem) 3538779Sgblack@eecs.umich.edu tc->getProcessPtr()->assignThreadContext(tc->contextId()); 354180SN/A } 355180SN/A} 356180SN/A 357180SN/A 3584000Ssaidi@eecs.umich.eduint 3594000Ssaidi@eecs.umich.eduBaseCPU::findContext(ThreadContext *tc) 3604000Ssaidi@eecs.umich.edu{ 3616221Snate@binkert.org ThreadID size = threadContexts.size(); 3626221Snate@binkert.org for (ThreadID tid = 0; tid < size; ++tid) { 3636221Snate@binkert.org if (tc == threadContexts[tid]) 3646221Snate@binkert.org return tid; 3654000Ssaidi@eecs.umich.edu } 3664000Ssaidi@eecs.umich.edu return 0; 3674000Ssaidi@eecs.umich.edu} 3684000Ssaidi@eecs.umich.edu 369180SN/Avoid 3702798Sktlim@umich.eduBaseCPU::switchOut() 371180SN/A{ 3729430SAndreas.Sandberg@ARM.com assert(!_switchedOut); 3739430SAndreas.Sandberg@ARM.com _switchedOut = true; 3742359SN/A if (profileEvent && profileEvent->scheduled()) 3755606Snate@binkert.org deschedule(profileEvent); 3769446SAndreas.Sandberg@ARM.com 3779446SAndreas.Sandberg@ARM.com // Flush all TLBs in the CPU to avoid having stale translations if 3789446SAndreas.Sandberg@ARM.com // it gets switched in later. 3799446SAndreas.Sandberg@ARM.com flushTLBs(); 380180SN/A} 381180SN/A 382180SN/Avoid 3838737Skoansin.tan@gmail.comBaseCPU::takeOverFrom(BaseCPU *oldCPU) 384180SN/A{ 3852680Sktlim@umich.edu assert(threadContexts.size() == oldCPU->threadContexts.size()); 3869152Satgutier@umich.edu assert(_cpuId == oldCPU->cpuId()); 3879430SAndreas.Sandberg@ARM.com assert(_switchedOut); 3889430SAndreas.Sandberg@ARM.com assert(oldCPU != this); 3899332Sdam.sunwoo@arm.com _pid = oldCPU->getPid(); 3909332Sdam.sunwoo@arm.com _taskId = oldCPU->taskId(); 3919430SAndreas.Sandberg@ARM.com _switchedOut = false; 3925712Shsul@eecs.umich.edu 3936221Snate@binkert.org ThreadID size = threadContexts.size(); 3946221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 3952680Sktlim@umich.edu ThreadContext *newTC = threadContexts[i]; 3962680Sktlim@umich.edu ThreadContext *oldTC = oldCPU->threadContexts[i]; 397180SN/A 3982680Sktlim@umich.edu newTC->takeOverFrom(oldTC); 3992651Ssaidi@eecs.umich.edu 4002680Sktlim@umich.edu CpuEvent::replaceThreadContext(oldTC, newTC); 4012651Ssaidi@eecs.umich.edu 4025714Shsul@eecs.umich.edu assert(newTC->contextId() == oldTC->contextId()); 4035715Shsul@eecs.umich.edu assert(newTC->threadId() == oldTC->threadId()); 4045714Shsul@eecs.umich.edu system->replaceThreadContext(newTC, newTC->contextId()); 4052359SN/A 4065875Ssteve.reinhardt@amd.com /* This code no longer works since the zero register (e.g., 4075875Ssteve.reinhardt@amd.com * r31 on Alpha) doesn't necessarily contain zero at this 4085875Ssteve.reinhardt@amd.com * point. 4095875Ssteve.reinhardt@amd.com if (DTRACE(Context)) 4105217Ssaidi@eecs.umich.edu ThreadContext::compare(oldTC, newTC); 4115875Ssteve.reinhardt@amd.com */ 4127781SAli.Saidi@ARM.com 4139294Sandreas.hansson@arm.com BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort(); 4149294Sandreas.hansson@arm.com BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort(); 4159294Sandreas.hansson@arm.com BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort(); 4169294Sandreas.hansson@arm.com BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort(); 4177781SAli.Saidi@ARM.com 4187781SAli.Saidi@ARM.com // Move over any table walker ports if they exist 4199178Sandreas.hansson@arm.com if (new_itb_port) { 4209178Sandreas.hansson@arm.com assert(!new_itb_port->isConnected()); 4217781SAli.Saidi@ARM.com assert(old_itb_port); 4229178Sandreas.hansson@arm.com assert(old_itb_port->isConnected()); 4239294Sandreas.hansson@arm.com BaseSlavePort &slavePort = old_itb_port->getSlavePort(); 4249178Sandreas.hansson@arm.com old_itb_port->unbind(); 4258922Swilliam.wang@arm.com new_itb_port->bind(slavePort); 4267781SAli.Saidi@ARM.com } 4279178Sandreas.hansson@arm.com if (new_dtb_port) { 4289178Sandreas.hansson@arm.com assert(!new_dtb_port->isConnected()); 4297781SAli.Saidi@ARM.com assert(old_dtb_port); 4309178Sandreas.hansson@arm.com assert(old_dtb_port->isConnected()); 4319294Sandreas.hansson@arm.com BaseSlavePort &slavePort = old_dtb_port->getSlavePort(); 4329178Sandreas.hansson@arm.com old_dtb_port->unbind(); 4338922Swilliam.wang@arm.com new_dtb_port->bind(slavePort); 4347781SAli.Saidi@ARM.com } 43510194SGeoffrey.Blake@arm.com newTC->getITBPtr()->takeOverFrom(oldTC->getITBPtr()); 43610194SGeoffrey.Blake@arm.com newTC->getDTBPtr()->takeOverFrom(oldTC->getDTBPtr()); 4378733Sgeoffrey.blake@arm.com 4388887Sgeoffrey.blake@arm.com // Checker whether or not we have to transfer CheckerCPU 4398887Sgeoffrey.blake@arm.com // objects over in the switch 4408887Sgeoffrey.blake@arm.com CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr(); 4418887Sgeoffrey.blake@arm.com CheckerCPU *newChecker = newTC->getCheckerCpuPtr(); 4428887Sgeoffrey.blake@arm.com if (oldChecker && newChecker) { 4439294Sandreas.hansson@arm.com BaseMasterPort *old_checker_itb_port = 4448922Swilliam.wang@arm.com oldChecker->getITBPtr()->getMasterPort(); 4459294Sandreas.hansson@arm.com BaseMasterPort *old_checker_dtb_port = 4468922Swilliam.wang@arm.com oldChecker->getDTBPtr()->getMasterPort(); 4479294Sandreas.hansson@arm.com BaseMasterPort *new_checker_itb_port = 4488922Swilliam.wang@arm.com newChecker->getITBPtr()->getMasterPort(); 4499294Sandreas.hansson@arm.com BaseMasterPort *new_checker_dtb_port = 4508922Swilliam.wang@arm.com newChecker->getDTBPtr()->getMasterPort(); 4518733Sgeoffrey.blake@arm.com 45210194SGeoffrey.Blake@arm.com newChecker->getITBPtr()->takeOverFrom(oldChecker->getITBPtr()); 45310194SGeoffrey.Blake@arm.com newChecker->getDTBPtr()->takeOverFrom(oldChecker->getDTBPtr()); 45410194SGeoffrey.Blake@arm.com 4558887Sgeoffrey.blake@arm.com // Move over any table walker ports if they exist for checker 4569178Sandreas.hansson@arm.com if (new_checker_itb_port) { 4579178Sandreas.hansson@arm.com assert(!new_checker_itb_port->isConnected()); 4588887Sgeoffrey.blake@arm.com assert(old_checker_itb_port); 4599178Sandreas.hansson@arm.com assert(old_checker_itb_port->isConnected()); 4609294Sandreas.hansson@arm.com BaseSlavePort &slavePort = 4619294Sandreas.hansson@arm.com old_checker_itb_port->getSlavePort(); 4629178Sandreas.hansson@arm.com old_checker_itb_port->unbind(); 4638922Swilliam.wang@arm.com new_checker_itb_port->bind(slavePort); 4648887Sgeoffrey.blake@arm.com } 4659178Sandreas.hansson@arm.com if (new_checker_dtb_port) { 4669178Sandreas.hansson@arm.com assert(!new_checker_dtb_port->isConnected()); 4678887Sgeoffrey.blake@arm.com assert(old_checker_dtb_port); 4689178Sandreas.hansson@arm.com assert(old_checker_dtb_port->isConnected()); 4699294Sandreas.hansson@arm.com BaseSlavePort &slavePort = 4709294Sandreas.hansson@arm.com old_checker_dtb_port->getSlavePort(); 4719178Sandreas.hansson@arm.com old_checker_dtb_port->unbind(); 4728922Swilliam.wang@arm.com new_checker_dtb_port->bind(slavePort); 4738887Sgeoffrey.blake@arm.com } 4748733Sgeoffrey.blake@arm.com } 475180SN/A } 476605SN/A 4773520Sgblack@eecs.umich.edu interrupts = oldCPU->interrupts; 4785810Sgblack@eecs.umich.edu interrupts->setCPU(this); 4799152Satgutier@umich.edu oldCPU->interrupts = NULL; 4802254SN/A 4818779Sgblack@eecs.umich.edu if (FullSystem) { 4828779Sgblack@eecs.umich.edu for (ThreadID i = 0; i < size; ++i) 4838779Sgblack@eecs.umich.edu threadContexts[i]->profileClear(); 4842254SN/A 4858779Sgblack@eecs.umich.edu if (profileEvent) 4868779Sgblack@eecs.umich.edu schedule(profileEvent, curTick()); 4878779Sgblack@eecs.umich.edu } 4884192Sktlim@umich.edu 4899178Sandreas.hansson@arm.com // All CPUs have an instruction and a data port, and the new CPU's 4909178Sandreas.hansson@arm.com // ports are dangling while the old CPU has its ports connected 4919178Sandreas.hansson@arm.com // already. Unbind the old CPU and then bind the ports of the one 4929178Sandreas.hansson@arm.com // we are switching to. 4939178Sandreas.hansson@arm.com assert(!getInstPort().isConnected()); 4949178Sandreas.hansson@arm.com assert(oldCPU->getInstPort().isConnected()); 4959294Sandreas.hansson@arm.com BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort(); 4969178Sandreas.hansson@arm.com oldCPU->getInstPort().unbind(); 4979178Sandreas.hansson@arm.com getInstPort().bind(inst_peer_port); 4984192Sktlim@umich.edu 4999178Sandreas.hansson@arm.com assert(!getDataPort().isConnected()); 5009178Sandreas.hansson@arm.com assert(oldCPU->getDataPort().isConnected()); 5019294Sandreas.hansson@arm.com BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort(); 5029178Sandreas.hansson@arm.com oldCPU->getDataPort().unbind(); 5039178Sandreas.hansson@arm.com getDataPort().bind(data_peer_port); 504180SN/A} 505180SN/A 5069446SAndreas.Sandberg@ARM.comvoid 5079446SAndreas.Sandberg@ARM.comBaseCPU::flushTLBs() 5089446SAndreas.Sandberg@ARM.com{ 5099446SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < threadContexts.size(); ++i) { 5109446SAndreas.Sandberg@ARM.com ThreadContext &tc(*threadContexts[i]); 5119446SAndreas.Sandberg@ARM.com CheckerCPU *checker(tc.getCheckerCpuPtr()); 5129446SAndreas.Sandberg@ARM.com 5139446SAndreas.Sandberg@ARM.com tc.getITBPtr()->flushAll(); 5149446SAndreas.Sandberg@ARM.com tc.getDTBPtr()->flushAll(); 5159446SAndreas.Sandberg@ARM.com if (checker) { 5169446SAndreas.Sandberg@ARM.com checker->getITBPtr()->flushAll(); 5179446SAndreas.Sandberg@ARM.com checker->getDTBPtr()->flushAll(); 5189446SAndreas.Sandberg@ARM.com } 5199446SAndreas.Sandberg@ARM.com } 5209446SAndreas.Sandberg@ARM.com} 5219446SAndreas.Sandberg@ARM.com 522180SN/A 5235536Srstrong@hp.comBaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval) 5245606Snate@binkert.org : cpu(_cpu), interval(_interval) 5251917SN/A{ } 5261917SN/A 5271917SN/Avoid 5281917SN/ABaseCPU::ProfileEvent::process() 5291917SN/A{ 5306221Snate@binkert.org ThreadID size = cpu->threadContexts.size(); 5316221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 5322680Sktlim@umich.edu ThreadContext *tc = cpu->threadContexts[i]; 5332680Sktlim@umich.edu tc->profileSample(); 5341917SN/A } 5352254SN/A 5367823Ssteve.reinhardt@amd.com cpu->schedule(this, curTick() + interval); 5371917SN/A} 5381917SN/A 5392SN/Avoid 540921SN/ABaseCPU::serialize(std::ostream &os) 541921SN/A{ 5424000Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(instCnt); 5439332Sdam.sunwoo@arm.com 5449448SAndreas.Sandberg@ARM.com if (!_switchedOut) { 5459448SAndreas.Sandberg@ARM.com /* Unlike _pid, _taskId is not serialized, as they are dynamically 5469448SAndreas.Sandberg@ARM.com * assigned unique ids that are only meaningful for the duration of 5479448SAndreas.Sandberg@ARM.com * a specific run. We will need to serialize the entire taskMap in 5489448SAndreas.Sandberg@ARM.com * system. */ 5499448SAndreas.Sandberg@ARM.com SERIALIZE_SCALAR(_pid); 5509332Sdam.sunwoo@arm.com 5519448SAndreas.Sandberg@ARM.com interrupts->serialize(os); 5529448SAndreas.Sandberg@ARM.com 5539448SAndreas.Sandberg@ARM.com // Serialize the threads, this is done by the CPU implementation. 5549448SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < numThreads; ++i) { 5559448SAndreas.Sandberg@ARM.com nameOut(os, csprintf("%s.xc.%i", name(), i)); 5569448SAndreas.Sandberg@ARM.com serializeThread(os, i); 5579448SAndreas.Sandberg@ARM.com } 5589448SAndreas.Sandberg@ARM.com } 559921SN/A} 560921SN/A 561921SN/Avoid 562921SN/ABaseCPU::unserialize(Checkpoint *cp, const std::string §ion) 563921SN/A{ 5644000Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(instCnt); 5659448SAndreas.Sandberg@ARM.com 5669448SAndreas.Sandberg@ARM.com if (!_switchedOut) { 5679448SAndreas.Sandberg@ARM.com UNSERIALIZE_SCALAR(_pid); 5689448SAndreas.Sandberg@ARM.com interrupts->unserialize(cp, section); 5699448SAndreas.Sandberg@ARM.com 5709448SAndreas.Sandberg@ARM.com // Unserialize the threads, this is done by the CPU implementation. 5719448SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < numThreads; ++i) 5729448SAndreas.Sandberg@ARM.com unserializeThread(cp, csprintf("%s.xc.%i", section, i), i); 5739448SAndreas.Sandberg@ARM.com } 574921SN/A} 575921SN/A 5761191SN/Avoid 5779749Sandreas@sandberg.pp.seBaseCPU::scheduleInstStop(ThreadID tid, Counter insts, const char *cause) 5789749Sandreas@sandberg.pp.se{ 5799749Sandreas@sandberg.pp.se const Tick now(comInstEventQueue[tid]->getCurTick()); 5809983Sstever@gmail.com Event *event(new LocalSimLoopExitEvent(cause, 0)); 5819749Sandreas@sandberg.pp.se 5829749Sandreas@sandberg.pp.se comInstEventQueue[tid]->schedule(event, now + insts); 5839749Sandreas@sandberg.pp.se} 5849749Sandreas@sandberg.pp.se 5859749Sandreas@sandberg.pp.sevoid 5869749Sandreas@sandberg.pp.seBaseCPU::scheduleLoadStop(ThreadID tid, Counter loads, const char *cause) 5879749Sandreas@sandberg.pp.se{ 5889749Sandreas@sandberg.pp.se const Tick now(comLoadEventQueue[tid]->getCurTick()); 5899983Sstever@gmail.com Event *event(new LocalSimLoopExitEvent(cause, 0)); 5909749Sandreas@sandberg.pp.se 5919749Sandreas@sandberg.pp.se comLoadEventQueue[tid]->schedule(event, now + loads); 5929749Sandreas@sandberg.pp.se} 5939749Sandreas@sandberg.pp.se 5949749Sandreas@sandberg.pp.se 5959749Sandreas@sandberg.pp.sevoid 5961191SN/ABaseCPU::traceFunctionsInternal(Addr pc) 5971191SN/A{ 5981191SN/A if (!debugSymbolTable) 5991191SN/A return; 6001191SN/A 6011191SN/A // if pc enters different function, print new function symbol and 6021191SN/A // update saved range. Otherwise do nothing. 6031191SN/A if (pc < currentFunctionStart || pc >= currentFunctionEnd) { 6041191SN/A string sym_str; 6051191SN/A bool found = debugSymbolTable->findNearestSymbol(pc, sym_str, 6061191SN/A currentFunctionStart, 6071191SN/A currentFunctionEnd); 6081191SN/A 6091191SN/A if (!found) { 6101191SN/A // no symbol found: use addr as label 6111191SN/A sym_str = csprintf("0x%x", pc); 6121191SN/A currentFunctionStart = pc; 6131191SN/A currentFunctionEnd = pc + 1; 6141191SN/A } 6151191SN/A 6161191SN/A ccprintf(*functionTraceStream, " (%d)\n%d: %s", 6177823Ssteve.reinhardt@amd.com curTick() - functionEntryTick, curTick(), sym_str); 6187823Ssteve.reinhardt@amd.com functionEntryTick = curTick(); 6191191SN/A } 6201191SN/A} 621