activity.hh revision 2689
16019Shines@cs.fsu.edu/* 212509Schuan.zhu@arm.com * Copyright (c) 2006 The Regents of The University of Michigan 37093Sgblack@eecs.umich.edu * All rights reserved. 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 67093Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 77093Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 87093Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 97093Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 107093Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 117093Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 127093Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 137093Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 146019Shines@cs.fsu.edu * this software without specific prior written permission. 156019Shines@cs.fsu.edu * 166019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * Authors: Kevin Lim 296019Shines@cs.fsu.edu */ 306019Shines@cs.fsu.edu 316019Shines@cs.fsu.edu#ifndef __CPU_ACTIVITY_HH__ 326019Shines@cs.fsu.edu#define __CPU_ACTIVITY_HH__ 336019Shines@cs.fsu.edu 346019Shines@cs.fsu.edu#include "base/timebuf.hh" 356019Shines@cs.fsu.edu#include "base/trace.hh" 366019Shines@cs.fsu.edu 376019Shines@cs.fsu.edu/** 386019Shines@cs.fsu.edu * ActivityRecorder helper class that informs the CPU if it can switch 396019Shines@cs.fsu.edu * over to being idle or not. It works by having a time buffer as 406019Shines@cs.fsu.edu * long as any time buffer in the CPU, and the CPU and all of its 416735Sgblack@eecs.umich.edu * stages inform the ActivityRecorder when they write to any time 426735Sgblack@eecs.umich.edu * buffer. The ActivityRecorder marks a 1 in the "0" slot of the time 4310037SARM gem5 Developers * buffer any time a stage writes to a time buffer, and it advances 4410037SARM gem5 Developers * its time buffer at the same time as all other stages. The 456019Shines@cs.fsu.edu * ActivityRecorder also records if a stage has activity to do next 466019Shines@cs.fsu.edu * cycle. The recorder keeps a count of these two. Thus any time the 476019Shines@cs.fsu.edu * count is non-zero, there is either communication still in flight, 4811793Sbrandon.potter@amd.com * or activity that still must be done, meaning that the CPU can not 4911793Sbrandon.potter@amd.com * idle. If count is zero, then the CPU can safely idle as it has no 5010037SARM gem5 Developers * more outstanding work to do. 5110037SARM gem5 Developers */ 5210037SARM gem5 Developersclass ActivityRecorder { 538229Snate@binkert.org public: 548229Snate@binkert.org ActivityRecorder(int num_stages, int longest_latency, int count); 556019Shines@cs.fsu.edu 568232Snate@binkert.org /** Records that there is activity this cycle. */ 578782Sgblack@eecs.umich.edu void activity(); 586019Shines@cs.fsu.edu 596019Shines@cs.fsu.edu /** Advances the activity buffer, decrementing the activityCount 606019Shines@cs.fsu.edu * if active communication just left the time buffer, and 616019Shines@cs.fsu.edu * determining if there is no activity. 6210037SARM gem5 Developers */ 6310037SARM gem5 Developers void advance(); 6410037SARM gem5 Developers 6510037SARM gem5 Developers /** Marks a stage as active. */ 6610037SARM gem5 Developers void activateStage(const int idx); 6710037SARM gem5 Developers 6810037SARM gem5 Developers /** Deactivates a stage. */ 6910037SARM gem5 Developers void deactivateStage(const int idx); 7010037SARM gem5 Developers 7110037SARM gem5 Developers /** Returns how many things are active within the recorder. */ 7210037SARM gem5 Developers int getActivityCount() { return activityCount; } 7310037SARM gem5 Developers 7410037SARM gem5 Developers /** Sets the count to a starting value. Can be used to disable 7510037SARM gem5 Developers * the idling option. 7610037SARM gem5 Developers */ 7710037SARM gem5 Developers void setActivityCount(int count) 7810037SARM gem5 Developers { activityCount = count; } 7910037SARM gem5 Developers 8010037SARM gem5 Developers /** Returns if the CPU should be active. */ 8110037SARM gem5 Developers bool active() { return activityCount; } 8210037SARM gem5 Developers 8310037SARM gem5 Developers /** Clears the time buffer and the activity count. */ 8410037SARM gem5 Developers void reset(); 8510037SARM gem5 Developers 8610037SARM gem5 Developers /** Debug function to dump the contents of the time buffer. */ 8710037SARM gem5 Developers void dump(); 8810037SARM gem5 Developers 8910037SARM gem5 Developers /** Debug function to ensure that the activity count matches the 9010037SARM gem5 Developers * contents of the time buffer. 9110037SARM gem5 Developers */ 9210037SARM gem5 Developers void validate(); 9310037SARM gem5 Developers 9410037SARM gem5 Developers private: 9510037SARM gem5 Developers /** Time buffer that tracks if any cycles has active communication 9610037SARM gem5 Developers * in them. It should be as long as the longest communication 9710037SARM gem5 Developers * latency in the system. Each time any time buffer is written, 9810037SARM gem5 Developers * the activity buffer should also be written to. The 9910037SARM gem5 Developers * activityBuffer is advanced along with all the other time 10010037SARM gem5 Developers * buffers, so it should have a 1 somewhere in it only if there 10110037SARM gem5 Developers * is active communication in a time buffer. 1026019Shines@cs.fsu.edu */ 10310037SARM gem5 Developers TimeBuffer<bool> activityBuffer; 10410037SARM gem5 Developers 10510037SARM gem5 Developers /** Longest latency time buffer in the CPU. */ 1066019Shines@cs.fsu.edu int longestLatency; 10710037SARM gem5 Developers 10810037SARM gem5 Developers /** Tracks how many stages and cycles of time buffer have 10910037SARM gem5 Developers * activity. Stages increment this count when they switch to 11010037SARM gem5 Developers * active, and decrement it when they switch to 11110037SARM gem5 Developers * inactive. Whenever a cycle that previously had no information 11210037SARM gem5 Developers * is written in the time buffer, this is incremented. When a 11310037SARM gem5 Developers * cycle that had information exits the time buffer due to age, 11410037SARM gem5 Developers * this count is decremented. When the count is 0, there is no 11510037SARM gem5 Developers * activity in the CPU, and it can be descheduled. 11610037SARM gem5 Developers */ 11710037SARM gem5 Developers int activityCount; 11810037SARM gem5 Developers 11910037SARM gem5 Developers /** Number of stages that can be marked as active or inactive. */ 12010037SARM gem5 Developers int numStages; 12110037SARM gem5 Developers 12210037SARM gem5 Developers /** Records which stages are active/inactive. */ 12310037SARM gem5 Developers bool *stageActive; 12410037SARM gem5 Developers}; 12510037SARM gem5 Developers 12610037SARM gem5 Developers#endif // __CPU_ACTIVITY_HH__ 12710037SARM gem5 Developers