activity.hh revision 10202
12348SN/A/* 22348SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32348SN/A * All rights reserved. 42348SN/A * 52348SN/A * Redistribution and use in source and binary forms, with or without 62348SN/A * modification, are permitted provided that the following conditions are 72348SN/A * met: redistributions of source code must retain the above copyright 82348SN/A * notice, this list of conditions and the following disclaimer; 92348SN/A * redistributions in binary form must reproduce the above copyright 102348SN/A * notice, this list of conditions and the following disclaimer in the 112348SN/A * documentation and/or other materials provided with the distribution; 122348SN/A * neither the name of the copyright holders nor the names of its 132348SN/A * contributors may be used to endorse or promote products derived from 142348SN/A * this software without specific prior written permission. 152348SN/A * 162348SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172348SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182348SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192348SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202348SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212348SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222348SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232348SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242348SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252348SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262348SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292348SN/A */ 302325SN/A 312325SN/A#ifndef __CPU_ACTIVITY_HH__ 322325SN/A#define __CPU_ACTIVITY_HH__ 332325SN/A 348229Snate@binkert.org#include "base/trace.hh" 357813Ssteve.reinhardt@amd.com#include "cpu/timebuf.hh" 362325SN/A 372348SN/A/** 382348SN/A * ActivityRecorder helper class that informs the CPU if it can switch 392348SN/A * over to being idle or not. It works by having a time buffer as 402348SN/A * long as any time buffer in the CPU, and the CPU and all of its 412348SN/A * stages inform the ActivityRecorder when they write to any time 422348SN/A * buffer. The ActivityRecorder marks a 1 in the "0" slot of the time 432348SN/A * buffer any time a stage writes to a time buffer, and it advances 442348SN/A * its time buffer at the same time as all other stages. The 452348SN/A * ActivityRecorder also records if a stage has activity to do next 462348SN/A * cycle. The recorder keeps a count of these two. Thus any time the 472348SN/A * count is non-zero, there is either communication still in flight, 482348SN/A * or activity that still must be done, meaning that the CPU can not 492348SN/A * idle. If count is zero, then the CPU can safely idle as it has no 502348SN/A * more outstanding work to do. 512348SN/A */ 525804Snate@binkert.orgclass ActivityRecorder 535804Snate@binkert.org{ 542325SN/A public: 555804Snate@binkert.org ActivityRecorder(const std::string &name, int num_stages, 565804Snate@binkert.org int longest_latency, int count); 579086Sandreas.hansson@arm.com ~ActivityRecorder(); 582325SN/A 592325SN/A /** Records that there is activity this cycle. */ 602325SN/A void activity(); 612348SN/A 622348SN/A /** Advances the activity buffer, decrementing the activityCount 632348SN/A * if active communication just left the time buffer, and 642348SN/A * determining if there is no activity. 652325SN/A */ 662325SN/A void advance(); 672348SN/A 682325SN/A /** Marks a stage as active. */ 692325SN/A void activateStage(const int idx); 702348SN/A 712325SN/A /** Deactivates a stage. */ 722325SN/A void deactivateStage(const int idx); 732325SN/A 7410202SAndrew.Bardsley@arm.com /** Returns the activity status of a stage. */ 7510202SAndrew.Bardsley@arm.com bool getStageActive(const int idx) const { return stageActive[idx]; } 7610202SAndrew.Bardsley@arm.com 7710202SAndrew.Bardsley@arm.com /** Returns the number of stages. */ 7810202SAndrew.Bardsley@arm.com int getNumStages() const { return numStages; } 7910202SAndrew.Bardsley@arm.com 802348SN/A /** Returns how many things are active within the recorder. */ 8110202SAndrew.Bardsley@arm.com int getActivityCount() const { return activityCount; } 822325SN/A 832348SN/A /** Sets the count to a starting value. Can be used to disable 842348SN/A * the idling option. 852348SN/A */ 862325SN/A void setActivityCount(int count) 872325SN/A { activityCount = count; } 882325SN/A 892348SN/A /** Returns if the CPU should be active. */ 902325SN/A bool active() { return activityCount; } 912325SN/A 922348SN/A /** Clears the time buffer and the activity count. */ 932325SN/A void reset(); 942325SN/A 952348SN/A /** Debug function to dump the contents of the time buffer. */ 962325SN/A void dump(); 972325SN/A 982348SN/A /** Debug function to ensure that the activity count matches the 992348SN/A * contents of the time buffer. 1002348SN/A */ 1012325SN/A void validate(); 1022325SN/A 10310202SAndrew.Bardsley@arm.com const std::string &name() const { return _name; } 10410202SAndrew.Bardsley@arm.com 1052325SN/A private: 1065804Snate@binkert.org // provide name() for DPRINTF. 1075804Snate@binkert.org std::string _name; 1085804Snate@binkert.org 1092325SN/A /** Time buffer that tracks if any cycles has active communication 1102325SN/A * in them. It should be as long as the longest communication 1112325SN/A * latency in the system. Each time any time buffer is written, 1122325SN/A * the activity buffer should also be written to. The 1132325SN/A * activityBuffer is advanced along with all the other time 1142325SN/A * buffers, so it should have a 1 somewhere in it only if there 1152325SN/A * is active communication in a time buffer. 1162325SN/A */ 1172325SN/A TimeBuffer<bool> activityBuffer; 1182325SN/A 1192348SN/A /** Longest latency time buffer in the CPU. */ 1202325SN/A int longestLatency; 1212325SN/A 1222325SN/A /** Tracks how many stages and cycles of time buffer have 1232325SN/A * activity. Stages increment this count when they switch to 1242325SN/A * active, and decrement it when they switch to 1252325SN/A * inactive. Whenever a cycle that previously had no information 1262325SN/A * is written in the time buffer, this is incremented. When a 1272325SN/A * cycle that had information exits the time buffer due to age, 1282325SN/A * this count is decremented. When the count is 0, there is no 1292325SN/A * activity in the CPU, and it can be descheduled. 1302325SN/A */ 1312325SN/A int activityCount; 1322325SN/A 1332348SN/A /** Number of stages that can be marked as active or inactive. */ 1342325SN/A int numStages; 1352325SN/A 1362325SN/A /** Records which stages are active/inactive. */ 1372325SN/A bool *stageActive; 1382325SN/A}; 1392325SN/A 1402325SN/A#endif // __CPU_ACTIVITY_HH__ 141