activity.cc revision 3918
12348SN/A/* 22348SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32348SN/A * All rights reserved. 42348SN/A * 52348SN/A * Redistribution and use in source and binary forms, with or without 62348SN/A * modification, are permitted provided that the following conditions are 72348SN/A * met: redistributions of source code must retain the above copyright 82348SN/A * notice, this list of conditions and the following disclaimer; 92348SN/A * redistributions in binary form must reproduce the above copyright 102348SN/A * notice, this list of conditions and the following disclaimer in the 112348SN/A * documentation and/or other materials provided with the distribution; 122348SN/A * neither the name of the copyright holders nor the names of its 132348SN/A * contributors may be used to endorse or promote products derived from 142348SN/A * this software without specific prior written permission. 152348SN/A * 162348SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172348SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182348SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192348SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202348SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212348SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222348SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232348SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242348SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252348SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262348SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292348SN/A */ 302325SN/A 313918Ssaidi@eecs.umich.edu#include <cstring> 323918Ssaidi@eecs.umich.edu 332325SN/A#include "base/timebuf.hh" 342325SN/A#include "cpu/activity.hh" 352325SN/A 362325SN/AActivityRecorder::ActivityRecorder(int num_stages, int longest_latency, 372325SN/A int activity) 382325SN/A : activityBuffer(longest_latency, 0), longestLatency(longest_latency), 392325SN/A activityCount(activity), numStages(num_stages) 402325SN/A{ 412325SN/A stageActive = new bool[numStages]; 423918Ssaidi@eecs.umich.edu std::memset(stageActive, 0, numStages); 432325SN/A} 442325SN/A 452325SN/Avoid 462325SN/AActivityRecorder::activity() 472325SN/A{ 482348SN/A // If we've already recorded activity for this cycle, we don't 492348SN/A // want to increment the count any more. 502325SN/A if (activityBuffer[0]) { 512325SN/A return; 522325SN/A } 532325SN/A 542325SN/A activityBuffer[0] = true; 552325SN/A 562325SN/A ++activityCount; 572325SN/A 582325SN/A DPRINTF(Activity, "Activity: %i\n", activityCount); 592325SN/A} 602325SN/A 612325SN/Avoid 622325SN/AActivityRecorder::advance() 632325SN/A{ 642348SN/A // If there's a 1 in the slot that is about to be erased once the 652348SN/A // time buffer advances, then decrement the activityCount. 662325SN/A if (activityBuffer[-longestLatency]) { 672325SN/A --activityCount; 682325SN/A 692325SN/A assert(activityCount >= 0); 702325SN/A 712325SN/A DPRINTF(Activity, "Activity: %i\n", activityCount); 722325SN/A 732325SN/A if (activityCount == 0) { 742325SN/A DPRINTF(Activity, "No activity left!\n"); 752325SN/A } 762325SN/A } 772325SN/A 782325SN/A activityBuffer.advance(); 792325SN/A} 802325SN/A 812325SN/Avoid 822325SN/AActivityRecorder::activateStage(const int idx) 832325SN/A{ 842348SN/A // Increment the activity count if this stage wasn't already active. 852325SN/A if (!stageActive[idx]) { 862325SN/A ++activityCount; 872325SN/A 882325SN/A stageActive[idx] = true; 892325SN/A 902325SN/A DPRINTF(Activity, "Activity: %i\n", activityCount); 912325SN/A } else { 922325SN/A DPRINTF(Activity, "Stage %i already active.\n", idx); 932325SN/A } 942325SN/A 952325SN/A// assert(activityCount < longestLatency + numStages + 1); 962325SN/A} 972325SN/A 982325SN/Avoid 992325SN/AActivityRecorder::deactivateStage(const int idx) 1002325SN/A{ 1012348SN/A // Decrement the activity count if this stage was active. 1022325SN/A if (stageActive[idx]) { 1032325SN/A --activityCount; 1042325SN/A 1052325SN/A stageActive[idx] = false; 1062325SN/A 1072325SN/A DPRINTF(Activity, "Activity: %i\n", activityCount); 1082325SN/A } else { 1092325SN/A DPRINTF(Activity, "Stage %i already inactive.\n", idx); 1102325SN/A } 1112325SN/A 1122325SN/A assert(activityCount >= 0); 1132325SN/A} 1142325SN/A 1152325SN/Avoid 1162325SN/AActivityRecorder::reset() 1172325SN/A{ 1182325SN/A activityCount = 0; 1193918Ssaidi@eecs.umich.edu std::memset(stageActive, 0, numStages); 1202325SN/A for (int i = 0; i < longestLatency + 1; ++i) 1212325SN/A activityBuffer.advance(); 1222325SN/A} 1232325SN/A 1242325SN/Avoid 1252325SN/AActivityRecorder::dump() 1262325SN/A{ 1272325SN/A for (int i = 0; i <= longestLatency; ++i) { 1282325SN/A cprintf("[Idx:%i %i] ", i, activityBuffer[-i]); 1292325SN/A } 1302325SN/A 1312325SN/A cprintf("\n"); 1322325SN/A 1332325SN/A for (int i = 0; i < numStages; ++i) { 1342325SN/A cprintf("[Stage:%i %i]\n", i, stageActive[i]); 1352325SN/A } 1362325SN/A 1372325SN/A cprintf("\n"); 1382325SN/A 1392325SN/A cprintf("Activity count: %i\n", activityCount); 1402325SN/A} 1412325SN/A 1422325SN/Avoid 1432325SN/AActivityRecorder::validate() 1442325SN/A{ 1452325SN/A int count = 0; 1462325SN/A for (int i = 0; i <= longestLatency; ++i) { 1472325SN/A if (activityBuffer[-i]) { 1482325SN/A count++; 1492325SN/A } 1502325SN/A } 1512325SN/A 1522325SN/A for (int i = 0; i < numStages; ++i) { 1532325SN/A if (stageActive[i]) { 1542325SN/A count++; 1552325SN/A } 1562325SN/A } 1572325SN/A 1582325SN/A assert(count == activityCount); 1592325SN/A} 160