activity.cc revision 2689
12348SN/A/* 22348SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32348SN/A * All rights reserved. 42348SN/A * 52348SN/A * Redistribution and use in source and binary forms, with or without 62348SN/A * modification, are permitted provided that the following conditions are 72348SN/A * met: redistributions of source code must retain the above copyright 82348SN/A * notice, this list of conditions and the following disclaimer; 92348SN/A * redistributions in binary form must reproduce the above copyright 102348SN/A * notice, this list of conditions and the following disclaimer in the 112348SN/A * documentation and/or other materials provided with the distribution; 122348SN/A * neither the name of the copyright holders nor the names of its 132348SN/A * contributors may be used to endorse or promote products derived from 142348SN/A * this software without specific prior written permission. 152348SN/A * 162348SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172348SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182348SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192348SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202348SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212348SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222348SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232348SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242348SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252348SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262348SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292348SN/A */ 302325SN/A 312325SN/A#include "base/timebuf.hh" 322325SN/A#include "cpu/activity.hh" 332325SN/A 342325SN/AActivityRecorder::ActivityRecorder(int num_stages, int longest_latency, 352325SN/A int activity) 362325SN/A : activityBuffer(longest_latency, 0), longestLatency(longest_latency), 372325SN/A activityCount(activity), numStages(num_stages) 382325SN/A{ 392325SN/A stageActive = new bool[numStages]; 402325SN/A memset(stageActive, 0, numStages); 412325SN/A} 422325SN/A 432325SN/Avoid 442325SN/AActivityRecorder::activity() 452325SN/A{ 462348SN/A // If we've already recorded activity for this cycle, we don't 472348SN/A // want to increment the count any more. 482325SN/A if (activityBuffer[0]) { 492325SN/A return; 502325SN/A } 512325SN/A 522325SN/A activityBuffer[0] = true; 532325SN/A 542325SN/A ++activityCount; 552325SN/A 562325SN/A DPRINTF(Activity, "Activity: %i\n", activityCount); 572325SN/A} 582325SN/A 592325SN/Avoid 602325SN/AActivityRecorder::advance() 612325SN/A{ 622348SN/A // If there's a 1 in the slot that is about to be erased once the 632348SN/A // time buffer advances, then decrement the activityCount. 642325SN/A if (activityBuffer[-longestLatency]) { 652325SN/A --activityCount; 662325SN/A 672325SN/A assert(activityCount >= 0); 682325SN/A 692325SN/A DPRINTF(Activity, "Activity: %i\n", activityCount); 702325SN/A 712325SN/A if (activityCount == 0) { 722325SN/A DPRINTF(Activity, "No activity left!\n"); 732325SN/A } 742325SN/A } 752325SN/A 762325SN/A activityBuffer.advance(); 772325SN/A} 782325SN/A 792325SN/Avoid 802325SN/AActivityRecorder::activateStage(const int idx) 812325SN/A{ 822348SN/A // Increment the activity count if this stage wasn't already active. 832325SN/A if (!stageActive[idx]) { 842325SN/A ++activityCount; 852325SN/A 862325SN/A stageActive[idx] = true; 872325SN/A 882325SN/A DPRINTF(Activity, "Activity: %i\n", activityCount); 892325SN/A } else { 902325SN/A DPRINTF(Activity, "Stage %i already active.\n", idx); 912325SN/A } 922325SN/A 932325SN/A// assert(activityCount < longestLatency + numStages + 1); 942325SN/A} 952325SN/A 962325SN/Avoid 972325SN/AActivityRecorder::deactivateStage(const int idx) 982325SN/A{ 992348SN/A // Decrement the activity count if this stage was active. 1002325SN/A if (stageActive[idx]) { 1012325SN/A --activityCount; 1022325SN/A 1032325SN/A stageActive[idx] = false; 1042325SN/A 1052325SN/A DPRINTF(Activity, "Activity: %i\n", activityCount); 1062325SN/A } else { 1072325SN/A DPRINTF(Activity, "Stage %i already inactive.\n", idx); 1082325SN/A } 1092325SN/A 1102325SN/A assert(activityCount >= 0); 1112325SN/A} 1122325SN/A 1132325SN/Avoid 1142325SN/AActivityRecorder::reset() 1152325SN/A{ 1162325SN/A activityCount = 0; 1172325SN/A memset(stageActive, 0, numStages); 1182325SN/A for (int i = 0; i < longestLatency + 1; ++i) 1192325SN/A activityBuffer.advance(); 1202325SN/A} 1212325SN/A 1222325SN/Avoid 1232325SN/AActivityRecorder::dump() 1242325SN/A{ 1252325SN/A for (int i = 0; i <= longestLatency; ++i) { 1262325SN/A cprintf("[Idx:%i %i] ", i, activityBuffer[-i]); 1272325SN/A } 1282325SN/A 1292325SN/A cprintf("\n"); 1302325SN/A 1312325SN/A for (int i = 0; i < numStages; ++i) { 1322325SN/A cprintf("[Stage:%i %i]\n", i, stageActive[i]); 1332325SN/A } 1342325SN/A 1352325SN/A cprintf("\n"); 1362325SN/A 1372325SN/A cprintf("Activity count: %i\n", activityCount); 1382325SN/A} 1392325SN/A 1402325SN/Avoid 1412325SN/AActivityRecorder::validate() 1422325SN/A{ 1432325SN/A int count = 0; 1442325SN/A for (int i = 0; i <= longestLatency; ++i) { 1452325SN/A if (activityBuffer[-i]) { 1462325SN/A count++; 1472325SN/A } 1482325SN/A } 1492325SN/A 1502325SN/A for (int i = 0; i < numStages; ++i) { 1512325SN/A if (stageActive[i]) { 1522325SN/A count++; 1532325SN/A } 1542325SN/A } 1552325SN/A 1562325SN/A assert(count == activityCount); 1572325SN/A} 158