SConscript revision 9534:5de6389b72f7 
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright
9# notice, this list of conditions and the following disclaimer;
10# redistributions in binary form must reproduce the above copyright
11# notice, this list of conditions and the following disclaimer in the
12# documentation and/or other materials provided with the distribution;
13# neither the name of the copyright holders nor the names of its
14# contributors may be used to endorse or promote products derived from
15# this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# Authors: Steve Reinhardt
30
31Import('*')
32
33if env['TARGET_ISA'] == 'no':
34    Return()
35
36#################################################################
37#
38# Generate StaticInst execute() method signatures.
39#
40# There must be one signature for each CPU model compiled in.
41# Since the set of compiled-in models is flexible, we generate a
42# header containing the appropriate set of signatures on the fly.
43#
44#################################################################
45
46# Template for execute() signature.
47exec_sig_template = '''
48virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
49virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
50{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
51virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
52{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
53virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
54                          Trace::InstRecord *traceData) const
55{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
56'''
57
58mem_ini_sig_template = '''
59virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
60{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
61virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
62'''
63
64mem_comp_sig_template = '''
65virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
66'''
67
68# Generate a temporary CPU list, including the CheckerCPU if
69# it's enabled.  This isn't used for anything else other than StaticInst
70# headers.
71temp_cpu_list = env['CPU_MODELS'][:]
72temp_cpu_list.append('CheckerCPU')
73SimObject('CheckerCPU.py')
74
75# Generate header.
76def gen_cpu_exec_signatures(target, source, env):
77    f = open(str(target[0]), 'w')
78    print >> f, '''
79#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
80#define __CPU_STATIC_INST_EXEC_SIGS_HH__
81'''
82    for cpu in temp_cpu_list:
83        xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
84        print >> f, exec_sig_template % { 'type' : xc_type }
85    print >> f, '''
86#endif  // __CPU_STATIC_INST_EXEC_SIGS_HH__
87'''
88
89# Generate string that gets printed when header is rebuilt
90def gen_sigs_string(target, source, env):
91    return " [GENERATE] static_inst_exec_sigs.hh: " \
92           + ', '.join(temp_cpu_list)
93
94# Add command to generate header to environment.
95env.Command('static_inst_exec_sigs.hh', (),
96            Action(gen_cpu_exec_signatures, gen_sigs_string,
97                   varlist = temp_cpu_list))
98
99env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
100
101SimObject('BaseCPU.py')
102SimObject('FuncUnit.py')
103SimObject('ExeTracer.py')
104SimObject('IntelTrace.py')
105SimObject('IntrControl.py')
106SimObject('NativeTrace.py')
107
108Source('activity.cc')
109Source('base.cc')
110Source('cpuevent.cc')
111Source('exetrace.cc')
112Source('func_unit.cc')
113Source('inteltrace.cc')
114Source('intr_control.cc')
115Source('nativetrace.cc')
116Source('pc_event.cc')
117Source('profile.cc')
118Source('quiesce_event.cc')
119Source('static_inst.cc')
120Source('simple_thread.cc')
121Source('thread_context.cc')
122Source('thread_state.cc')
123
124if env['TARGET_ISA'] == 'sparc':
125    SimObject('LegionTrace.py')
126    Source('legiontrace.cc')
127
128SimObject('DummyChecker.py')
129Source('checker/cpu.cc')
130Source('dummy_checker.cc')
131DebugFlag('Checker')
132
133DebugFlag('Activity')
134DebugFlag('Commit')
135DebugFlag('Context')
136DebugFlag('Decode')
137DebugFlag('DynInst')
138DebugFlag('ExecEnable', 'Filter: Enable exec tracing (no tracing without this)')
139DebugFlag('ExecCPSeq', 'Format: Instruction sequence number')
140DebugFlag('ExecEffAddr', 'Format: Include effective address')
141DebugFlag('ExecFaulting', 'Trace faulting instructions')
142DebugFlag('ExecFetchSeq', 'Format: Fetch sequence number')
143DebugFlag('ExecOpClass', 'Format: Include operand class')
144DebugFlag('ExecRegDelta')
145DebugFlag('ExecResult', 'Format: Include results from execution')
146DebugFlag('ExecSpeculative', 'Format: Include a miss-/speculation flag (-/+)')
147DebugFlag('ExecSymbol', 'Format: Try to include symbol names')
148DebugFlag('ExecThread', 'Format: Include thread ID in trace')
149DebugFlag('ExecTicks', 'Format: Include tick count')
150DebugFlag('ExecMicro', 'Filter: Include microops')
151DebugFlag('ExecMacro', 'Filter: Include macroops')
152DebugFlag('ExecUser', 'Filter: Trace user mode instructions')
153DebugFlag('ExecKernel', 'Filter: Trace kernel mode instructions')
154DebugFlag('ExecAsid', 'Format: Include ASID in trace')
155DebugFlag('Fetch')
156DebugFlag('IntrControl')
157DebugFlag('O3PipeView')
158DebugFlag('PCEvent')
159DebugFlag('Quiesce')
160
161CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
162    'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
163    'ExecResult', 'ExecSpeculative', 'ExecSymbol', 'ExecThread',
164    'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
165    'ExecAsid' ])
166CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
167    'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting',
168    'ExecUser', 'ExecKernel' ])
169CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
170    'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting',
171    'ExecUser', 'ExecKernel' ])
172