SConscript revision 9340:40f8c6a8f38d
14486Sbinkertn@umich.edu# -*- mode:python -*- 24486Sbinkertn@umich.edu 34486Sbinkertn@umich.edu# Copyright (c) 2006 The Regents of The University of Michigan 44486Sbinkertn@umich.edu# All rights reserved. 54486Sbinkertn@umich.edu# 64486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 74486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 84486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 94486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 104486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 114486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 124486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 134486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 144486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 154486Sbinkertn@umich.edu# this software without specific prior written permission. 164486Sbinkertn@umich.edu# 174486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 184486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 194486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 204486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 214486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 224486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 234486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 244486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 254486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 264486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 274486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 284486Sbinkertn@umich.edu# 293102SN/A# Authors: Steve Reinhardt 303102SN/A 313102SN/AImport('*') 321692SN/A 331366SN/Aif env['TARGET_ISA'] == 'no': 349338SAndreas.Sandberg@arm.com Return() 354103SN/A 36################################################################# 37# 38# Generate StaticInst execute() method signatures. 39# 40# There must be one signature for each CPU model compiled in. 41# Since the set of compiled-in models is flexible, we generate a 42# header containing the appropriate set of signatures on the fly. 43# 44################################################################# 45 46# Template for execute() signature. 47exec_sig_template = ''' 48virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0; 49virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const 50{ panic("eaComp not defined!"); M5_DUMMY_RETURN }; 51virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const 52{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN }; 53virtual Fault completeAcc(Packet *pkt, %(type)s *xc, 54 Trace::InstRecord *traceData) const 55{ panic("completeAcc not defined!"); M5_DUMMY_RETURN }; 56''' 57 58mem_ini_sig_template = ''' 59virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const 60{ panic("eaComp not defined!"); M5_DUMMY_RETURN }; 61virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN }; 62''' 63 64mem_comp_sig_template = ''' 65virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN }; 66''' 67 68# Generate a temporary CPU list, including the CheckerCPU if 69# it's enabled. This isn't used for anything else other than StaticInst 70# headers. 71temp_cpu_list = env['CPU_MODELS'][:] 72temp_cpu_list.append('CheckerCPU') 73SimObject('CheckerCPU.py') 74 75# Generate header. 76def gen_cpu_exec_signatures(target, source, env): 77 f = open(str(target[0]), 'w') 78 print >> f, ''' 79#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__ 80#define __CPU_STATIC_INST_EXEC_SIGS_HH__ 81''' 82 for cpu in temp_cpu_list: 83 xc_type = CpuModel.dict[cpu].strings['CPU_exec_context'] 84 print >> f, exec_sig_template % { 'type' : xc_type } 85 print >> f, ''' 86#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__ 87''' 88 89# Generate string that gets printed when header is rebuilt 90def gen_sigs_string(target, source, env): 91 return " [GENERATE] static_inst_exec_sigs.hh: " \ 92 + ', '.join(temp_cpu_list) 93 94# Add command to generate header to environment. 95env.Command('static_inst_exec_sigs.hh', (), 96 Action(gen_cpu_exec_signatures, gen_sigs_string, 97 varlist = temp_cpu_list)) 98 99env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS'])) 100 101SimObject('BaseCPU.py') 102SimObject('FuncUnit.py') 103SimObject('ExeTracer.py') 104SimObject('IntelTrace.py') 105SimObject('IntrControl.py') 106SimObject('NativeTrace.py') 107 108Source('activity.cc') 109Source('base.cc') 110Source('cpuevent.cc') 111Source('exetrace.cc') 112Source('func_unit.cc') 113Source('inteltrace.cc') 114Source('intr_control.cc') 115Source('nativetrace.cc') 116Source('pc_event.cc') 117Source('profile.cc') 118Source('quiesce_event.cc') 119Source('static_inst.cc') 120Source('simple_thread.cc') 121Source('thread_context.cc') 122Source('thread_state.cc') 123 124if env['TARGET_ISA'] == 'sparc': 125 SimObject('LegionTrace.py') 126 Source('legiontrace.cc') 127 128SimObject('DummyChecker.py') 129Source('checker/cpu.cc') 130Source('dummy_checker.cc') 131DebugFlag('Checker') 132 133DebugFlag('Activity') 134DebugFlag('Commit') 135DebugFlag('Context') 136DebugFlag('Decode') 137DebugFlag('DynInst') 138DebugFlag('ExecEnable') 139DebugFlag('ExecCPSeq') 140DebugFlag('ExecEffAddr') 141DebugFlag('ExecFaulting', 'Trace faulting instructions') 142DebugFlag('ExecFetchSeq') 143DebugFlag('ExecOpClass') 144DebugFlag('ExecRegDelta') 145DebugFlag('ExecResult') 146DebugFlag('ExecSpeculative') 147DebugFlag('ExecSymbol') 148DebugFlag('ExecThread') 149DebugFlag('ExecTicks') 150DebugFlag('ExecMicro') 151DebugFlag('ExecMacro') 152DebugFlag('ExecUser') 153DebugFlag('ExecKernel') 154DebugFlag('ExecAsid') 155DebugFlag('Fetch') 156DebugFlag('IntrControl') 157DebugFlag('O3PipeView') 158DebugFlag('PCEvent') 159DebugFlag('Quiesce') 160 161CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr', 162 'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta', 163 'ExecResult', 'ExecSpeculative', 'ExecSymbol', 'ExecThread', 164 'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel', 165 'ExecAsid' ]) 166CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread', 167 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting', 168 'ExecUser', 'ExecKernel' ]) 169CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread', 170 'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting', 171 'ExecUser', 'ExecKernel' ]) 172