SConscript revision 8739
12155SN/A# -*- mode:python -*-
22155SN/A
32155SN/A# Copyright (c) 2006 The Regents of The University of Michigan
42155SN/A# All rights reserved.
52155SN/A#
62155SN/A# Redistribution and use in source and binary forms, with or without
72155SN/A# modification, are permitted provided that the following conditions are
82155SN/A# met: redistributions of source code must retain the above copyright
92155SN/A# notice, this list of conditions and the following disclaimer;
102155SN/A# redistributions in binary form must reproduce the above copyright
112155SN/A# notice, this list of conditions and the following disclaimer in the
122155SN/A# documentation and/or other materials provided with the distribution;
132155SN/A# neither the name of the copyright holders nor the names of its
142155SN/A# contributors may be used to endorse or promote products derived from
152155SN/A# this software without specific prior written permission.
162155SN/A#
172155SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
182155SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
192155SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
202155SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
212155SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
222155SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
232155SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
242155SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
252155SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
262155SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
272155SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
282665Ssaidi@eecs.umich.edu#
292665Ssaidi@eecs.umich.edu# Authors: Steve Reinhardt
302155SN/A
314202Sbinkertn@umich.eduImport('*')
322155SN/A
332178SN/Aif env['TARGET_ISA'] == 'no':
342178SN/A    Return()
352178SN/A
362178SN/A#################################################################
372178SN/A#
382178SN/A# Generate StaticInst execute() method signatures.
392178SN/A#
402178SN/A# There must be one signature for each CPU model compiled in.
412178SN/A# Since the set of compiled-in models is flexible, we generate a
422178SN/A# header containing the appropriate set of signatures on the fly.
432178SN/A#
442155SN/A#################################################################
455865Sksewell@umich.edu
466181Sksewell@umich.edu# Template for execute() signature.
476181Sksewell@umich.eduexec_sig_template = '''
485865Sksewell@umich.eduvirtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
493918Ssaidi@eecs.umich.eduvirtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
505865Sksewell@umich.edu{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
512623SN/Avirtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
523918Ssaidi@eecs.umich.edu{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
532155SN/Avirtual Fault completeAcc(Packet *pkt, %(type)s *xc,
542155SN/A                          Trace::InstRecord *traceData) const
552292SN/A{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
566181Sksewell@umich.edu'''
576181Sksewell@umich.edu
583918Ssaidi@eecs.umich.edumem_ini_sig_template = '''
592292SN/Avirtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
602292SN/A{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
612292SN/Avirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
623918Ssaidi@eecs.umich.edu'''
632292SN/A
642292SN/Amem_comp_sig_template = '''
652766Sktlim@umich.eduvirtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
662766Sktlim@umich.edu'''
672766Sktlim@umich.edu
682921Sktlim@umich.edu# Generate a temporary CPU list, including the CheckerCPU if
692921Sktlim@umich.edu# it's enabled.  This isn't used for anything else other than StaticInst
702766Sktlim@umich.edu# headers.
712766Sktlim@umich.edutemp_cpu_list = env['CPU_MODELS'][:]
725529Snate@binkert.org
732766Sktlim@umich.eduif env['USE_CHECKER']:
744762Snate@binkert.org    temp_cpu_list.append('CheckerCPU')
752155SN/A    SimObject('CheckerCPU.py')
762155SN/A
772155SN/A# Generate header.
782155SN/Adef gen_cpu_exec_signatures(target, source, env):
792155SN/A    f = open(str(target[0]), 'w')
802155SN/A    print >> f, '''
812766Sktlim@umich.edu#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
822155SN/A#define __CPU_STATIC_INST_EXEC_SIGS_HH__
835865Sksewell@umich.edu'''
842155SN/A    for cpu in temp_cpu_list:
852155SN/A        xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
862155SN/A        print >> f, exec_sig_template % { 'type' : xc_type }
872155SN/A    print >> f, '''
882178SN/A#endif  // __CPU_STATIC_INST_EXEC_SIGS_HH__
892178SN/A'''
902178SN/A
912766Sktlim@umich.edu# Generate string that gets printed when header is rebuilt
922178SN/Adef gen_sigs_string(target, source, env):
932178SN/A    return " [GENERATE] static_inst_exec_sigs.hh: " \
946994Snate@binkert.org           + ', '.join(temp_cpu_list)
952178SN/A
962766Sktlim@umich.edu# Add command to generate header to environment.
972766Sktlim@umich.eduenv.Command('static_inst_exec_sigs.hh', (),
982766Sktlim@umich.edu            Action(gen_cpu_exec_signatures, gen_sigs_string,
992788Sktlim@umich.edu                   varlist = temp_cpu_list))
1002178SN/A
1012733Sktlim@umich.eduenv.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER']))
1022733Sktlim@umich.eduenv.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
1032817Sksewell@umich.edu
1042733Sktlim@umich.edu# List of suppported CPUs by the Checker.  Errors out if USE_CHECKER=True
1054486Sbinkertn@umich.edu# and one of these are not being used.
1064486Sbinkertn@umich.eduCheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
1074776Sgblack@eecs.umich.edu
1084776Sgblack@eecs.umich.eduSimObject('BaseCPU.py')
1096365Sgblack@eecs.umich.eduSimObject('FuncUnit.py')
1104486Sbinkertn@umich.eduSimObject('ExeTracer.py')
1114202Sbinkertn@umich.eduSimObject('IntelTrace.py')
1124202Sbinkertn@umich.eduSimObject('IntrControl.py')
1134202Sbinkertn@umich.eduSimObject('NativeTrace.py')
1144202Sbinkertn@umich.edu
1154202Sbinkertn@umich.eduSource('activity.cc')
1164776Sgblack@eecs.umich.eduSource('base.cc')
1176365Sgblack@eecs.umich.eduSource('cpuevent.cc')
1184202Sbinkertn@umich.eduSource('decode.cc')
1194202Sbinkertn@umich.eduSource('exetrace.cc')
1204202Sbinkertn@umich.eduSource('func_unit.cc')
1214202Sbinkertn@umich.eduSource('inteltrace.cc')
1225217Ssaidi@eecs.umich.eduSource('intr_control.cc')
1234202Sbinkertn@umich.eduSource('nativetrace.cc')
1242155SN/ASource('pc_event.cc')
1254202Sbinkertn@umich.eduSource('quiesce_event.cc')
1264486Sbinkertn@umich.eduSource('static_inst.cc')
1274486Sbinkertn@umich.eduSource('simple_thread.cc')
1284202Sbinkertn@umich.eduSource('thread_context.cc')
1294202Sbinkertn@umich.eduSource('thread_state.cc')
1302821Sktlim@umich.edu
1314776Sgblack@eecs.umich.eduif env['FULL_SYSTEM']:
1324776Sgblack@eecs.umich.edu    Source('profile.cc')
1334776Sgblack@eecs.umich.edu
1344776Sgblack@eecs.umich.edu    if env['TARGET_ISA'] == 'sparc':
1352766Sktlim@umich.edu        SimObject('LegionTrace.py')
1364202Sbinkertn@umich.edu        Source('legiontrace.cc')
1375192Ssaidi@eecs.umich.edu
1382733Sktlim@umich.eduif env['USE_CHECKER']:
1392733Sktlim@umich.edu    Source('checker/cpu.cc')
1402733Sktlim@umich.edu    DebugFlag('Checker')
1412733Sktlim@umich.edu    checker_supports = False
1422733Sktlim@umich.edu    for i in CheckerSupportedCPUList:
1432874Sktlim@umich.edu        if i in env['CPU_MODELS']:
1442874Sktlim@umich.edu            checker_supports = True
1452874Sktlim@umich.edu    if not checker_supports:
1464202Sbinkertn@umich.edu        print "Checker only supports CPU models",
1472733Sktlim@umich.edu        for i in CheckerSupportedCPUList:
1485192Ssaidi@eecs.umich.edu            print i,
1495192Ssaidi@eecs.umich.edu        print ", please set USE_CHECKER=False or use one of those CPU models"
1505192Ssaidi@eecs.umich.edu        Exit(1)
1515217Ssaidi@eecs.umich.edu
1525192Ssaidi@eecs.umich.eduDebugFlag('Activity')
1535192Ssaidi@eecs.umich.eduDebugFlag('Commit')
1545192Ssaidi@eecs.umich.eduDebugFlag('Context')
1555192Ssaidi@eecs.umich.eduDebugFlag('Decode')
1565192Ssaidi@eecs.umich.eduDebugFlag('DynInst')
1576667Ssteve.reinhardt@amd.comDebugFlag('ExecEnable')
1585192Ssaidi@eecs.umich.eduDebugFlag('ExecCPSeq')
1595192Ssaidi@eecs.umich.eduDebugFlag('ExecEffAddr')
1605192Ssaidi@eecs.umich.eduDebugFlag('ExecFaulting', 'Trace faulting instructions')
1615192Ssaidi@eecs.umich.eduDebugFlag('ExecFetchSeq')
1625192Ssaidi@eecs.umich.eduDebugFlag('ExecOpClass')
1635192Ssaidi@eecs.umich.eduDebugFlag('ExecRegDelta')
1645192Ssaidi@eecs.umich.eduDebugFlag('ExecResult')
1655192Ssaidi@eecs.umich.eduDebugFlag('ExecSpeculative')
1665784Sgblack@eecs.umich.eduDebugFlag('ExecSymbol')
1675784Sgblack@eecs.umich.eduDebugFlag('ExecThread')
1685192Ssaidi@eecs.umich.eduDebugFlag('ExecTicks')
1695192Ssaidi@eecs.umich.eduDebugFlag('ExecMicro')
1705192Ssaidi@eecs.umich.eduDebugFlag('ExecMacro')
1715192Ssaidi@eecs.umich.eduDebugFlag('ExecUser')
1725192Ssaidi@eecs.umich.eduDebugFlag('ExecKernel')
1735192Ssaidi@eecs.umich.eduDebugFlag('ExecAsid')
1746667Ssteve.reinhardt@amd.comDebugFlag('Fetch')
1756036Sksewell@umich.eduDebugFlag('IntrControl')
1766667Ssteve.reinhardt@amd.comDebugFlag('O3PipeView')
177DebugFlag('PCEvent')
178DebugFlag('Quiesce')
179
180CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
181    'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
182    'ExecResult', 'ExecSpeculative', 'ExecSymbol', 'ExecThread',
183    'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
184    'ExecAsid' ])
185CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
186    'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting',
187    'ExecUser', 'ExecKernel' ])
188CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
189    'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting',
190    'ExecUser', 'ExecKernel' ])
191