SConscript revision 6667:8b5bc1a777bc 
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright
9# notice, this list of conditions and the following disclaimer;
10# redistributions in binary form must reproduce the above copyright
11# notice, this list of conditions and the following disclaimer in the
12# documentation and/or other materials provided with the distribution;
13# neither the name of the copyright holders nor the names of its
14# contributors may be used to endorse or promote products derived from
15# this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# Authors: Steve Reinhardt
30
31Import('*')
32
33#################################################################
34#
35# Generate StaticInst execute() method signatures.
36#
37# There must be one signature for each CPU model compiled in.
38# Since the set of compiled-in models is flexible, we generate a
39# header containing the appropriate set of signatures on the fly.
40#
41#################################################################
42
43# CPU model-specific data is contained in cpu_models.py
44# Convert to SCons File node to get path handling
45models_db = File('cpu_models.py')
46# slurp in contents of file
47execfile(models_db.srcnode().abspath)
48
49# Template for execute() signature.
50exec_sig_template = '''
51virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
52virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
53{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
54virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
55{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
56virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
57                          Trace::InstRecord *traceData) const
58{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
59'''
60
61mem_ini_sig_template = '''
62virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
63{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
64virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
65'''
66
67mem_comp_sig_template = '''
68virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
69'''
70
71# Generate a temporary CPU list, including the CheckerCPU if
72# it's enabled.  This isn't used for anything else other than StaticInst
73# headers.
74temp_cpu_list = env['CPU_MODELS'][:]
75
76if env['USE_CHECKER']:
77    temp_cpu_list.append('CheckerCPU')
78    SimObject('CheckerCPU.py')
79
80# Generate header.
81def gen_cpu_exec_signatures(target, source, env):
82    f = open(str(target[0]), 'w')
83    print >> f, '''
84#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
85#define __CPU_STATIC_INST_EXEC_SIGS_HH__
86'''
87    for cpu in temp_cpu_list:
88        xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
89        print >> f, exec_sig_template % { 'type' : xc_type }
90    print >> f, '''
91#endif  // __CPU_STATIC_INST_EXEC_SIGS_HH__
92'''
93
94# Generate string that gets printed when header is rebuilt
95def gen_sigs_string(target, source, env):
96    return "Generating static_inst_exec_sigs.hh: " \
97           + ', '.join(temp_cpu_list)
98
99# Add command to generate header to environment.
100env.Command('static_inst_exec_sigs.hh', models_db,
101            Action(gen_cpu_exec_signatures, gen_sigs_string,
102                   varlist = temp_cpu_list))
103
104env.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER']))
105env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
106
107# List of suppported CPUs by the Checker.  Errors out if USE_CHECKER=True
108# and one of these are not being used.
109CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
110
111SimObject('BaseCPU.py')
112SimObject('FuncUnit.py')
113SimObject('ExeTracer.py')
114SimObject('IntelTrace.py')
115SimObject('NativeTrace.py')
116
117Source('activity.cc')
118Source('base.cc')
119Source('cpuevent.cc')
120Source('exetrace.cc')
121Source('func_unit.cc')
122Source('inteltrace.cc')
123Source('nativetrace.cc')
124Source('pc_event.cc')
125Source('quiesce_event.cc')
126Source('static_inst.cc')
127Source('simple_thread.cc')
128Source('thread_context.cc')
129Source('thread_state.cc')
130
131if env['FULL_SYSTEM']:
132    SimObject('IntrControl.py')
133
134    Source('intr_control.cc')
135    Source('profile.cc')
136
137    if env['TARGET_ISA'] == 'sparc':
138        SimObject('LegionTrace.py')
139        Source('legiontrace.cc')
140
141if env['USE_CHECKER']:
142    Source('checker/cpu.cc')
143    TraceFlag('Checker')
144    checker_supports = False
145    for i in CheckerSupportedCPUList:
146        if i in env['CPU_MODELS']:
147            checker_supports = True
148    if not checker_supports:
149        print "Checker only supports CPU models",
150        for i in CheckerSupportedCPUList:
151            print i,
152        print ", please set USE_CHECKER=False or use one of those CPU models"
153        Exit(1)
154
155TraceFlag('Activity')
156TraceFlag('Commit')
157TraceFlag('Context')
158TraceFlag('Decode')
159TraceFlag('DynInst')
160TraceFlag('ExecEnable')
161TraceFlag('ExecCPSeq')
162TraceFlag('ExecEffAddr')
163TraceFlag('ExecFaulting', 'Trace faulting instructions')
164TraceFlag('ExecFetchSeq')
165TraceFlag('ExecOpClass')
166TraceFlag('ExecRegDelta')
167TraceFlag('ExecResult')
168TraceFlag('ExecSpeculative')
169TraceFlag('ExecSymbol')
170TraceFlag('ExecThread')
171TraceFlag('ExecTicks')
172TraceFlag('ExecMicro')
173TraceFlag('ExecMacro')
174TraceFlag('Fetch')
175TraceFlag('IntrControl')
176TraceFlag('PCEvent')
177TraceFlag('Quiesce')
178
179CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
180    'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting' ])
181CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
182    'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting' ])
183