SConscript revision 6365:a3037fa327a0
12SN/A# -*- mode:python -*- 21762SN/A 32SN/A# Copyright (c) 2006 The Regents of The University of Michigan 42SN/A# All rights reserved. 52SN/A# 62SN/A# Redistribution and use in source and binary forms, with or without 72SN/A# modification, are permitted provided that the following conditions are 82SN/A# met: redistributions of source code must retain the above copyright 92SN/A# notice, this list of conditions and the following disclaimer; 102SN/A# redistributions in binary form must reproduce the above copyright 112SN/A# notice, this list of conditions and the following disclaimer in the 122SN/A# documentation and/or other materials provided with the distribution; 132SN/A# neither the name of the copyright holders nor the names of its 142SN/A# contributors may be used to endorse or promote products derived from 152SN/A# this software without specific prior written permission. 162SN/A# 172SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272665Ssaidi@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu# 292665Ssaidi@eecs.umich.edu# Authors: Steve Reinhardt 302SN/A 312SN/AImport('*') 321112SN/A 331112SN/A################################################################# 342SN/A# 356215Snate@binkert.org# Generate StaticInst execute() method signatures. 362SN/A# 372SN/A# There must be one signature for each CPU model compiled in. 382SN/A# Since the set of compiled-in models is flexible, we generate a 392SN/A# header containing the appropriate set of signatures on the fly. 402SN/A# 412SN/A################################################################# 422SN/A 432SN/A# CPU model-specific data is contained in cpu_models.py 442SN/A# Convert to SCons File node to get path handling 452SN/Amodels_db = File('cpu_models.py') 462SN/A# slurp in contents of file 474070Ssaidi@eecs.umich.eduexecfile(models_db.srcnode().abspath) 482SN/A 492SN/A# Template for execute() signature. 502SN/Aexec_sig_template = ''' 512SN/Avirtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0; 522SN/Avirtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const 532SN/A{ panic("eaComp not defined!"); M5_DUMMY_RETURN }; 542SN/Avirtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const 552SN/A{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN }; 562SN/Avirtual Fault completeAcc(Packet *pkt, %(type)s *xc, 572SN/A Trace::InstRecord *traceData) const 582SN/A{ panic("completeAcc not defined!"); M5_DUMMY_RETURN }; 592SN/A''' 602SN/A 612SN/Amem_ini_sig_template = ''' 624661Sksewell@umich.eduvirtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const 634661Sksewell@umich.edu{ panic("eaComp not defined!"); M5_DUMMY_RETURN }; 644661Sksewell@umich.eduvirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN }; 654661Sksewell@umich.edu''' 664661Sksewell@umich.edu 674661Sksewell@umich.edumem_comp_sig_template = ''' 684661Sksewell@umich.eduvirtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN }; 694661Sksewell@umich.edu''' 704661Sksewell@umich.edu 714661Sksewell@umich.edu# Generate a temporary CPU list, including the CheckerCPU if 724661Sksewell@umich.edu# it's enabled. This isn't used for anything else other than StaticInst 733814Ssaidi@eecs.umich.edu# headers. 743814Ssaidi@eecs.umich.edutemp_cpu_list = env['CPU_MODELS'][:] 753814Ssaidi@eecs.umich.edu 763814Ssaidi@eecs.umich.eduif env['USE_CHECKER']: 773814Ssaidi@eecs.umich.edu temp_cpu_list.append('CheckerCPU') 783814Ssaidi@eecs.umich.edu SimObject('CheckerCPU.py') 793814Ssaidi@eecs.umich.edu 803814Ssaidi@eecs.umich.edu# Generate header. 813814Ssaidi@eecs.umich.edudef gen_cpu_exec_signatures(target, source, env): 823814Ssaidi@eecs.umich.edu f = open(str(target[0]), 'w') 833814Ssaidi@eecs.umich.edu print >> f, ''' 844070Ssaidi@eecs.umich.edu#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__ 854070Ssaidi@eecs.umich.edu#define __CPU_STATIC_INST_EXEC_SIGS_HH__ 864070Ssaidi@eecs.umich.edu''' 874070Ssaidi@eecs.umich.edu for cpu in temp_cpu_list: 884070Ssaidi@eecs.umich.edu xc_type = CpuModel.dict[cpu].strings['CPU_exec_context'] 894070Ssaidi@eecs.umich.edu print >> f, exec_sig_template % { 'type' : xc_type } 903814Ssaidi@eecs.umich.edu print >> f, ''' 912SN/A#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__ 922SN/A''' 932SN/A 942SN/A# Generate string that gets printed when header is rebuilt 9510537Sandreas.hansson@arm.comdef gen_sigs_string(target, source, env): 962SN/A return "Generating static_inst_exec_sigs.hh: " \ 972SN/A + ', '.join(temp_cpu_list) 982SN/A 992SN/A# Add command to generate header to environment. 1002SN/Aenv.Command('static_inst_exec_sigs.hh', models_db, 1012SN/A Action(gen_cpu_exec_signatures, gen_sigs_string, 1023422Sgblack@eecs.umich.edu varlist = temp_cpu_list)) 1033422Sgblack@eecs.umich.edu 1043422Sgblack@eecs.umich.eduenv.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER'])) 1053422Sgblack@eecs.umich.eduenv.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS'])) 1063422Sgblack@eecs.umich.edu 1073422Sgblack@eecs.umich.edu# List of suppported CPUs by the Checker. Errors out if USE_CHECKER=True 1083422Sgblack@eecs.umich.edu# and one of these are not being used. 1093422Sgblack@eecs.umich.eduCheckerSupportedCPUList = ['O3CPU', 'OzoneCPU'] 1104425Ssaidi@eecs.umich.edu 1113422Sgblack@eecs.umich.eduSimObject('BaseCPU.py') 1124425Ssaidi@eecs.umich.eduSimObject('FuncUnit.py') 1133422Sgblack@eecs.umich.eduSimObject('ExeTracer.py') 1143422Sgblack@eecs.umich.eduSimObject('IntelTrace.py') 1153422Sgblack@eecs.umich.eduSimObject('NativeTrace.py') 1164661Sksewell@umich.edu 1174661Sksewell@umich.eduSource('activity.cc') 1184661Sksewell@umich.eduSource('base.cc') 1194661Sksewell@umich.eduSource('cpuevent.cc') 1204661Sksewell@umich.eduSource('exetrace.cc') 1214661Sksewell@umich.eduSource('func_unit.cc') 1224661Sksewell@umich.eduSource('inteltrace.cc') 1234661Sksewell@umich.eduSource('nativetrace.cc') 1244661Sksewell@umich.eduSource('pc_event.cc') 1254661Sksewell@umich.eduSource('quiesce_event.cc') 1264661Sksewell@umich.eduSource('static_inst.cc') 1273422Sgblack@eecs.umich.eduSource('simple_thread.cc') 1283422Sgblack@eecs.umich.eduSource('thread_context.cc') 1293422Sgblack@eecs.umich.eduSource('thread_state.cc') 1303422Sgblack@eecs.umich.edu 1313422Sgblack@eecs.umich.eduif env['FULL_SYSTEM']: 1323422Sgblack@eecs.umich.edu SimObject('IntrControl.py') 1333422Sgblack@eecs.umich.edu 1343422Sgblack@eecs.umich.edu Source('intr_control.cc') 1353422Sgblack@eecs.umich.edu Source('profile.cc') 1363422Sgblack@eecs.umich.edu 1373422Sgblack@eecs.umich.edu if env['TARGET_ISA'] == 'sparc': 1384661Sksewell@umich.edu SimObject('LegionTrace.py') 1394661Sksewell@umich.edu Source('legiontrace.cc') 1404661Sksewell@umich.edu 1414661Sksewell@umich.eduif env['USE_CHECKER']: 1424661Sksewell@umich.edu Source('checker/cpu.cc') 1434661Sksewell@umich.edu TraceFlag('Checker') 1444661Sksewell@umich.edu checker_supports = False 1454661Sksewell@umich.edu for i in CheckerSupportedCPUList: 1464103Ssaidi@eecs.umich.edu if i in env['CPU_MODELS']: 1474103Ssaidi@eecs.umich.edu checker_supports = True 1484103Ssaidi@eecs.umich.edu if not checker_supports: 1494103Ssaidi@eecs.umich.edu print "Checker only supports CPU models", 1504103Ssaidi@eecs.umich.edu for i in CheckerSupportedCPUList: 1514103Ssaidi@eecs.umich.edu print i, 1524103Ssaidi@eecs.umich.edu print ", please set USE_CHECKER=False or use one of those CPU models" 1534103Ssaidi@eecs.umich.edu Exit(1) 1544103Ssaidi@eecs.umich.edu 1554244Ssaidi@eecs.umich.eduTraceFlag('Activity') 1564244Ssaidi@eecs.umich.eduTraceFlag('Commit') 1574244Ssaidi@eecs.umich.eduTraceFlag('Context') 1584244Ssaidi@eecs.umich.eduTraceFlag('Decode') 1594244Ssaidi@eecs.umich.eduTraceFlag('DynInst') 1604244Ssaidi@eecs.umich.eduTraceFlag('ExecEnable') 1614103Ssaidi@eecs.umich.eduTraceFlag('ExecCPSeq') 1624103Ssaidi@eecs.umich.eduTraceFlag('ExecEffAddr') 1634103Ssaidi@eecs.umich.eduTraceFlag('ExecFetchSeq') 1646274Sgblack@eecs.umich.eduTraceFlag('ExecOpClass') 1656274Sgblack@eecs.umich.eduTraceFlag('ExecRegDelta') 1666274Sgblack@eecs.umich.eduTraceFlag('ExecResult') 1676274Sgblack@eecs.umich.eduTraceFlag('ExecSpeculative') 1686274Sgblack@eecs.umich.eduTraceFlag('ExecSymbol') 1696274Sgblack@eecs.umich.eduTraceFlag('ExecThread') 1706274Sgblack@eecs.umich.eduTraceFlag('ExecTicks') 1716274Sgblack@eecs.umich.eduTraceFlag('ExecMicro') 1726274Sgblack@eecs.umich.eduTraceFlag('ExecMacro') 1736274Sgblack@eecs.umich.eduTraceFlag('Fetch') 1746274Sgblack@eecs.umich.eduTraceFlag('IntrControl') 1756274Sgblack@eecs.umich.eduTraceFlag('PCEvent') 1766274Sgblack@eecs.umich.eduTraceFlag('Quiesce') 1776274Sgblack@eecs.umich.edu 1786274Sgblack@eecs.umich.eduCompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread', 1796274Sgblack@eecs.umich.edu 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro' ]) 1806274Sgblack@eecs.umich.eduCompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread', 18110400Sstephan.diestelhorst@arm.com 'ExecEffAddr', 'ExecResult', 'ExecMicro' ]) 18210400Sstephan.diestelhorst@arm.com