SConscript revision 6036:f0841ee466a5
12023SN/A# -*- mode:python -*- 22023SN/A 32023SN/A# Copyright (c) 2006 The Regents of The University of Michigan 42023SN/A# All rights reserved. 52023SN/A# 62023SN/A# Redistribution and use in source and binary forms, with or without 72023SN/A# modification, are permitted provided that the following conditions are 82023SN/A# met: redistributions of source code must retain the above copyright 92023SN/A# notice, this list of conditions and the following disclaimer; 102023SN/A# redistributions in binary form must reproduce the above copyright 112023SN/A# notice, this list of conditions and the following disclaimer in the 122023SN/A# documentation and/or other materials provided with the distribution; 132023SN/A# neither the name of the copyright holders nor the names of its 142023SN/A# contributors may be used to endorse or promote products derived from 152023SN/A# this software without specific prior written permission. 162023SN/A# 172023SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182023SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192023SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202023SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212023SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222023SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232023SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242023SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252023SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262023SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272023SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu# 292665Ssaidi@eecs.umich.edu# Authors: Steve Reinhardt 302665Ssaidi@eecs.umich.edu 312023SN/AImport('*') 324202Sbinkertn@umich.edu 332023SN/A################################################################# 344202Sbinkertn@umich.edu# 359022Sgblack@eecs.umich.edu# Generate StaticInst execute() method signatures. 364997Sgblack@eecs.umich.edu# 374202Sbinkertn@umich.edu# There must be one signature for each CPU model compiled in. 388780Sgblack@eecs.umich.edu# Since the set of compiled-in models is flexible, we generate a 398780Sgblack@eecs.umich.edu# header containing the appropriate set of signatures on the fly. 408745Sgblack@eecs.umich.edu# 414997Sgblack@eecs.umich.edu################################################################# 426313Sgblack@eecs.umich.edu 438777Sgblack@eecs.umich.edu# CPU model-specific data is contained in cpu_models.py 448780Sgblack@eecs.umich.edu# Convert to SCons File node to get path handling 458780Sgblack@eecs.umich.edumodels_db = File('cpu_models.py') 468780Sgblack@eecs.umich.edu# slurp in contents of file 478777Sgblack@eecs.umich.eduexecfile(models_db.srcnode().abspath) 484997Sgblack@eecs.umich.edu 498780Sgblack@eecs.umich.edu# Template for execute() signature. 506327Sgblack@eecs.umich.eduexec_sig_template = ''' 514202Sbinkertn@umich.eduvirtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0; 528777Sgblack@eecs.umich.eduvirtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const 538780Sgblack@eecs.umich.edu{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN }; 544997Sgblack@eecs.umich.eduvirtual Fault completeAcc(Packet *pkt, %(type)s *xc, 558780Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 568780Sgblack@eecs.umich.edu{ panic("completeAcc not defined!"); M5_DUMMY_RETURN }; 578780Sgblack@eecs.umich.eduvirtual int memAccSize(%(type)s *xc) 584826Ssaidi@eecs.umich.edu{ panic("memAccSize not defined!"); M5_DUMMY_RETURN }; 598755Sgblack@eecs.umich.edu''' 602023SN/A 618745Sgblack@eecs.umich.edumem_ini_sig_template = ''' 628780Sgblack@eecs.umich.eduvirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN }; 634997Sgblack@eecs.umich.edu''' 644997Sgblack@eecs.umich.edu 652023SN/Amem_comp_sig_template = ''' 664202Sbinkertn@umich.eduvirtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN }; 674202Sbinkertn@umich.edu''' 684202Sbinkertn@umich.edu 694202Sbinkertn@umich.edu# Generate a temporary CPU list, including the CheckerCPU if 704202Sbinkertn@umich.edu# it's enabled. This isn't used for anything else other than StaticInst 714202Sbinkertn@umich.edu# headers. 72temp_cpu_list = env['CPU_MODELS'][:] 73 74if env['USE_CHECKER']: 75 temp_cpu_list.append('CheckerCPU') 76 SimObject('CheckerCPU.py') 77 78# Generate header. 79def gen_cpu_exec_signatures(target, source, env): 80 f = open(str(target[0]), 'w') 81 print >> f, ''' 82#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__ 83#define __CPU_STATIC_INST_EXEC_SIGS_HH__ 84''' 85 for cpu in temp_cpu_list: 86 xc_type = CpuModel.dict[cpu].strings['CPU_exec_context'] 87 print >> f, exec_sig_template % { 'type' : xc_type } 88 print >> f, ''' 89#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__ 90''' 91 92# Generate string that gets printed when header is rebuilt 93def gen_sigs_string(target, source, env): 94 return "Generating static_inst_exec_sigs.hh: " \ 95 + ', '.join(temp_cpu_list) 96 97# Add command to generate header to environment. 98env.Command('static_inst_exec_sigs.hh', models_db, 99 Action(gen_cpu_exec_signatures, gen_sigs_string, 100 varlist = temp_cpu_list)) 101 102env.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER'])) 103env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS'])) 104 105# List of suppported CPUs by the Checker. Errors out if USE_CHECKER=True 106# and one of these are not being used. 107CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU'] 108 109SimObject('BaseCPU.py') 110SimObject('FuncUnit.py') 111SimObject('ExeTracer.py') 112SimObject('IntelTrace.py') 113 114Source('activity.cc') 115Source('base.cc') 116Source('cpuevent.cc') 117Source('exetrace.cc') 118Source('func_unit.cc') 119Source('inteltrace.cc') 120Source('pc_event.cc') 121Source('quiesce_event.cc') 122Source('static_inst.cc') 123Source('simple_thread.cc') 124Source('thread_context.cc') 125Source('thread_state.cc') 126 127if env['FULL_SYSTEM']: 128 SimObject('IntrControl.py') 129 130 Source('intr_control.cc') 131 Source('profile.cc') 132 133 if env['TARGET_ISA'] == 'sparc': 134 SimObject('LegionTrace.py') 135 Source('legiontrace.cc') 136 137if env['TARGET_ISA'] == 'x86': 138 SimObject('NativeTrace.py') 139 Source('nativetrace.cc') 140 141if env['USE_CHECKER']: 142 Source('checker/cpu.cc') 143 TraceFlag('Checker') 144 checker_supports = False 145 for i in CheckerSupportedCPUList: 146 if i in env['CPU_MODELS']: 147 checker_supports = True 148 if not checker_supports: 149 print "Checker only supports CPU models", 150 for i in CheckerSupportedCPUList: 151 print i, 152 print ", please set USE_CHECKER=False or use one of those CPU models" 153 Exit(1) 154 155TraceFlag('Activity') 156TraceFlag('Commit') 157TraceFlag('Context') 158TraceFlag('Decode') 159TraceFlag('DynInst') 160TraceFlag('ExecEnable') 161TraceFlag('ExecCPSeq') 162TraceFlag('ExecEffAddr') 163TraceFlag('ExecFetchSeq') 164TraceFlag('ExecOpClass') 165TraceFlag('ExecRegDelta') 166TraceFlag('ExecResult') 167TraceFlag('ExecSpeculative') 168TraceFlag('ExecSymbol') 169TraceFlag('ExecThread') 170TraceFlag('ExecTicks') 171TraceFlag('ExecMicro') 172TraceFlag('ExecMacro') 173TraceFlag('Fetch') 174TraceFlag('IntrControl') 175TraceFlag('PCEvent') 176TraceFlag('Quiesce') 177 178CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread', 179 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro' ]) 180CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread', 181 'ExecEffAddr', 'ExecResult', 'ExecMicro' ]) 182