SConscript revision 9958
12155SN/A# -*- mode:python -*- 22155SN/A 32155SN/A# Copyright (c) 2006 The Regents of The University of Michigan 42155SN/A# All rights reserved. 52155SN/A# 62155SN/A# Redistribution and use in source and binary forms, with or without 72155SN/A# modification, are permitted provided that the following conditions are 82155SN/A# met: redistributions of source code must retain the above copyright 92155SN/A# notice, this list of conditions and the following disclaimer; 102155SN/A# redistributions in binary form must reproduce the above copyright 112155SN/A# notice, this list of conditions and the following disclaimer in the 122155SN/A# documentation and/or other materials provided with the distribution; 132155SN/A# neither the name of the copyright holders nor the names of its 142155SN/A# contributors may be used to endorse or promote products derived from 152155SN/A# this software without specific prior written permission. 162155SN/A# 172155SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182155SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192155SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202155SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212155SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222155SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232155SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242155SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252155SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262155SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272155SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu# 292665Ssaidi@eecs.umich.edu# Authors: Steve Reinhardt 302155SN/A 314202Sbinkertn@umich.eduImport('*') 322155SN/A 337768SAli.Saidi@ARM.comif env['TARGET_ISA'] == 'null': 347768SAli.Saidi@ARM.com SimObject('IntrControl.py') 357768SAli.Saidi@ARM.com Source('intr_control_noisa.cc') 362178SN/A Return() 372178SN/A 382178SN/A################################################################# 392178SN/A# 402178SN/A# Generate StaticInst execute() method signatures. 412178SN/A# 422178SN/A# There must be one signature for each CPU model compiled in. 432178SN/A# Since the set of compiled-in models is flexible, we generate a 442178SN/A# header containing the appropriate set of signatures on the fly. 452178SN/A# 462178SN/A################################################################# 472155SN/A 485865Sksewell@umich.edu# Template for execute() signature. 496181Sksewell@umich.eduexec_sig_template = ''' 506181Sksewell@umich.eduvirtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0; 515865Sksewell@umich.eduvirtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const 523918Ssaidi@eecs.umich.edu{ panic("eaComp not defined!"); M5_DUMMY_RETURN }; 535865Sksewell@umich.eduvirtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const 542623SN/A{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN }; 553918Ssaidi@eecs.umich.eduvirtual Fault completeAcc(Packet *pkt, %(type)s *xc, 562155SN/A Trace::InstRecord *traceData) const 572155SN/A{ panic("completeAcc not defined!"); M5_DUMMY_RETURN }; 582292SN/A''' 596181Sksewell@umich.edu 606181Sksewell@umich.edumem_ini_sig_template = ''' 613918Ssaidi@eecs.umich.eduvirtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const 622292SN/A{ panic("eaComp not defined!"); M5_DUMMY_RETURN }; 632292SN/Avirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN }; 642292SN/A''' 653918Ssaidi@eecs.umich.edu 662292SN/Amem_comp_sig_template = ''' 672292SN/Avirtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN }; 682766Sktlim@umich.edu''' 692766Sktlim@umich.edu 702766Sktlim@umich.edu# Generate a temporary CPU list, including the CheckerCPU if 712921Sktlim@umich.edu# it's enabled. This isn't used for anything else other than StaticInst 722921Sktlim@umich.edu# headers. 732766Sktlim@umich.edutemp_cpu_list = env['CPU_MODELS'][:] 742766Sktlim@umich.edutemp_cpu_list.append('CheckerCPU') 755529Snate@binkert.orgSimObject('CheckerCPU.py') 762766Sktlim@umich.edu 774762Snate@binkert.org# Generate header. 782155SN/Adef gen_cpu_exec_signatures(target, source, env): 792155SN/A f = open(str(target[0]), 'w') 802155SN/A print >> f, ''' 812155SN/A#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__ 822155SN/A#define __CPU_STATIC_INST_EXEC_SIGS_HH__ 832155SN/A''' 842766Sktlim@umich.edu for cpu in temp_cpu_list: 852155SN/A xc_type = CpuModel.dict[cpu].strings['CPU_exec_context'] 865865Sksewell@umich.edu print >> f, exec_sig_template % { 'type' : xc_type } 872155SN/A print >> f, ''' 882155SN/A#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__ 892155SN/A''' 902155SN/A 912178SN/A# Generate string that gets printed when header is rebuilt 922178SN/Adef gen_sigs_string(target, source, env): 937756SAli.Saidi@ARM.com return " [GENERATE] static_inst_exec_sigs.hh: " \ 942766Sktlim@umich.edu + ', '.join(temp_cpu_list) 952178SN/A 962178SN/A# Add command to generate header to environment. 976994Snate@binkert.orgenv.Command('static_inst_exec_sigs.hh', (), 982178SN/A Action(gen_cpu_exec_signatures, gen_sigs_string, 992766Sktlim@umich.edu varlist = temp_cpu_list)) 1002766Sktlim@umich.edu 1012766Sktlim@umich.eduenv.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS'])) 1022788Sktlim@umich.edu 1032178SN/ASimObject('BaseCPU.py') 1042733Sktlim@umich.eduSimObject('FuncUnit.py') 1052733Sktlim@umich.eduSimObject('ExeTracer.py') 1062817Sksewell@umich.eduSimObject('IntelTrace.py') 1072733Sktlim@umich.eduSimObject('IntrControl.py') 1084486Sbinkertn@umich.eduSimObject('NativeTrace.py') 1094486Sbinkertn@umich.edu 1104776Sgblack@eecs.umich.eduSource('activity.cc') 1114776Sgblack@eecs.umich.eduSource('base.cc') 1128739Sgblack@eecs.umich.eduSource('cpuevent.cc') 1136365Sgblack@eecs.umich.eduSource('exetrace.cc') 1144486Sbinkertn@umich.eduSource('func_unit.cc') 1154202Sbinkertn@umich.eduSource('inteltrace.cc') 1164202Sbinkertn@umich.eduSource('intr_control.cc') 1174202Sbinkertn@umich.eduSource('nativetrace.cc') 1188541Sgblack@eecs.umich.eduSource('pc_event.cc') 1194202Sbinkertn@umich.eduSource('profile.cc') 1204202Sbinkertn@umich.eduSource('quiesce_event.cc') 1214776Sgblack@eecs.umich.eduSource('reg_class.cc') 1228739Sgblack@eecs.umich.eduSource('static_inst.cc') 1236365Sgblack@eecs.umich.eduSource('simple_thread.cc') 1244202Sbinkertn@umich.eduSource('thread_context.cc') 1258777Sgblack@eecs.umich.eduSource('thread_state.cc') 1264202Sbinkertn@umich.edu 1274202Sbinkertn@umich.eduif env['TARGET_ISA'] == 'sparc': 1284202Sbinkertn@umich.edu SimObject('LegionTrace.py') 1295217Ssaidi@eecs.umich.edu Source('legiontrace.cc') 1304202Sbinkertn@umich.edu 1312155SN/ASimObject('DummyChecker.py') 1328793Sgblack@eecs.umich.eduSource('checker/cpu.cc') 1338793Sgblack@eecs.umich.eduSource('dummy_checker.cc') 1348793Sgblack@eecs.umich.eduDebugFlag('Checker') 1354776Sgblack@eecs.umich.edu 1362766Sktlim@umich.eduDebugFlag('Activity') 1378733Sgeoffrey.blake@arm.comDebugFlag('Commit') 1384202Sbinkertn@umich.eduDebugFlag('Context') 1398733Sgeoffrey.blake@arm.comDebugFlag('Decode') 1408335Snate@binkert.orgDebugFlag('DynInst') 1412733Sktlim@umich.eduDebugFlag('ExecEnable', 'Filter: Enable exec tracing (no tracing without this)') 1422733Sktlim@umich.eduDebugFlag('ExecCPSeq', 'Format: Instruction sequence number') 1432733Sktlim@umich.eduDebugFlag('ExecEffAddr', 'Format: Include effective address') 1442733Sktlim@umich.eduDebugFlag('ExecFaulting', 'Trace faulting instructions') 1452733Sktlim@umich.eduDebugFlag('ExecFetchSeq', 'Format: Fetch sequence number') 1462874Sktlim@umich.eduDebugFlag('ExecOpClass', 'Format: Include operand class') 1472874Sktlim@umich.eduDebugFlag('ExecRegDelta') 1482874Sktlim@umich.eduDebugFlag('ExecResult', 'Format: Include results from execution') 1494202Sbinkertn@umich.eduDebugFlag('ExecSpeculative', 'Format: Include a miss-/speculation flag (-/+)') 1502733Sktlim@umich.eduDebugFlag('ExecSymbol', 'Format: Try to include symbol names') 1515192Ssaidi@eecs.umich.eduDebugFlag('ExecThread', 'Format: Include thread ID in trace') 1528335Snate@binkert.orgDebugFlag('ExecTicks', 'Format: Include tick count') 1538335Snate@binkert.orgDebugFlag('ExecMicro', 'Filter: Include microops') 1548335Snate@binkert.orgDebugFlag('ExecMacro', 'Filter: Include macroops') 1558335Snate@binkert.orgDebugFlag('ExecUser', 'Filter: Trace user mode instructions') 1568335Snate@binkert.orgDebugFlag('ExecKernel', 'Filter: Trace kernel mode instructions') 1578335Snate@binkert.orgDebugFlag('ExecAsid', 'Format: Include ASID in trace') 1588335Snate@binkert.orgDebugFlag('Fetch') 1598335Snate@binkert.orgDebugFlag('IntrControl') 1608335Snate@binkert.orgDebugFlag('O3PipeView') 1618335Snate@binkert.orgDebugFlag('PCEvent') 1628335Snate@binkert.orgDebugFlag('Quiesce') 1638335Snate@binkert.org 1648335Snate@binkert.orgCompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr', 1658335Snate@binkert.org 'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta', 1668335Snate@binkert.org 'ExecResult', 'ExecSpeculative', 'ExecSymbol', 'ExecThread', 1678335Snate@binkert.org 'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel', 1688335Snate@binkert.org 'ExecAsid' ]) 1698335Snate@binkert.orgCompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread', 1708335Snate@binkert.org 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting', 1718335Snate@binkert.org 'ExecUser', 'ExecKernel' ]) 1728335Snate@binkert.orgCompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread', 1738335Snate@binkert.org 'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting', 1748335Snate@binkert.org 'ExecUser', 'ExecKernel' ]) 1758335Snate@binkert.org