SConscript revision 9850
16757SAli.Saidi@ARM.com# -*- mode:python -*-
26757SAli.Saidi@ARM.com
310037SARM gem5 Developers# Copyright (c) 2006 The Regents of The University of Michigan
46757SAli.Saidi@ARM.com# All rights reserved.
56757SAli.Saidi@ARM.com#
67090SAli.Saidi@ARM.com# Redistribution and use in source and binary forms, with or without
77090SAli.Saidi@ARM.com# modification, are permitted provided that the following conditions are
87090SAli.Saidi@ARM.com# met: redistributions of source code must retain the above copyright
97090SAli.Saidi@ARM.com# notice, this list of conditions and the following disclaimer;
107090SAli.Saidi@ARM.com# redistributions in binary form must reproduce the above copyright
117090SAli.Saidi@ARM.com# notice, this list of conditions and the following disclaimer in the
127090SAli.Saidi@ARM.com# documentation and/or other materials provided with the distribution;
137090SAli.Saidi@ARM.com# neither the name of the copyright holders nor the names of its
147090SAli.Saidi@ARM.com# contributors may be used to endorse or promote products derived from
156757SAli.Saidi@ARM.com# this software without specific prior written permission.
166757SAli.Saidi@ARM.com#
176757SAli.Saidi@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
186757SAli.Saidi@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
196757SAli.Saidi@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
206757SAli.Saidi@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
216757SAli.Saidi@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
226757SAli.Saidi@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
236757SAli.Saidi@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
246757SAli.Saidi@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
256757SAli.Saidi@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
266757SAli.Saidi@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
276757SAli.Saidi@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
286757SAli.Saidi@ARM.com#
296757SAli.Saidi@ARM.com# Authors: Steve Reinhardt
306757SAli.Saidi@ARM.com
316757SAli.Saidi@ARM.comImport('*')
326757SAli.Saidi@ARM.com
336757SAli.Saidi@ARM.comif env['TARGET_ISA'] == 'null':
346757SAli.Saidi@ARM.com    SimObject('IntrControl.py')
356757SAli.Saidi@ARM.com    Source('intr_control_noisa.cc')
366757SAli.Saidi@ARM.com    Return()
376757SAli.Saidi@ARM.com
386757SAli.Saidi@ARM.com#################################################################
396757SAli.Saidi@ARM.com#
406757SAli.Saidi@ARM.com# Generate StaticInst execute() method signatures.
416757SAli.Saidi@ARM.com#
428739Sgblack@eecs.umich.edu# There must be one signature for each CPU model compiled in.
4310801Srene.dejong@arm.com# Since the set of compiled-in models is flexible, we generate a
4410801Srene.dejong@arm.com# header containing the appropriate set of signatures on the fly.
459525SAndreas.Sandberg@ARM.com#
467584SAli.Saidi@arm.com#################################################################
4710802Srene.dejong@arm.com
4810396Sakash.bagdia@arm.com# Template for execute() signature.
4910916Sandreas.sandberg@arm.comexec_sig_template = '''
5012740Sandreas.sandberg@arm.comvirtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
516757SAli.Saidi@ARM.comvirtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
528282SAli.Saidi@ARM.com{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
537584SAli.Saidi@arm.comvirtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
547584SAli.Saidi@arm.com{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
559525SAndreas.Sandberg@ARM.comvirtual Fault completeAcc(Packet *pkt, %(type)s *xc,
5610801Srene.dejong@arm.com                          Trace::InstRecord *traceData) const
5710037SARM gem5 Developers{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
5813014Sciro.santilli@arm.com'''
5910749Smatt.evans@arm.com
607584SAli.Saidi@arm.commem_ini_sig_template = '''
617753SWilliam.Wang@arm.comvirtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
629646SChris.Emmons@arm.com{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
637754SWilliam.Wang@arm.comvirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
647584SAli.Saidi@arm.com'''
6510916Sandreas.sandberg@arm.com
6611296Sandreas.sandberg@arm.commem_comp_sig_template = '''
677584SAli.Saidi@arm.comvirtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
687584SAli.Saidi@arm.com'''
698869SAli.Saidi@ARM.com
708512Sgeoffrey.blake@arm.com# Generate a temporary CPU list, including the CheckerCPU if
7112077Sgedare@rtems.org# it's enabled.  This isn't used for anything else other than StaticInst
7210037SARM gem5 Developers# headers.
7312740Sandreas.sandberg@arm.comtemp_cpu_list = env['CPU_MODELS'][:]
7410802Srene.dejong@arm.comtemp_cpu_list.append('CheckerCPU')
7510396Sakash.bagdia@arm.comSimObject('CheckerCPU.py')
767584SAli.Saidi@arm.com
778335Snate@binkert.org# Generate header.
7810801Srene.dejong@arm.comdef gen_cpu_exec_signatures(target, source, env):
799646SChris.Emmons@arm.com    f = open(str(target[0]), 'w')
808335Snate@binkert.org    print >> f, '''
8110749Smatt.evans@arm.com#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
828335Snate@binkert.org#define __CPU_STATIC_INST_EXEC_SIGS_HH__
838335Snate@binkert.org'''
849958Smatt.evans@arm.com    for cpu in temp_cpu_list:
8510396Sakash.bagdia@arm.com        xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
8610802Srene.dejong@arm.com        print >> f, exec_sig_template % { 'type' : xc_type }
8710037SARM gem5 Developers    print >> f, '''
8810916Sandreas.sandberg@arm.com#endif  // __CPU_STATIC_INST_EXEC_SIGS_HH__
89'''
90
91# Generate string that gets printed when header is rebuilt
92def gen_sigs_string(target, source, env):
93    return " [GENERATE] static_inst_exec_sigs.hh: " \
94           + ', '.join(temp_cpu_list)
95
96# Add command to generate header to environment.
97env.Command('static_inst_exec_sigs.hh', (),
98            Action(gen_cpu_exec_signatures, gen_sigs_string,
99                   varlist = temp_cpu_list))
100
101env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
102
103SimObject('BaseCPU.py')
104SimObject('FuncUnit.py')
105SimObject('ExeTracer.py')
106SimObject('IntelTrace.py')
107SimObject('IntrControl.py')
108SimObject('NativeTrace.py')
109
110Source('activity.cc')
111Source('base.cc')
112Source('cpuevent.cc')
113Source('exetrace.cc')
114Source('func_unit.cc')
115Source('inteltrace.cc')
116Source('intr_control.cc')
117Source('nativetrace.cc')
118Source('pc_event.cc')
119Source('profile.cc')
120Source('quiesce_event.cc')
121Source('static_inst.cc')
122Source('simple_thread.cc')
123Source('thread_context.cc')
124Source('thread_state.cc')
125
126if env['TARGET_ISA'] == 'sparc':
127    SimObject('LegionTrace.py')
128    Source('legiontrace.cc')
129
130SimObject('DummyChecker.py')
131Source('checker/cpu.cc')
132Source('dummy_checker.cc')
133DebugFlag('Checker')
134
135DebugFlag('Activity')
136DebugFlag('Commit')
137DebugFlag('Context')
138DebugFlag('Decode')
139DebugFlag('DynInst')
140DebugFlag('ExecEnable', 'Filter: Enable exec tracing (no tracing without this)')
141DebugFlag('ExecCPSeq', 'Format: Instruction sequence number')
142DebugFlag('ExecEffAddr', 'Format: Include effective address')
143DebugFlag('ExecFaulting', 'Trace faulting instructions')
144DebugFlag('ExecFetchSeq', 'Format: Fetch sequence number')
145DebugFlag('ExecOpClass', 'Format: Include operand class')
146DebugFlag('ExecRegDelta')
147DebugFlag('ExecResult', 'Format: Include results from execution')
148DebugFlag('ExecSpeculative', 'Format: Include a miss-/speculation flag (-/+)')
149DebugFlag('ExecSymbol', 'Format: Try to include symbol names')
150DebugFlag('ExecThread', 'Format: Include thread ID in trace')
151DebugFlag('ExecTicks', 'Format: Include tick count')
152DebugFlag('ExecMicro', 'Filter: Include microops')
153DebugFlag('ExecMacro', 'Filter: Include macroops')
154DebugFlag('ExecUser', 'Filter: Trace user mode instructions')
155DebugFlag('ExecKernel', 'Filter: Trace kernel mode instructions')
156DebugFlag('ExecAsid', 'Format: Include ASID in trace')
157DebugFlag('Fetch')
158DebugFlag('IntrControl')
159DebugFlag('O3PipeView')
160DebugFlag('PCEvent')
161DebugFlag('Quiesce')
162
163CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
164    'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
165    'ExecResult', 'ExecSpeculative', 'ExecSymbol', 'ExecThread',
166    'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
167    'ExecAsid' ])
168CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
169    'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting',
170    'ExecUser', 'ExecKernel' ])
171CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
172    'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting',
173    'ExecUser', 'ExecKernel' ])
174