SConscript revision 8335
1955SN/A# -*- mode:python -*-
2955SN/A
39812Sandreas.hansson@arm.com# Copyright (c) 2006 The Regents of The University of Michigan
49812Sandreas.hansson@arm.com# All rights reserved.
59812Sandreas.hansson@arm.com#
69812Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without
79812Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are
89812Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright
99812Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer;
109812Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright
119812Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the
129812Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution;
139812Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its
149812Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from
157816Ssteve.reinhardt@amd.com# this software without specific prior written permission.
165871Snate@binkert.org#
171762SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18955SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19955SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20955SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21955SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22955SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23955SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24955SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25955SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26955SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27955SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28955SN/A#
29955SN/A# Authors: Steve Reinhardt
30955SN/A
31955SN/AImport('*')
32955SN/A
33955SN/Aif env['TARGET_ISA'] == 'no':
34955SN/A    Return()
35955SN/A
36955SN/A#################################################################
37955SN/A#
38955SN/A# Generate StaticInst execute() method signatures.
39955SN/A#
40955SN/A# There must be one signature for each CPU model compiled in.
41955SN/A# Since the set of compiled-in models is flexible, we generate a
422665Ssaidi@eecs.umich.edu# header containing the appropriate set of signatures on the fly.
432665Ssaidi@eecs.umich.edu#
445863Snate@binkert.org#################################################################
45955SN/A
46955SN/A# Template for execute() signature.
47955SN/Aexec_sig_template = '''
48955SN/Avirtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
49955SN/Avirtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
508878Ssteve.reinhardt@amd.com{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
512632Sstever@eecs.umich.eduvirtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
528878Ssteve.reinhardt@amd.com{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
532632Sstever@eecs.umich.eduvirtual Fault completeAcc(Packet *pkt, %(type)s *xc,
54955SN/A                          Trace::InstRecord *traceData) const
558878Ssteve.reinhardt@amd.com{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
562632Sstever@eecs.umich.edu'''
572761Sstever@eecs.umich.edu
582632Sstever@eecs.umich.edumem_ini_sig_template = '''
592632Sstever@eecs.umich.eduvirtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
602632Sstever@eecs.umich.edu{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
612761Sstever@eecs.umich.eduvirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
622761Sstever@eecs.umich.edu'''
632761Sstever@eecs.umich.edu
648878Ssteve.reinhardt@amd.commem_comp_sig_template = '''
658878Ssteve.reinhardt@amd.comvirtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
662761Sstever@eecs.umich.edu'''
672761Sstever@eecs.umich.edu
682761Sstever@eecs.umich.edu# Generate a temporary CPU list, including the CheckerCPU if
692761Sstever@eecs.umich.edu# it's enabled.  This isn't used for anything else other than StaticInst
702761Sstever@eecs.umich.edu# headers.
718878Ssteve.reinhardt@amd.comtemp_cpu_list = env['CPU_MODELS'][:]
728878Ssteve.reinhardt@amd.com
732632Sstever@eecs.umich.eduif env['USE_CHECKER']:
742632Sstever@eecs.umich.edu    temp_cpu_list.append('CheckerCPU')
758878Ssteve.reinhardt@amd.com    SimObject('CheckerCPU.py')
768878Ssteve.reinhardt@amd.com
772632Sstever@eecs.umich.edu# Generate header.
78955SN/Adef gen_cpu_exec_signatures(target, source, env):
79955SN/A    f = open(str(target[0]), 'w')
80955SN/A    print >> f, '''
815863Snate@binkert.org#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
825863Snate@binkert.org#define __CPU_STATIC_INST_EXEC_SIGS_HH__
835863Snate@binkert.org'''
845863Snate@binkert.org    for cpu in temp_cpu_list:
855863Snate@binkert.org        xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
865863Snate@binkert.org        print >> f, exec_sig_template % { 'type' : xc_type }
875863Snate@binkert.org    print >> f, '''
885863Snate@binkert.org#endif  // __CPU_STATIC_INST_EXEC_SIGS_HH__
895863Snate@binkert.org'''
905863Snate@binkert.org
915863Snate@binkert.org# Generate string that gets printed when header is rebuilt
928878Ssteve.reinhardt@amd.comdef gen_sigs_string(target, source, env):
935863Snate@binkert.org    return " [GENERATE] static_inst_exec_sigs.hh: " \
945863Snate@binkert.org           + ', '.join(temp_cpu_list)
955863Snate@binkert.org
969812Sandreas.hansson@arm.com# Add command to generate header to environment.
979812Sandreas.hansson@arm.comenv.Command('static_inst_exec_sigs.hh', (),
985863Snate@binkert.org            Action(gen_cpu_exec_signatures, gen_sigs_string,
999812Sandreas.hansson@arm.com                   varlist = temp_cpu_list))
1005863Snate@binkert.org
1015863Snate@binkert.orgenv.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER']))
1025863Snate@binkert.orgenv.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
1039812Sandreas.hansson@arm.com
1049812Sandreas.hansson@arm.com# List of suppported CPUs by the Checker.  Errors out if USE_CHECKER=True
1055863Snate@binkert.org# and one of these are not being used.
1065863Snate@binkert.orgCheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
1078878Ssteve.reinhardt@amd.com
1085863Snate@binkert.orgSimObject('BaseCPU.py')
1095863Snate@binkert.orgSimObject('FuncUnit.py')
1105863Snate@binkert.orgSimObject('ExeTracer.py')
1116654Snate@binkert.orgSimObject('IntelTrace.py')
112955SN/ASimObject('NativeTrace.py')
1135396Ssaidi@eecs.umich.edu
1145863Snate@binkert.orgSource('activity.cc')
1155863Snate@binkert.orgSource('base.cc')
1164202Sbinkertn@umich.eduSource('cpuevent.cc')
1175863Snate@binkert.orgSource('exetrace.cc')
1185863Snate@binkert.orgSource('func_unit.cc')
1195863Snate@binkert.orgSource('inteltrace.cc')
1205863Snate@binkert.orgSource('nativetrace.cc')
121955SN/ASource('pc_event.cc')
1226654Snate@binkert.orgSource('quiesce_event.cc')
1235273Sstever@gmail.comSource('static_inst.cc')
1245871Snate@binkert.orgSource('simple_thread.cc')
1255273Sstever@gmail.comSource('thread_context.cc')
1266655Snate@binkert.orgSource('thread_state.cc')
1278878Ssteve.reinhardt@amd.com
1286655Snate@binkert.orgif env['FULL_SYSTEM']:
1296655Snate@binkert.org    SimObject('IntrControl.py')
1309219Spower.jg@gmail.com
1316655Snate@binkert.org    Source('intr_control.cc')
1325871Snate@binkert.org    Source('profile.cc')
1336654Snate@binkert.org
1348947Sandreas.hansson@arm.com    if env['TARGET_ISA'] == 'sparc':
1355396Ssaidi@eecs.umich.edu        SimObject('LegionTrace.py')
1368120Sgblack@eecs.umich.edu        Source('legiontrace.cc')
1378120Sgblack@eecs.umich.edu
1388120Sgblack@eecs.umich.eduif env['USE_CHECKER']:
1398120Sgblack@eecs.umich.edu    Source('checker/cpu.cc')
1408120Sgblack@eecs.umich.edu    DebugFlag('Checker')
1418120Sgblack@eecs.umich.edu    checker_supports = False
1428120Sgblack@eecs.umich.edu    for i in CheckerSupportedCPUList:
1438120Sgblack@eecs.umich.edu        if i in env['CPU_MODELS']:
1448879Ssteve.reinhardt@amd.com            checker_supports = True
1458879Ssteve.reinhardt@amd.com    if not checker_supports:
1468879Ssteve.reinhardt@amd.com        print "Checker only supports CPU models",
1478879Ssteve.reinhardt@amd.com        for i in CheckerSupportedCPUList:
1488879Ssteve.reinhardt@amd.com            print i,
1498879Ssteve.reinhardt@amd.com        print ", please set USE_CHECKER=False or use one of those CPU models"
1508879Ssteve.reinhardt@amd.com        Exit(1)
1518879Ssteve.reinhardt@amd.com
1528879Ssteve.reinhardt@amd.comDebugFlag('Activity')
1538879Ssteve.reinhardt@amd.comDebugFlag('Commit')
1548879Ssteve.reinhardt@amd.comDebugFlag('Context')
1558879Ssteve.reinhardt@amd.comDebugFlag('Decode')
1568879Ssteve.reinhardt@amd.comDebugFlag('DynInst')
1578120Sgblack@eecs.umich.eduDebugFlag('ExecEnable')
1588120Sgblack@eecs.umich.eduDebugFlag('ExecCPSeq')
1598120Sgblack@eecs.umich.eduDebugFlag('ExecEffAddr')
1608120Sgblack@eecs.umich.eduDebugFlag('ExecFaulting', 'Trace faulting instructions')
1618120Sgblack@eecs.umich.eduDebugFlag('ExecFetchSeq')
1628120Sgblack@eecs.umich.eduDebugFlag('ExecOpClass')
1638120Sgblack@eecs.umich.eduDebugFlag('ExecRegDelta')
1648120Sgblack@eecs.umich.eduDebugFlag('ExecResult')
1658120Sgblack@eecs.umich.eduDebugFlag('ExecSpeculative')
1668120Sgblack@eecs.umich.eduDebugFlag('ExecSymbol')
1678120Sgblack@eecs.umich.eduDebugFlag('ExecThread')
1688120Sgblack@eecs.umich.eduDebugFlag('ExecTicks')
1698120Sgblack@eecs.umich.eduDebugFlag('ExecMicro')
1708120Sgblack@eecs.umich.eduDebugFlag('ExecMacro')
1718879Ssteve.reinhardt@amd.comDebugFlag('ExecUser')
1728879Ssteve.reinhardt@amd.comDebugFlag('ExecKernel')
1738879Ssteve.reinhardt@amd.comDebugFlag('ExecAsid')
1748879Ssteve.reinhardt@amd.comDebugFlag('Fetch')
1758879Ssteve.reinhardt@amd.comDebugFlag('IntrControl')
1768879Ssteve.reinhardt@amd.comDebugFlag('PCEvent')
1778879Ssteve.reinhardt@amd.comDebugFlag('Quiesce')
1788879Ssteve.reinhardt@amd.com
1799227Sandreas.hansson@arm.comCompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
1809227Sandreas.hansson@arm.com    'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
1818879Ssteve.reinhardt@amd.com    'ExecResult', 'ExecSpeculative', 'ExecSymbol', 'ExecThread',
1828879Ssteve.reinhardt@amd.com    'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
1838879Ssteve.reinhardt@amd.com    'ExecAsid' ])
1848879Ssteve.reinhardt@amd.comCompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
1858120Sgblack@eecs.umich.edu    'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting',
1868947Sandreas.hansson@arm.com    'ExecUser', 'ExecKernel' ])
1877816Ssteve.reinhardt@amd.comCompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
1885871Snate@binkert.org    'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting',
1895871Snate@binkert.org    'ExecUser', 'ExecKernel' ])
1906121Snate@binkert.org