SConscript revision 7768 
15584Snate@binkert.org# -*- mode:python -*-
25584Snate@binkert.org
35584Snate@binkert.org# Copyright (c) 2006 The Regents of The University of Michigan
45584Snate@binkert.org# All rights reserved.
55584Snate@binkert.org#
65584Snate@binkert.org# Redistribution and use in source and binary forms, with or without
75584Snate@binkert.org# modification, are permitted provided that the following conditions are
85584Snate@binkert.org# met: redistributions of source code must retain the above copyright
95584Snate@binkert.org# notice, this list of conditions and the following disclaimer;
105584Snate@binkert.org# redistributions in binary form must reproduce the above copyright
115584Snate@binkert.org# notice, this list of conditions and the following disclaimer in the
125584Snate@binkert.org# documentation and/or other materials provided with the distribution;
135584Snate@binkert.org# neither the name of the copyright holders nor the names of its
145584Snate@binkert.org# contributors may be used to endorse or promote products derived from
155584Snate@binkert.org# this software without specific prior written permission.
165584Snate@binkert.org#
175584Snate@binkert.org# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
185584Snate@binkert.org# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
195584Snate@binkert.org# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
205584Snate@binkert.org# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
215584Snate@binkert.org# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
225584Snate@binkert.org# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
235584Snate@binkert.org# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
245584Snate@binkert.org# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
255584Snate@binkert.org# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
265584Snate@binkert.org# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
275584Snate@binkert.org# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
285584Snate@binkert.org#
295584Snate@binkert.org# Authors: Steve Reinhardt
305584Snate@binkert.org
315584Snate@binkert.orgImport('*')
325584Snate@binkert.org
337768SAli.Saidi@ARM.comif env['TARGET_ISA'] == 'no':
347768SAli.Saidi@ARM.com    Return()
357768SAli.Saidi@ARM.com
367841Sgblack@eecs.umich.edu#################################################################
377841Sgblack@eecs.umich.edu#
385584Snate@binkert.org# Generate StaticInst execute() method signatures.
395584Snate@binkert.org#
405584Snate@binkert.org# There must be one signature for each CPU model compiled in.
415584Snate@binkert.org# Since the set of compiled-in models is flexible, we generate a
425584Snate@binkert.org# header containing the appropriate set of signatures on the fly.
435584Snate@binkert.org#
445584Snate@binkert.org#################################################################
455584Snate@binkert.org
465584Snate@binkert.org# Template for execute() signature.
475584Snate@binkert.orgexec_sig_template = '''
485584Snate@binkert.orgvirtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
497824Sgblack@eecs.umich.eduvirtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
505584Snate@binkert.org{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
518235Snate@binkert.orgvirtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
528235Snate@binkert.org{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
538235Snate@binkert.orgvirtual Fault completeAcc(Packet *pkt, %(type)s *xc,
548235Snate@binkert.org                          Trace::InstRecord *traceData) const
558235Snate@binkert.org{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
565584Snate@binkert.org'''
575584Snate@binkert.org
585584Snate@binkert.orgmem_ini_sig_template = '''
59virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
60{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
61virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
62'''
63
64mem_comp_sig_template = '''
65virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
66'''
67
68# Generate a temporary CPU list, including the CheckerCPU if
69# it's enabled.  This isn't used for anything else other than StaticInst
70# headers.
71temp_cpu_list = env['CPU_MODELS'][:]
72
73if env['USE_CHECKER']:
74    temp_cpu_list.append('CheckerCPU')
75    SimObject('CheckerCPU.py')
76
77# Generate header.
78def gen_cpu_exec_signatures(target, source, env):
79    f = open(str(target[0]), 'w')
80    print >> f, '''
81#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
82#define __CPU_STATIC_INST_EXEC_SIGS_HH__
83'''
84    for cpu in temp_cpu_list:
85        xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
86        print >> f, exec_sig_template % { 'type' : xc_type }
87    print >> f, '''
88#endif  // __CPU_STATIC_INST_EXEC_SIGS_HH__
89'''
90
91# Generate string that gets printed when header is rebuilt
92def gen_sigs_string(target, source, env):
93    return " [GENERATE] static_inst_exec_sigs.hh: " \
94           + ', '.join(temp_cpu_list)
95
96# Add command to generate header to environment.
97env.Command('static_inst_exec_sigs.hh', (),
98            Action(gen_cpu_exec_signatures, gen_sigs_string,
99                   varlist = temp_cpu_list))
100
101env.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER']))
102env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
103
104# List of suppported CPUs by the Checker.  Errors out if USE_CHECKER=True
105# and one of these are not being used.
106CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
107
108SimObject('BaseCPU.py')
109SimObject('FuncUnit.py')
110SimObject('ExeTracer.py')
111SimObject('IntelTrace.py')
112SimObject('NativeTrace.py')
113
114Source('activity.cc')
115Source('base.cc')
116Source('cpuevent.cc')
117Source('exetrace.cc')
118Source('func_unit.cc')
119Source('inteltrace.cc')
120Source('nativetrace.cc')
121Source('pc_event.cc')
122Source('quiesce_event.cc')
123Source('static_inst.cc')
124Source('simple_thread.cc')
125Source('thread_context.cc')
126Source('thread_state.cc')
127
128if env['FULL_SYSTEM']:
129    SimObject('IntrControl.py')
130
131    Source('intr_control.cc')
132    Source('profile.cc')
133
134    if env['TARGET_ISA'] == 'sparc':
135        SimObject('LegionTrace.py')
136        Source('legiontrace.cc')
137
138if env['USE_CHECKER']:
139    Source('checker/cpu.cc')
140    TraceFlag('Checker')
141    checker_supports = False
142    for i in CheckerSupportedCPUList:
143        if i in env['CPU_MODELS']:
144            checker_supports = True
145    if not checker_supports:
146        print "Checker only supports CPU models",
147        for i in CheckerSupportedCPUList:
148            print i,
149        print ", please set USE_CHECKER=False or use one of those CPU models"
150        Exit(1)
151
152TraceFlag('Activity')
153TraceFlag('Commit')
154TraceFlag('Context')
155TraceFlag('Decode')
156TraceFlag('DynInst')
157TraceFlag('ExecEnable')
158TraceFlag('ExecCPSeq')
159TraceFlag('ExecEffAddr')
160TraceFlag('ExecFaulting', 'Trace faulting instructions')
161TraceFlag('ExecFetchSeq')
162TraceFlag('ExecOpClass')
163TraceFlag('ExecRegDelta')
164TraceFlag('ExecResult')
165TraceFlag('ExecSpeculative')
166TraceFlag('ExecSymbol')
167TraceFlag('ExecThread')
168TraceFlag('ExecTicks')
169TraceFlag('ExecMicro')
170TraceFlag('ExecMacro')
171TraceFlag('Fetch')
172TraceFlag('IntrControl')
173TraceFlag('PCEvent')
174TraceFlag('Quiesce')
175
176CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
177    'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting' ])
178CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
179    'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting' ])
180