SConscript revision 7754
12155SN/A# -*- mode:python -*-
22155SN/A
32155SN/A# Copyright (c) 2006 The Regents of The University of Michigan
42155SN/A# All rights reserved.
52155SN/A#
62155SN/A# Redistribution and use in source and binary forms, with or without
72155SN/A# modification, are permitted provided that the following conditions are
82155SN/A# met: redistributions of source code must retain the above copyright
92155SN/A# notice, this list of conditions and the following disclaimer;
102155SN/A# redistributions in binary form must reproduce the above copyright
112155SN/A# notice, this list of conditions and the following disclaimer in the
122155SN/A# documentation and/or other materials provided with the distribution;
132155SN/A# neither the name of the copyright holders nor the names of its
142155SN/A# contributors may be used to endorse or promote products derived from
152155SN/A# this software without specific prior written permission.
162155SN/A#
172155SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
182155SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
192155SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
202155SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
212155SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
222155SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
232155SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
242155SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
252155SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
262155SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
272155SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
282665Ssaidi@eecs.umich.edu#
292665Ssaidi@eecs.umich.edu# Authors: Steve Reinhardt
302155SN/A
314202Sbinkertn@umich.eduImport('*')
322155SN/A
339850Sandreas.hansson@arm.com#################################################################
349850Sandreas.hansson@arm.com#
359850Sandreas.hansson@arm.com# Generate StaticInst execute() method signatures.
367768SAli.Saidi@ARM.com#
377768SAli.Saidi@ARM.com# There must be one signature for each CPU model compiled in.
3810695SAli.Saidi@ARM.com# Since the set of compiled-in models is flexible, we generate a
3910695SAli.Saidi@ARM.com# header containing the appropriate set of signatures on the fly.
4010695SAli.Saidi@ARM.com#
4110695SAli.Saidi@ARM.com#################################################################
4210695SAli.Saidi@ARM.com
438887Sgeoffrey.blake@arm.com# Template for execute() signature.
442766Sktlim@umich.eduexec_sig_template = '''
454486Sbinkertn@umich.eduvirtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
4610663SAli.Saidi@ARM.comvirtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
474486Sbinkertn@umich.edu{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
488739Sgblack@eecs.umich.eduvirtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
4910259SAndrew.Bardsley@arm.com{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
504486Sbinkertn@umich.eduvirtual Fault completeAcc(Packet *pkt, %(type)s *xc,
514202Sbinkertn@umich.edu                          Trace::InstRecord *traceData) const
524202Sbinkertn@umich.edu{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
534202Sbinkertn@umich.edu'''
544202Sbinkertn@umich.edu
5510319SAndreas.Sandberg@ARM.commem_ini_sig_template = '''
564202Sbinkertn@umich.eduvirtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
574776Sgblack@eecs.umich.edu{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
588739Sgblack@eecs.umich.eduvirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
596365Sgblack@eecs.umich.edu'''
604202Sbinkertn@umich.edu
618777Sgblack@eecs.umich.edumem_comp_sig_template = '''
624202Sbinkertn@umich.eduvirtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
639913Ssteve.reinhardt@amd.com'''
644202Sbinkertn@umich.edu
654202Sbinkertn@umich.edu# Generate a temporary CPU list, including the CheckerCPU if
665217Ssaidi@eecs.umich.edu# it's enabled.  This isn't used for anything else other than StaticInst
674202Sbinkertn@umich.edu# headers.
6810259SAndrew.Bardsley@arm.comtemp_cpu_list = env['CPU_MODELS'][:]
692155SN/A
708887Sgeoffrey.blake@arm.comif env['USE_CHECKER']:
7110201SAndrew.Bardsley@arm.com    temp_cpu_list.append('CheckerCPU')
728887Sgeoffrey.blake@arm.com    SimObject('CheckerCPU.py')
739340SAndreas.Sandberg@arm.com
748887Sgeoffrey.blake@arm.com# Generate header.
755192Ssaidi@eecs.umich.edudef gen_cpu_exec_signatures(target, source, env):
768335Snate@binkert.org    f = open(str(target[0]), 'w')
778335Snate@binkert.org    print >> f, '''
788335Snate@binkert.org#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
798335Snate@binkert.org#define __CPU_STATIC_INST_EXEC_SIGS_HH__
808335Snate@binkert.org'''
819534SAndreas.Sandberg@ARM.com    for cpu in temp_cpu_list:
829534SAndreas.Sandberg@ARM.com        xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
839534SAndreas.Sandberg@ARM.com        print >> f, exec_sig_template % { 'type' : xc_type }
848335Snate@binkert.org    print >> f, '''
859534SAndreas.Sandberg@ARM.com#endif  // __CPU_STATIC_INST_EXEC_SIGS_HH__
869534SAndreas.Sandberg@ARM.com'''
878335Snate@binkert.org
889534SAndreas.Sandberg@ARM.com# Generate string that gets printed when header is rebuilt
899534SAndreas.Sandberg@ARM.comdef gen_sigs_string(target, source, env):
909534SAndreas.Sandberg@ARM.com    return "Generating static_inst_exec_sigs.hh: " \
919534SAndreas.Sandberg@ARM.com           + ', '.join(temp_cpu_list)
929534SAndreas.Sandberg@ARM.com
939534SAndreas.Sandberg@ARM.com# Add command to generate header to environment.
949534SAndreas.Sandberg@ARM.comenv.Command('static_inst_exec_sigs.hh', (),
959534SAndreas.Sandberg@ARM.com            Action(gen_cpu_exec_signatures, gen_sigs_string,
969534SAndreas.Sandberg@ARM.com                   varlist = temp_cpu_list))
9710383Smitch.hayenga@arm.com
988335Snate@binkert.orgenv.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER']))
998335Snate@binkert.orgenv.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
1008471SGiacomo.Gabrielli@arm.com
1018335Snate@binkert.org# List of suppported CPUs by the Checker.  Errors out if USE_CHECKER=True
1028335Snate@binkert.org# and one of these are not being used.
10310529Smorr@cs.wisc.eduCheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
1045192Ssaidi@eecs.umich.edu
1058232Snate@binkert.orgSimObject('BaseCPU.py')
1068232Snate@binkert.orgSimObject('FuncUnit.py')
10710664SAli.Saidi@ARM.comSimObject('ExeTracer.py')
1088300Schander.sudanthi@arm.comSimObject('IntelTrace.py')
10910383Smitch.hayenga@arm.comSimObject('NativeTrace.py')
1105192Ssaidi@eecs.umich.edu
11111162Ssteve.reinhardt@amd.comSource('activity.cc')
11211162Ssteve.reinhardt@amd.comSource('base.cc')
11311162Ssteve.reinhardt@amd.comSource('cpuevent.cc')
11411162Ssteve.reinhardt@amd.comSource('exetrace.cc')
1158300Schander.sudanthi@arm.comSource('func_unit.cc')
116Source('inteltrace.cc')
117Source('nativetrace.cc')
118Source('pc_event.cc')
119Source('quiesce_event.cc')
120Source('static_inst.cc')
121Source('simple_thread.cc')
122Source('thread_context.cc')
123Source('thread_state.cc')
124
125if env['FULL_SYSTEM']:
126    SimObject('IntrControl.py')
127
128    Source('intr_control.cc')
129    Source('profile.cc')
130
131    if env['TARGET_ISA'] == 'sparc':
132        SimObject('LegionTrace.py')
133        Source('legiontrace.cc')
134
135if env['USE_CHECKER']:
136    Source('checker/cpu.cc')
137    TraceFlag('Checker')
138    checker_supports = False
139    for i in CheckerSupportedCPUList:
140        if i in env['CPU_MODELS']:
141            checker_supports = True
142    if not checker_supports:
143        print "Checker only supports CPU models",
144        for i in CheckerSupportedCPUList:
145            print i,
146        print ", please set USE_CHECKER=False or use one of those CPU models"
147        Exit(1)
148
149TraceFlag('Activity')
150TraceFlag('Commit')
151TraceFlag('Context')
152TraceFlag('Decode')
153TraceFlag('DynInst')
154TraceFlag('ExecEnable')
155TraceFlag('ExecCPSeq')
156TraceFlag('ExecEffAddr')
157TraceFlag('ExecFaulting', 'Trace faulting instructions')
158TraceFlag('ExecFetchSeq')
159TraceFlag('ExecOpClass')
160TraceFlag('ExecRegDelta')
161TraceFlag('ExecResult')
162TraceFlag('ExecSpeculative')
163TraceFlag('ExecSymbol')
164TraceFlag('ExecThread')
165TraceFlag('ExecTicks')
166TraceFlag('ExecMicro')
167TraceFlag('ExecMacro')
168TraceFlag('Fetch')
169TraceFlag('IntrControl')
170TraceFlag('PCEvent')
171TraceFlag('Quiesce')
172
173CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
174    'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting' ])
175CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
176    'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting' ])
177