SConscript revision 7624
12155SN/A# -*- mode:python -*- 22155SN/A 32155SN/A# Copyright (c) 2006 The Regents of The University of Michigan 42155SN/A# All rights reserved. 52155SN/A# 62155SN/A# Redistribution and use in source and binary forms, with or without 72155SN/A# modification, are permitted provided that the following conditions are 82155SN/A# met: redistributions of source code must retain the above copyright 92155SN/A# notice, this list of conditions and the following disclaimer; 102155SN/A# redistributions in binary form must reproduce the above copyright 112155SN/A# notice, this list of conditions and the following disclaimer in the 122155SN/A# documentation and/or other materials provided with the distribution; 132155SN/A# neither the name of the copyright holders nor the names of its 142155SN/A# contributors may be used to endorse or promote products derived from 152155SN/A# this software without specific prior written permission. 162155SN/A# 172155SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182155SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192155SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202155SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212155SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222155SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232155SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242155SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252155SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262155SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272155SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu# 292665Ssaidi@eecs.umich.edu# Authors: Steve Reinhardt 302155SN/A 314202Sbinkertn@umich.eduImport('*') 322155SN/A 337768SAli.Saidi@ARM.com################################################################# 347768SAli.Saidi@ARM.com# 357768SAli.Saidi@ARM.com# Generate StaticInst execute() method signatures. 362178SN/A# 372178SN/A# There must be one signature for each CPU model compiled in. 382178SN/A# Since the set of compiled-in models is flexible, we generate a 392178SN/A# header containing the appropriate set of signatures on the fly. 402178SN/A# 412178SN/A################################################################# 422178SN/A 432178SN/A# Template for execute() signature. 442178SN/Aexec_sig_template = ''' 452178SN/Avirtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0; 462178SN/Avirtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const 472155SN/A{ panic("eaComp not defined!"); M5_DUMMY_RETURN }; 485865Sksewell@umich.eduvirtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const 496181Sksewell@umich.edu{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN }; 506181Sksewell@umich.eduvirtual Fault completeAcc(Packet *pkt, %(type)s *xc, 515865Sksewell@umich.edu Trace::InstRecord *traceData) const 523918Ssaidi@eecs.umich.edu{ panic("completeAcc not defined!"); M5_DUMMY_RETURN }; 535865Sksewell@umich.edu''' 542623SN/A 553918Ssaidi@eecs.umich.edumem_ini_sig_template = ''' 562155SN/Avirtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const 572155SN/A{ panic("eaComp not defined!"); M5_DUMMY_RETURN }; 582292SN/Avirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN }; 596181Sksewell@umich.edu''' 606181Sksewell@umich.edu 613918Ssaidi@eecs.umich.edumem_comp_sig_template = ''' 622292SN/Avirtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN }; 632292SN/A''' 642292SN/A 653918Ssaidi@eecs.umich.edu# Generate a temporary CPU list, including the CheckerCPU if 662292SN/A# it's enabled. This isn't used for anything else other than StaticInst 672292SN/A# headers. 682766Sktlim@umich.edutemp_cpu_list = env['CPU_MODELS'][:] 692766Sktlim@umich.edu 702766Sktlim@umich.eduif env['USE_CHECKER']: 712921Sktlim@umich.edu temp_cpu_list.append('CheckerCPU') 722921Sktlim@umich.edu SimObject('CheckerCPU.py') 732766Sktlim@umich.edu 742766Sktlim@umich.edu# Generate header. 755529Snate@binkert.orgdef gen_cpu_exec_signatures(target, source, env): 762766Sktlim@umich.edu f = open(str(target[0]), 'w') 774762Snate@binkert.org print >> f, ''' 782155SN/A#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__ 792155SN/A#define __CPU_STATIC_INST_EXEC_SIGS_HH__ 802155SN/A''' 812155SN/A for cpu in temp_cpu_list: 822155SN/A xc_type = CpuModel.dict[cpu].strings['CPU_exec_context'] 832155SN/A print >> f, exec_sig_template % { 'type' : xc_type } 842766Sktlim@umich.edu print >> f, ''' 852155SN/A#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__ 865865Sksewell@umich.edu''' 872155SN/A 882155SN/A# Generate string that gets printed when header is rebuilt 892155SN/Adef gen_sigs_string(target, source, env): 902155SN/A return "Generating static_inst_exec_sigs.hh: " \ 912178SN/A + ', '.join(temp_cpu_list) 922178SN/A 937756SAli.Saidi@ARM.com# Add command to generate header to environment. 942766Sktlim@umich.eduenv.Command('static_inst_exec_sigs.hh', (), 952178SN/A Action(gen_cpu_exec_signatures, gen_sigs_string, 962178SN/A varlist = temp_cpu_list)) 976994Snate@binkert.org 982178SN/Aenv.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER'])) 992766Sktlim@umich.eduenv.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS'])) 1002766Sktlim@umich.edu 1012766Sktlim@umich.edu# List of suppported CPUs by the Checker. Errors out if USE_CHECKER=True 1022788Sktlim@umich.edu# and one of these are not being used. 1032178SN/ACheckerSupportedCPUList = ['O3CPU', 'OzoneCPU'] 1042733Sktlim@umich.edu 1052733Sktlim@umich.eduSimObject('BaseCPU.py') 1062817Sksewell@umich.eduSimObject('FuncUnit.py') 1072733Sktlim@umich.eduSimObject('ExeTracer.py') 1084486Sbinkertn@umich.eduSimObject('IntelTrace.py') 1094486Sbinkertn@umich.eduSimObject('NativeTrace.py') 1104776Sgblack@eecs.umich.edu 1114776Sgblack@eecs.umich.eduSource('activity.cc') 1128739Sgblack@eecs.umich.eduSource('base.cc') 1136365Sgblack@eecs.umich.eduSource('cpuevent.cc') 1144486Sbinkertn@umich.eduSource('exetrace.cc') 1154202Sbinkertn@umich.eduSource('func_unit.cc') 1164202Sbinkertn@umich.eduSource('inteltrace.cc') 1174202Sbinkertn@umich.eduSource('nativetrace.cc') 1188541Sgblack@eecs.umich.eduSource('pc_event.cc') 1194202Sbinkertn@umich.eduSource('quiesce_event.cc') 1204202Sbinkertn@umich.eduSource('static_inst.cc') 1214776Sgblack@eecs.umich.eduSource('simple_thread.cc') 1228739Sgblack@eecs.umich.eduSource('thread_context.cc') 1236365Sgblack@eecs.umich.eduSource('thread_state.cc') 1244202Sbinkertn@umich.edu 1254202Sbinkertn@umich.eduif env['FULL_SYSTEM']: 1264202Sbinkertn@umich.edu SimObject('IntrControl.py') 1274202Sbinkertn@umich.edu 1285217Ssaidi@eecs.umich.edu Source('intr_control.cc') 1294202Sbinkertn@umich.edu Source('profile.cc') 1302155SN/A 1314202Sbinkertn@umich.edu if env['TARGET_ISA'] == 'sparc': 1324202Sbinkertn@umich.edu SimObject('LegionTrace.py') 1332821Sktlim@umich.edu Source('legiontrace.cc') 1344776Sgblack@eecs.umich.edu 1354776Sgblack@eecs.umich.eduif env['USE_CHECKER']: 1364776Sgblack@eecs.umich.edu Source('checker/cpu.cc') 1374776Sgblack@eecs.umich.edu TraceFlag('Checker') 1382766Sktlim@umich.edu checker_supports = False 1394202Sbinkertn@umich.edu for i in CheckerSupportedCPUList: 1408335Snate@binkert.org if i in env['CPU_MODELS']: 1412733Sktlim@umich.edu checker_supports = True 1422733Sktlim@umich.edu if not checker_supports: 1432733Sktlim@umich.edu print "Checker only supports CPU models", 1442733Sktlim@umich.edu for i in CheckerSupportedCPUList: 1452733Sktlim@umich.edu print i, 1462874Sktlim@umich.edu print ", please set USE_CHECKER=False or use one of those CPU models" 1472874Sktlim@umich.edu Exit(1) 1482874Sktlim@umich.edu 1494202Sbinkertn@umich.eduTraceFlag('Activity') 1502733Sktlim@umich.eduTraceFlag('Commit') 1515192Ssaidi@eecs.umich.eduTraceFlag('Context') 1528335Snate@binkert.orgTraceFlag('Decode') 1538335Snate@binkert.orgTraceFlag('DynInst') 1548335Snate@binkert.orgTraceFlag('ExecEnable') 1558335Snate@binkert.orgTraceFlag('ExecCPSeq') 1568335Snate@binkert.orgTraceFlag('ExecEffAddr') 1578335Snate@binkert.orgTraceFlag('ExecFaulting', 'Trace faulting instructions') 1588335Snate@binkert.orgTraceFlag('ExecFetchSeq') 1598335Snate@binkert.orgTraceFlag('ExecOpClass') 1608335Snate@binkert.orgTraceFlag('ExecRegDelta') 1618335Snate@binkert.orgTraceFlag('ExecResult') 1628335Snate@binkert.orgTraceFlag('ExecSpeculative') 1638335Snate@binkert.orgTraceFlag('ExecSymbol') 1648335Snate@binkert.orgTraceFlag('ExecThread') 1658335Snate@binkert.orgTraceFlag('ExecTicks') 1668335Snate@binkert.orgTraceFlag('ExecMicro') 1678335Snate@binkert.orgTraceFlag('ExecMacro') 1688335Snate@binkert.orgTraceFlag('Fetch') 1698335Snate@binkert.orgTraceFlag('IntrControl') 1708335Snate@binkert.orgTraceFlag('PCEvent') 1718335Snate@binkert.orgTraceFlag('Quiesce') 1728335Snate@binkert.org 1738335Snate@binkert.orgCompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread', 1748335Snate@binkert.org 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting' ]) 1758335Snate@binkert.orgCompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread', 1768471SGiacomo.Gabrielli@arm.com 'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting' ]) 1778335Snate@binkert.org