SConscript revision 7170
12929Sktlim@umich.edu# -*- mode:python -*-
22929Sktlim@umich.edu
32932Sktlim@umich.edu# Copyright (c) 2006 The Regents of The University of Michigan
42929Sktlim@umich.edu# All rights reserved.
52929Sktlim@umich.edu#
62929Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without
72929Sktlim@umich.edu# modification, are permitted provided that the following conditions are
82929Sktlim@umich.edu# met: redistributions of source code must retain the above copyright
92929Sktlim@umich.edu# notice, this list of conditions and the following disclaimer;
102929Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright
112929Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the
122929Sktlim@umich.edu# documentation and/or other materials provided with the distribution;
132929Sktlim@umich.edu# neither the name of the copyright holders nor the names of its
142929Sktlim@umich.edu# contributors may be used to endorse or promote products derived from
152929Sktlim@umich.edu# this software without specific prior written permission.
162929Sktlim@umich.edu#
172929Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
182929Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
192929Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
202929Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
212929Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
222929Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
232929Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
242929Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
252929Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
262929Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
272929Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
282932Sktlim@umich.edu#
292932Sktlim@umich.edu# Authors: Steve Reinhardt
302932Sktlim@umich.edu
312929Sktlim@umich.eduImport('*')
322929Sktlim@umich.edu
332929Sktlim@umich.edu#################################################################
342929Sktlim@umich.edu#
352929Sktlim@umich.edu# Generate StaticInst execute() method signatures.
362929Sktlim@umich.edu#
372929Sktlim@umich.edu# There must be one signature for each CPU model compiled in.
382929Sktlim@umich.edu# Since the set of compiled-in models is flexible, we generate a
392929Sktlim@umich.edu# header containing the appropriate set of signatures on the fly.
402929Sktlim@umich.edu#
412929Sktlim@umich.edu#################################################################
422929Sktlim@umich.edu
432929Sktlim@umich.edu# Template for execute() signature.
442929Sktlim@umich.eduexec_sig_template = '''
452929Sktlim@umich.eduvirtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
462929Sktlim@umich.eduvirtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
472929Sktlim@umich.edu{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
482929Sktlim@umich.eduvirtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
492929Sktlim@umich.edu{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
502929Sktlim@umich.eduvirtual Fault completeAcc(Packet *pkt, %(type)s *xc,
512929Sktlim@umich.edu                          Trace::InstRecord *traceData) const
522929Sktlim@umich.edu{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
532929Sktlim@umich.edu'''
542929Sktlim@umich.edu
552929Sktlim@umich.edumem_ini_sig_template = '''
562929Sktlim@umich.eduvirtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
572929Sktlim@umich.edu{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
582929Sktlim@umich.eduvirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
592929Sktlim@umich.edu'''
602929Sktlim@umich.edu
612929Sktlim@umich.edumem_comp_sig_template = '''
622929Sktlim@umich.eduvirtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
632929Sktlim@umich.edu'''
643020Sstever@eecs.umich.edu
653020Sstever@eecs.umich.edu# Generate a temporary CPU list, including the CheckerCPU if
663020Sstever@eecs.umich.edu# it's enabled.  This isn't used for anything else other than StaticInst
672929Sktlim@umich.edu# headers.
682929Sktlim@umich.edutemp_cpu_list = env['CPU_MODELS'][:]
693021Sstever@eecs.umich.edu
702929Sktlim@umich.eduif env['USE_CHECKER']:
712929Sktlim@umich.edu    temp_cpu_list.append('CheckerCPU')
722929Sktlim@umich.edu    SimObject('CheckerCPU.py')
732929Sktlim@umich.edu
742929Sktlim@umich.edu# Generate header.
752929Sktlim@umich.edudef gen_cpu_exec_signatures(target, source, env):
762929Sktlim@umich.edu    f = open(str(target[0]), 'w')
772929Sktlim@umich.edu    print >> f, '''
782929Sktlim@umich.edu#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
792929Sktlim@umich.edu#define __CPU_STATIC_INST_EXEC_SIGS_HH__
802929Sktlim@umich.edu'''
812929Sktlim@umich.edu    for cpu in temp_cpu_list:
822929Sktlim@umich.edu        xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
832929Sktlim@umich.edu        print >> f, exec_sig_template % { 'type' : xc_type }
842929Sktlim@umich.edu    print >> f, '''
852929Sktlim@umich.edu#endif  // __CPU_STATIC_INST_EXEC_SIGS_HH__
862929Sktlim@umich.edu'''
872929Sktlim@umich.edu
882929Sktlim@umich.edu# Generate string that gets printed when header is rebuilt
892929Sktlim@umich.edudef gen_sigs_string(target, source, env):
902929Sktlim@umich.edu    return "Generating static_inst_exec_sigs.hh: " \
912929Sktlim@umich.edu           + ', '.join(temp_cpu_list)
922929Sktlim@umich.edu
932929Sktlim@umich.edu# Add command to generate header to environment.
942929Sktlim@umich.eduenv.Command('static_inst_exec_sigs.hh', (),
952929Sktlim@umich.edu            Action(gen_cpu_exec_signatures, gen_sigs_string,
962929Sktlim@umich.edu                   varlist = temp_cpu_list))
972929Sktlim@umich.edu
982929Sktlim@umich.eduenv.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER']))
992929Sktlim@umich.eduenv.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
1002929Sktlim@umich.edu
1012929Sktlim@umich.edu# List of suppported CPUs by the Checker.  Errors out if USE_CHECKER=True
1022929Sktlim@umich.edu# and one of these are not being used.
1032929Sktlim@umich.eduCheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
1042929Sktlim@umich.edu
1052929Sktlim@umich.eduSimObject('BaseCPU.py')
1062929Sktlim@umich.eduSimObject('FuncUnit.py')
1072929Sktlim@umich.eduSimObject('ExeTracer.py')
1082929Sktlim@umich.eduSimObject('IntelTrace.py')
1092929Sktlim@umich.eduSimObject('NativeTrace.py')
1102929Sktlim@umich.edu
1112929Sktlim@umich.eduSource('activity.cc')
1122929Sktlim@umich.eduSource('base.cc')
1132929Sktlim@umich.eduSource('cpuevent.cc')
1142929Sktlim@umich.eduSource('exetrace.cc')
1152929Sktlim@umich.eduSource('func_unit.cc')
1162929Sktlim@umich.eduSource('inteltrace.cc')
1173701Sstever@eecs.umich.eduSource('nativetrace.cc')
1182929Sktlim@umich.eduSource('pc_event.cc')
1192929Sktlim@umich.eduSource('quiesce_event.cc')
1202929Sktlim@umich.eduSource('static_inst.cc')
1212929Sktlim@umich.eduSource('simple_thread.cc')
1222929Sktlim@umich.eduSource('thread_context.cc')
1232929Sktlim@umich.eduSource('thread_state.cc')
1242929Sktlim@umich.edu
1252929Sktlim@umich.eduif env['FULL_SYSTEM']:
1262929Sktlim@umich.edu    SimObject('IntrControl.py')
1272929Sktlim@umich.edu
1282929Sktlim@umich.edu    Source('intr_control.cc')
1292929Sktlim@umich.edu    Source('profile.cc')
1302929Sktlim@umich.edu
1312929Sktlim@umich.edu    if env['TARGET_ISA'] == 'sparc':
1322929Sktlim@umich.edu        SimObject('LegionTrace.py')
1332929Sktlim@umich.edu        Source('legiontrace.cc')
1342929Sktlim@umich.edu
1352929Sktlim@umich.eduif env['USE_CHECKER']:
1362929Sktlim@umich.edu    Source('checker/cpu.cc')
1372929Sktlim@umich.edu    TraceFlag('Checker')
1382929Sktlim@umich.edu    checker_supports = False
1392929Sktlim@umich.edu    for i in CheckerSupportedCPUList:
1402997Sstever@eecs.umich.edu        if i in env['CPU_MODELS']:
1412997Sstever@eecs.umich.edu            checker_supports = True
1422929Sktlim@umich.edu    if not checker_supports:
1432997Sstever@eecs.umich.edu        print "Checker only supports CPU models",
1442997Sstever@eecs.umich.edu        for i in CheckerSupportedCPUList:
1452929Sktlim@umich.edu            print i,
1462997Sstever@eecs.umich.edu        print ", please set USE_CHECKER=False or use one of those CPU models"
1472997Sstever@eecs.umich.edu        Exit(1)
1482997Sstever@eecs.umich.edu
1492929Sktlim@umich.eduTraceFlag('Activity')
1502997Sstever@eecs.umich.eduTraceFlag('Commit')
1512997Sstever@eecs.umich.eduTraceFlag('Context')
1522997Sstever@eecs.umich.eduTraceFlag('Decode')
1532997Sstever@eecs.umich.eduTraceFlag('DynInst')
1542997Sstever@eecs.umich.eduTraceFlag('ExecEnable')
1552997Sstever@eecs.umich.eduTraceFlag('ExecCPSeq')
1562997Sstever@eecs.umich.eduTraceFlag('ExecEffAddr')
1572997Sstever@eecs.umich.eduTraceFlag('ExecFaulting', 'Trace faulting instructions')
1582997Sstever@eecs.umich.eduTraceFlag('ExecFetchSeq')
1592997Sstever@eecs.umich.eduTraceFlag('ExecOpClass')
1602997Sstever@eecs.umich.eduTraceFlag('ExecRegDelta')
1612997Sstever@eecs.umich.eduTraceFlag('ExecResult')
1622997Sstever@eecs.umich.eduTraceFlag('ExecSpeculative')
1632997Sstever@eecs.umich.eduTraceFlag('ExecSymbol')
1642997Sstever@eecs.umich.eduTraceFlag('ExecThread')
1652997Sstever@eecs.umich.eduTraceFlag('ExecTicks')
1662997Sstever@eecs.umich.eduTraceFlag('ExecMicro')
1672997Sstever@eecs.umich.eduTraceFlag('ExecMacro')
1682997Sstever@eecs.umich.eduTraceFlag('Fetch')
1692997Sstever@eecs.umich.eduTraceFlag('IntrControl')
1703045Sstever@eecs.umich.eduTraceFlag('PCEvent')
1712997Sstever@eecs.umich.eduTraceFlag('Quiesce')
1722997Sstever@eecs.umich.edu
1732997Sstever@eecs.umich.eduCompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
1742953Sktlim@umich.edu    'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting' ])
1752997Sstever@eecs.umich.eduCompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
1762997Sstever@eecs.umich.edu    'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting' ])
1772997Sstever@eecs.umich.edu