SConscript revision 7025
14484Sbinkertn@umich.edu# -*- mode:python -*- 24484Sbinkertn@umich.edu 34484Sbinkertn@umich.edu# Copyright (c) 2006 The Regents of The University of Michigan 44484Sbinkertn@umich.edu# All rights reserved. 54484Sbinkertn@umich.edu# 64484Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 74484Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 84484Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 94484Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 104484Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 114484Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 124484Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 134484Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 144484Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 154484Sbinkertn@umich.edu# this software without specific prior written permission. 164484Sbinkertn@umich.edu# 174484Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 184484Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 194484Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 204484Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 214484Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 224484Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 234484Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 244484Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 254484Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 264484Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 274484Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 284484Sbinkertn@umich.edu# 294484Sbinkertn@umich.edu# Authors: Steve Reinhardt 304484Sbinkertn@umich.edu 314494Ssaidi@eecs.umich.eduImport('*') 324484Sbinkertn@umich.edu 336121Snate@binkert.org################################################################# 344484Sbinkertn@umich.edu# 354484Sbinkertn@umich.edu# Generate StaticInst execute() method signatures. 364484Sbinkertn@umich.edu# 374484Sbinkertn@umich.edu# There must be one signature for each CPU model compiled in. 384781Snate@binkert.org# Since the set of compiled-in models is flexible, we generate a 394484Sbinkertn@umich.edu# header containing the appropriate set of signatures on the fly. 404484Sbinkertn@umich.edu# 414484Sbinkertn@umich.edu################################################################# 424484Sbinkertn@umich.edu 438349Sgblack@eecs.umich.edu# Template for execute() signature. 448349Sgblack@eecs.umich.eduexec_sig_template = ''' 454484Sbinkertn@umich.eduvirtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0; 464484Sbinkertn@umich.eduvirtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const 474484Sbinkertn@umich.edu{ panic("eaComp not defined!"); M5_DUMMY_RETURN }; 484484Sbinkertn@umich.eduvirtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const 494484Sbinkertn@umich.edu{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN }; 504484Sbinkertn@umich.eduvirtual Fault completeAcc(Packet *pkt, %(type)s *xc, 514484Sbinkertn@umich.edu Trace::InstRecord *traceData) const 524484Sbinkertn@umich.edu{ panic("completeAcc not defined!"); M5_DUMMY_RETURN }; 534484Sbinkertn@umich.edu''' 544484Sbinkertn@umich.edu 554484Sbinkertn@umich.edumem_ini_sig_template = ''' 564484Sbinkertn@umich.eduvirtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const 574484Sbinkertn@umich.edu{ panic("eaComp not defined!"); M5_DUMMY_RETURN }; 584484Sbinkertn@umich.eduvirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN }; 594484Sbinkertn@umich.edu''' 604484Sbinkertn@umich.edu 614484Sbinkertn@umich.edumem_comp_sig_template = ''' 624484Sbinkertn@umich.eduvirtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN }; 634484Sbinkertn@umich.edu''' 644484Sbinkertn@umich.edu 654484Sbinkertn@umich.edu# Generate a temporary CPU list, including the CheckerCPU if 664484Sbinkertn@umich.edu# it's enabled. This isn't used for anything else other than StaticInst 674484Sbinkertn@umich.edu# headers. 684484Sbinkertn@umich.edutemp_cpu_list = env['CPU_MODELS'][:] 694484Sbinkertn@umich.edu 704484Sbinkertn@umich.eduif env['USE_CHECKER']: 714484Sbinkertn@umich.edu temp_cpu_list.append('CheckerCPU') 724484Sbinkertn@umich.edu SimObject('CheckerCPU.py') 734484Sbinkertn@umich.edu 744484Sbinkertn@umich.edu# Generate header. 754484Sbinkertn@umich.edudef gen_cpu_exec_signatures(target, source, env): 764484Sbinkertn@umich.edu f = open(str(target[0]), 'w') 774484Sbinkertn@umich.edu print >> f, ''' 784484Sbinkertn@umich.edu#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__ 794484Sbinkertn@umich.edu#define __CPU_STATIC_INST_EXEC_SIGS_HH__ 804484Sbinkertn@umich.edu''' 814484Sbinkertn@umich.edu for cpu in temp_cpu_list: 824484Sbinkertn@umich.edu xc_type = CpuModel.dict[cpu].strings['CPU_exec_context'] 834484Sbinkertn@umich.edu print >> f, exec_sig_template % { 'type' : xc_type } 844484Sbinkertn@umich.edu print >> f, ''' 854484Sbinkertn@umich.edu#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__ 864484Sbinkertn@umich.edu''' 874484Sbinkertn@umich.edu 884484Sbinkertn@umich.edu# Generate string that gets printed when header is rebuilt 894484Sbinkertn@umich.edudef gen_sigs_string(target, source, env): 904484Sbinkertn@umich.edu return "Generating static_inst_exec_sigs.hh: " \ 914484Sbinkertn@umich.edu + ', '.join(temp_cpu_list) 926121Snate@binkert.org 936121Snate@binkert.org# Add command to generate header to environment. 948655Sandreas.hansson@arm.comenv.Command('static_inst_exec_sigs.hh', (), 955765Snate@binkert.org Action(gen_cpu_exec_signatures, gen_sigs_string, 965765Snate@binkert.org varlist = temp_cpu_list)) 978737Skoansin.tan@gmail.com 988737Skoansin.tan@gmail.comenv.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER'])) 995765Snate@binkert.orgenv.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS'])) 1005397Ssaidi@eecs.umich.edu 1015274Ssaidi@eecs.umich.edu# List of suppported CPUs by the Checker. Errors out if USE_CHECKER=True 1024494Ssaidi@eecs.umich.edu# and one of these are not being used. 1034504Ssaidi@eecs.umich.eduCheckerSupportedCPUList = ['O3CPU', 'OzoneCPU'] 1044494Ssaidi@eecs.umich.edu 1054494Ssaidi@eecs.umich.eduSimObject('BaseCPU.py') 1064496Ssaidi@eecs.umich.eduSimObject('FuncUnit.py') 1074504Ssaidi@eecs.umich.eduSimObject('ExeTracer.py') 1084504Ssaidi@eecs.umich.eduSimObject('IntelTrace.py') 1094500Sbinkertn@umich.eduSimObject('NativeTrace.py') 1104500Sbinkertn@umich.edu 1114496Ssaidi@eecs.umich.eduSource('activity.cc') 1124496Ssaidi@eecs.umich.eduSource('base.cc') 1137739Sgblack@eecs.umich.eduSource('cpuevent.cc') 1144487Sstever@eecs.umich.eduSource('exetrace.cc') 1154484Sbinkertn@umich.eduSource('func_unit.cc') 1164484Sbinkertn@umich.eduSource('inteltrace.cc') 1174484Sbinkertn@umich.eduSource('nativetrace.cc') 1184484Sbinkertn@umich.eduSource('pc_event.cc') 1194484Sbinkertn@umich.eduSource('quiesce_event.cc') 1204484Sbinkertn@umich.eduSource('static_inst.cc') 1215601Snate@binkert.orgSource('simple_thread.cc') 1225601Snate@binkert.orgSource('thread_context.cc') 1235601Snate@binkert.orgSource('thread_state.cc') 1245601Snate@binkert.org 1254484Sbinkertn@umich.eduif env['FULL_SYSTEM']: 1266121Snate@binkert.org SimObject('IntrControl.py') 1276121Snate@binkert.org 1286121Snate@binkert.org Source('intr_control.cc') 1294494Ssaidi@eecs.umich.edu Source('profile.cc') 130 131 if env['TARGET_ISA'] == 'sparc': 132 SimObject('LegionTrace.py') 133 Source('legiontrace.cc') 134 135if env['USE_CHECKER']: 136 Source('checker/cpu.cc') 137 TraceFlag('Checker') 138 checker_supports = False 139 for i in CheckerSupportedCPUList: 140 if i in env['CPU_MODELS']: 141 checker_supports = True 142 if not checker_supports: 143 print "Checker only supports CPU models", 144 for i in CheckerSupportedCPUList: 145 print i, 146 print ", please set USE_CHECKER=False or use one of those CPU models" 147 Exit(1) 148 149TraceFlag('Activity') 150TraceFlag('Commit') 151TraceFlag('Context') 152TraceFlag('Decode') 153TraceFlag('DynInst') 154TraceFlag('ExecEnable') 155TraceFlag('ExecCPSeq') 156TraceFlag('ExecEffAddr') 157TraceFlag('ExecFaulting', 'Trace faulting instructions') 158TraceFlag('ExecFetchSeq') 159TraceFlag('ExecOpClass') 160TraceFlag('ExecRegDelta') 161TraceFlag('ExecResult') 162TraceFlag('ExecSpeculative') 163TraceFlag('ExecSymbol') 164TraceFlag('ExecThread') 165TraceFlag('ExecTicks') 166TraceFlag('ExecMicro') 167TraceFlag('ExecMacro') 168TraceFlag('Fetch') 169TraceFlag('IntrControl') 170TraceFlag('PCEvent') 171TraceFlag('Quiesce') 172 173CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread', 174 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting' ]) 175CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread', 176 'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting' ]) 177