SConscript revision 6654
12155SN/A# -*- mode:python -*- 22155SN/A 32155SN/A# Copyright (c) 2006 The Regents of The University of Michigan 42155SN/A# All rights reserved. 52155SN/A# 62155SN/A# Redistribution and use in source and binary forms, with or without 72155SN/A# modification, are permitted provided that the following conditions are 82155SN/A# met: redistributions of source code must retain the above copyright 92155SN/A# notice, this list of conditions and the following disclaimer; 102155SN/A# redistributions in binary form must reproduce the above copyright 112155SN/A# notice, this list of conditions and the following disclaimer in the 122155SN/A# documentation and/or other materials provided with the distribution; 132155SN/A# neither the name of the copyright holders nor the names of its 142155SN/A# contributors may be used to endorse or promote products derived from 152155SN/A# this software without specific prior written permission. 162155SN/A# 172155SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182155SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192155SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202155SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212155SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222155SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232155SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242155SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252155SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262155SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272155SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu# 292665Ssaidi@eecs.umich.edu# Authors: Steve Reinhardt 302155SN/A 314202Sbinkertn@umich.eduImport('*') 322155SN/A 332178SN/A################################################################# 342178SN/A# 352178SN/A# Generate StaticInst execute() method signatures. 362178SN/A# 372178SN/A# There must be one signature for each CPU model compiled in. 382178SN/A# Since the set of compiled-in models is flexible, we generate a 392178SN/A# header containing the appropriate set of signatures on the fly. 402178SN/A# 412178SN/A################################################################# 422178SN/A 432178SN/A# CPU model-specific data is contained in cpu_models.py 442178SN/A# Convert to SCons File node to get path handling 452155SN/Amodels_db = File('cpu_models.py') 462178SN/A# slurp in contents of file 472155SN/Aexecfile(models_db.srcnode().abspath) 482155SN/A 492178SN/A# Template for execute() signature. 502155SN/Aexec_sig_template = ''' 515865Sksewell@umich.eduvirtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0; 526181Sksewell@umich.eduvirtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const 536181Sksewell@umich.edu{ panic("eaComp not defined!"); M5_DUMMY_RETURN }; 545865Sksewell@umich.eduvirtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const 553918Ssaidi@eecs.umich.edu{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN }; 565865Sksewell@umich.eduvirtual Fault completeAcc(Packet *pkt, %(type)s *xc, 572623SN/A Trace::InstRecord *traceData) const 583918Ssaidi@eecs.umich.edu{ panic("completeAcc not defined!"); M5_DUMMY_RETURN }; 592155SN/A''' 602155SN/A 612292SN/Amem_ini_sig_template = ''' 626181Sksewell@umich.eduvirtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const 636181Sksewell@umich.edu{ panic("eaComp not defined!"); M5_DUMMY_RETURN }; 643918Ssaidi@eecs.umich.eduvirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN }; 652292SN/A''' 662292SN/A 672292SN/Amem_comp_sig_template = ''' 683918Ssaidi@eecs.umich.eduvirtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN }; 692292SN/A''' 702292SN/A 712766Sktlim@umich.edu# Generate a temporary CPU list, including the CheckerCPU if 722766Sktlim@umich.edu# it's enabled. This isn't used for anything else other than StaticInst 732766Sktlim@umich.edu# headers. 742921Sktlim@umich.edutemp_cpu_list = env['CPU_MODELS'][:] 752921Sktlim@umich.edu 762766Sktlim@umich.eduif env['USE_CHECKER']: 772766Sktlim@umich.edu temp_cpu_list.append('CheckerCPU') 785529Snate@binkert.org SimObject('CheckerCPU.py') 792766Sktlim@umich.edu 804762Snate@binkert.org# Generate header. 812155SN/Adef gen_cpu_exec_signatures(target, source, env): 822155SN/A f = open(str(target[0]), 'w') 832155SN/A print >> f, ''' 842155SN/A#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__ 852155SN/A#define __CPU_STATIC_INST_EXEC_SIGS_HH__ 862155SN/A''' 872766Sktlim@umich.edu for cpu in temp_cpu_list: 882155SN/A xc_type = CpuModel.dict[cpu].strings['CPU_exec_context'] 895865Sksewell@umich.edu print >> f, exec_sig_template % { 'type' : xc_type } 902155SN/A print >> f, ''' 912155SN/A#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__ 922155SN/A''' 932155SN/A 942178SN/A# Generate string that gets printed when header is rebuilt 952178SN/Adef gen_sigs_string(target, source, env): 962178SN/A return "Generating static_inst_exec_sigs.hh: " \ 972766Sktlim@umich.edu + ', '.join(temp_cpu_list) 982178SN/A 992178SN/A# Add command to generate header to environment. 1002178SN/Aenv.Command('static_inst_exec_sigs.hh', models_db, 1012178SN/A Action(gen_cpu_exec_signatures, gen_sigs_string, 1022766Sktlim@umich.edu varlist = temp_cpu_list)) 1032766Sktlim@umich.edu 1042766Sktlim@umich.eduenv.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER'])) 1052788Sktlim@umich.eduenv.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS'])) 1062178SN/A 1072733Sktlim@umich.edu# List of suppported CPUs by the Checker. Errors out if USE_CHECKER=True 1082733Sktlim@umich.edu# and one of these are not being used. 1092817Sksewell@umich.eduCheckerSupportedCPUList = ['O3CPU', 'OzoneCPU'] 1102733Sktlim@umich.edu 1114486Sbinkertn@umich.eduSimObject('BaseCPU.py') 1124486Sbinkertn@umich.eduSimObject('FuncUnit.py') 1134776Sgblack@eecs.umich.eduSimObject('ExeTracer.py') 1144776Sgblack@eecs.umich.eduSimObject('IntelTrace.py') 1156365Sgblack@eecs.umich.eduSimObject('NativeTrace.py') 1164486Sbinkertn@umich.edu 1174202Sbinkertn@umich.eduSource('activity.cc') 1184202Sbinkertn@umich.eduSource('base.cc') 1194202Sbinkertn@umich.eduSource('cpuevent.cc') 1204202Sbinkertn@umich.eduSource('exetrace.cc') 1214202Sbinkertn@umich.eduSource('func_unit.cc') 1224776Sgblack@eecs.umich.eduSource('inteltrace.cc') 1236365Sgblack@eecs.umich.eduSource('nativetrace.cc') 1244202Sbinkertn@umich.eduSource('pc_event.cc') 1254202Sbinkertn@umich.eduSource('quiesce_event.cc') 1264202Sbinkertn@umich.eduSource('static_inst.cc') 1274202Sbinkertn@umich.eduSource('simple_thread.cc') 1285217Ssaidi@eecs.umich.eduSource('thread_context.cc') 1294202Sbinkertn@umich.eduSource('thread_state.cc') 1302155SN/A 1314202Sbinkertn@umich.eduif env['FULL_SYSTEM']: 1324486Sbinkertn@umich.edu SimObject('IntrControl.py') 1334486Sbinkertn@umich.edu 1344202Sbinkertn@umich.edu Source('intr_control.cc') 1354202Sbinkertn@umich.edu Source('profile.cc') 1362821Sktlim@umich.edu 1374776Sgblack@eecs.umich.edu if env['TARGET_ISA'] == 'sparc': 1384776Sgblack@eecs.umich.edu SimObject('LegionTrace.py') 1394776Sgblack@eecs.umich.edu Source('legiontrace.cc') 1404776Sgblack@eecs.umich.edu 1412766Sktlim@umich.eduif env['USE_CHECKER']: 1424202Sbinkertn@umich.edu Source('checker/cpu.cc') 1435192Ssaidi@eecs.umich.edu TraceFlag('Checker') 1442733Sktlim@umich.edu checker_supports = False 1452733Sktlim@umich.edu for i in CheckerSupportedCPUList: 1462733Sktlim@umich.edu if i in env['CPU_MODELS']: 1472733Sktlim@umich.edu checker_supports = True 1482733Sktlim@umich.edu if not checker_supports: 1492874Sktlim@umich.edu print "Checker only supports CPU models", 1502874Sktlim@umich.edu for i in CheckerSupportedCPUList: 1512874Sktlim@umich.edu print i, 1524202Sbinkertn@umich.edu print ", please set USE_CHECKER=False or use one of those CPU models" 1532733Sktlim@umich.edu Exit(1) 1545192Ssaidi@eecs.umich.edu 1555192Ssaidi@eecs.umich.eduTraceFlag('Activity') 1565192Ssaidi@eecs.umich.eduTraceFlag('Commit') 1575217Ssaidi@eecs.umich.eduTraceFlag('Context') 1585192Ssaidi@eecs.umich.eduTraceFlag('Decode') 1595192Ssaidi@eecs.umich.eduTraceFlag('DynInst') 1605192Ssaidi@eecs.umich.eduTraceFlag('ExecEnable') 1615192Ssaidi@eecs.umich.eduTraceFlag('ExecCPSeq') 1625192Ssaidi@eecs.umich.eduTraceFlag('ExecEffAddr') 1635192Ssaidi@eecs.umich.eduTraceFlag('ExecFetchSeq') 1645192Ssaidi@eecs.umich.eduTraceFlag('ExecOpClass') 1655192Ssaidi@eecs.umich.eduTraceFlag('ExecRegDelta') 1665192Ssaidi@eecs.umich.eduTraceFlag('ExecResult') 1675192Ssaidi@eecs.umich.eduTraceFlag('ExecSpeculative') 1685192Ssaidi@eecs.umich.eduTraceFlag('ExecSymbol') 1695192Ssaidi@eecs.umich.eduTraceFlag('ExecThread') 1705192Ssaidi@eecs.umich.eduTraceFlag('ExecTicks') 1715784Sgblack@eecs.umich.eduTraceFlag('ExecMicro') 1725784Sgblack@eecs.umich.eduTraceFlag('ExecMacro') 1735192Ssaidi@eecs.umich.eduTraceFlag('Fetch') 1745192Ssaidi@eecs.umich.eduTraceFlag('IntrControl') 1755192Ssaidi@eecs.umich.eduTraceFlag('PCEvent') 1765192Ssaidi@eecs.umich.eduTraceFlag('Quiesce') 1775192Ssaidi@eecs.umich.edu 1785192Ssaidi@eecs.umich.eduCompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread', 1795784Sgblack@eecs.umich.edu 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro' ]) 1806036Sksewell@umich.eduCompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread', 1816036Sksewell@umich.edu 'ExecEffAddr', 'ExecResult', 'ExecMicro' ]) 182