SConscript revision 5780
12139SN/A# -*- mode:python -*- 22139SN/A 32139SN/A# Copyright (c) 2006 The Regents of The University of Michigan 42139SN/A# All rights reserved. 52139SN/A# 62139SN/A# Redistribution and use in source and binary forms, with or without 72139SN/A# modification, are permitted provided that the following conditions are 82139SN/A# met: redistributions of source code must retain the above copyright 92139SN/A# notice, this list of conditions and the following disclaimer; 102139SN/A# redistributions in binary form must reproduce the above copyright 112139SN/A# notice, this list of conditions and the following disclaimer in the 122139SN/A# documentation and/or other materials provided with the distribution; 132139SN/A# neither the name of the copyright holders nor the names of its 142139SN/A# contributors may be used to endorse or promote products derived from 152139SN/A# this software without specific prior written permission. 162139SN/A# 172139SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182139SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192139SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202139SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212139SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222139SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232139SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242139SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252139SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262139SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272139SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu# 292665Ssaidi@eecs.umich.edu# Authors: Steve Reinhardt 302139SN/A 312718Sstever@eecs.umich.eduImport('*') 322139SN/A 332139SN/A################################################################# 342139SN/A# 352139SN/A# Generate StaticInst execute() method signatures. 362152SN/A# 372152SN/A# There must be one signature for each CPU model compiled in. 382152SN/A# Since the set of compiled-in models is flexible, we generate a 392152SN/A# header containing the appropriate set of signatures on the fly. 402139SN/A# 412139SN/A################################################################# 422139SN/A 432139SN/A# CPU model-specific data is contained in cpu_models.py 442139SN/A# Convert to SCons File node to get path handling 452152SN/Amodels_db = File('cpu_models.py') 462152SN/A# slurp in contents of file 472139SN/Aexecfile(models_db.srcnode().abspath) 482139SN/A 492139SN/A# Template for execute() signature. 502984Sgblack@eecs.umich.eduexec_sig_template = ''' 512439SN/Avirtual Fault execute(%s *xc, Trace::InstRecord *traceData) const = 0; 523520Sgblack@eecs.umich.eduvirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const 532139SN/A{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN }; 543565Sgblack@eecs.umich.eduvirtual Fault completeAcc(Packet *pkt, %s *xc, 553170Sstever@eecs.umich.edu Trace::InstRecord *traceData) const 563806Ssaidi@eecs.umich.edu{ panic("completeAcc not defined!"); M5_DUMMY_RETURN }; 572439SN/A''' 582460SN/A 593536Sgblack@eecs.umich.edumem_ini_sig_template = ''' 602439SN/Avirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN }; 612972Sgblack@eecs.umich.edu''' 622171SN/A 632439SN/Amem_comp_sig_template = ''' 642439SN/Avirtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN }; 652170SN/A''' 662139SN/A 672139SN/A# Generate a temporary CPU list, including the CheckerCPU if 683546Sgblack@eecs.umich.edu# it's enabled. This isn't used for anything else other than StaticInst 693546Sgblack@eecs.umich.edu# headers. 702152SN/Atemp_cpu_list = env['CPU_MODELS'][:] 712152SN/A 722152SN/Aif env['USE_CHECKER']: 732152SN/A temp_cpu_list.append('CheckerCPU') 742152SN/A SimObject('CheckerCPU.py') 752152SN/A 762152SN/A# Generate header. 772152SN/Adef gen_cpu_exec_signatures(target, source, env): 782152SN/A f = open(str(target[0]), 'w') 792152SN/A print >> f, ''' 802152SN/A#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__ 812152SN/A#define __CPU_STATIC_INST_EXEC_SIGS_HH__ 822504SN/A''' 832504SN/A for cpu in temp_cpu_list: 842504SN/A xc_type = CpuModel.dict[cpu].strings['CPU_exec_context'] 852504SN/A print >> f, exec_sig_template % (xc_type, xc_type, xc_type) 862152SN/A print >> f, ''' 872504SN/A#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__ 882152SN/A''' 892152SN/A 902152SN/A# Generate string that gets printed when header is rebuilt 912152SN/Adef gen_sigs_string(target, source, env): 922152SN/A return "Generating static_inst_exec_sigs.hh: " \ 932152SN/A + ', '.join(temp_cpu_list) 942152SN/A 952152SN/A# Add command to generate header to environment. 962632Sstever@eecs.umich.eduenv.Command('static_inst_exec_sigs.hh', models_db, 972155SN/A Action(gen_cpu_exec_signatures, gen_sigs_string, 982155SN/A varlist = temp_cpu_list)) 992155SN/A 1002155SN/Aenv.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER'])) 1012155SN/Aenv.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS'])) 1022155SN/A 1032155SN/A# List of suppported CPUs by the Checker. Errors out if USE_CHECKER=True 1042155SN/A# and one of these are not being used. 1052155SN/ACheckerSupportedCPUList = ['O3CPU', 'OzoneCPU'] 1062155SN/A 1072152SN/ASimObject('BaseCPU.py') 1082766Sktlim@umich.eduSimObject('FuncUnit.py') 1092766Sktlim@umich.eduSimObject('ExeTracer.py') 1102766Sktlim@umich.eduSimObject('IntelTrace.py') 1112766Sktlim@umich.edu 1122766Sktlim@umich.eduSource('activity.cc') 1132152SN/ASource('base.cc') 1142152SN/ASource('cpuevent.cc') 1152152SN/ASource('exetrace.cc') 1162155SN/ASource('func_unit.cc') 1172152SN/ASource('inteltrace.cc') 1182152SN/ASource('pc_event.cc') 1192718Sstever@eecs.umich.eduSource('quiesce_event.cc') 1202921Sktlim@umich.eduSource('static_inst.cc') 1212921Sktlim@umich.eduSource('simple_thread.cc') 1222921Sktlim@umich.eduSource('thread_context.cc') 1232921Sktlim@umich.eduSource('thread_state.cc') 1242921Sktlim@umich.edu 1252921Sktlim@umich.eduif env['FULL_SYSTEM']: 1262921Sktlim@umich.edu SimObject('IntrControl.py') 1272921Sktlim@umich.edu 1282921Sktlim@umich.edu Source('intr_control.cc') 1292152SN/A Source('profile.cc') 1302152SN/A 1312152SN/A if env['TARGET_ISA'] == 'sparc': 1322152SN/A SimObject('LegionTrace.py') 1332152SN/A Source('legiontrace.cc') 1342152SN/A 1352152SN/Aif env['TARGET_ISA'] == 'x86': 1362152SN/A SimObject('NativeTrace.py') 1372152SN/A Source('nativetrace.cc') 1382152SN/A 1392667Sstever@eecs.umich.eduif env['USE_CHECKER']: 1402152SN/A Source('checker/cpu.cc') 1412152SN/A TraceFlag('Checker') 142 checker_supports = False 143 for i in CheckerSupportedCPUList: 144 if i in env['CPU_MODELS']: 145 checker_supports = True 146 if not checker_supports: 147 print "Checker only supports CPU models", 148 for i in CheckerSupportedCPUList: 149 print i, 150 print ", please set USE_CHECKER=False or use one of those CPU models" 151 Exit(1) 152# Workaround for bug in SCons version > 0.97d20071212 153# Scons bug id: 2006 M5 Bug id: 308 154else: 155 Dir('checker') 156 157TraceFlag('Activity') 158TraceFlag('Commit') 159TraceFlag('Context') 160TraceFlag('Decode') 161TraceFlag('DynInst') 162TraceFlag('ExecEnable') 163TraceFlag('ExecCPSeq') 164TraceFlag('ExecEffAddr') 165TraceFlag('ExecFetchSeq') 166TraceFlag('ExecOpClass') 167TraceFlag('ExecRegDelta') 168TraceFlag('ExecResult') 169TraceFlag('ExecSpeculative') 170TraceFlag('ExecSymbol') 171TraceFlag('ExecThread') 172TraceFlag('ExecTicks') 173TraceFlag('Fetch') 174TraceFlag('IntrControl') 175TraceFlag('PCEvent') 176TraceFlag('Quiesce') 177 178CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread', 179 'ExecEffAddr', 'ExecResult', 'ExecSymbol' ]) 180