SConscript revision 5529
12155SN/A# -*- mode:python -*- 22155SN/A 32155SN/A# Copyright (c) 2006 The Regents of The University of Michigan 42155SN/A# All rights reserved. 52155SN/A# 62155SN/A# Redistribution and use in source and binary forms, with or without 72155SN/A# modification, are permitted provided that the following conditions are 82155SN/A# met: redistributions of source code must retain the above copyright 92155SN/A# notice, this list of conditions and the following disclaimer; 102155SN/A# redistributions in binary form must reproduce the above copyright 112155SN/A# notice, this list of conditions and the following disclaimer in the 122155SN/A# documentation and/or other materials provided with the distribution; 132155SN/A# neither the name of the copyright holders nor the names of its 142155SN/A# contributors may be used to endorse or promote products derived from 152155SN/A# this software without specific prior written permission. 162155SN/A# 172155SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182155SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192155SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202155SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212155SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222155SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232155SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242155SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252155SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262155SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272155SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu# 292665Ssaidi@eecs.umich.edu# Authors: Steve Reinhardt 302155SN/A 312155SN/AImport('*') 322155SN/A 332155SN/A################################################################# 342155SN/A# 352155SN/A# Generate StaticInst execute() method signatures. 362155SN/A# 372178SN/A# There must be one signature for each CPU model compiled in. 382178SN/A# Since the set of compiled-in models is flexible, we generate a 392178SN/A# header containing the appropriate set of signatures on the fly. 402178SN/A# 412178SN/A################################################################# 422178SN/A 432178SN/A# CPU model-specific data is contained in cpu_models.py 442178SN/A# Convert to SCons File node to get path handling 452178SN/Amodels_db = File('cpu_models.py') 462178SN/A# slurp in contents of file 472178SN/Aexecfile(models_db.srcnode().abspath) 482178SN/A 492155SN/A# Template for execute() signature. 502178SN/Aexec_sig_template = ''' 512155SN/Avirtual Fault execute(%s *xc, Trace::InstRecord *traceData) const = 0; 522155SN/Avirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const 532178SN/A{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN }; 542155SN/Avirtual Fault completeAcc(Packet *pkt, %s *xc, 552155SN/A Trace::InstRecord *traceData) const 562623SN/A{ panic("completeAcc not defined!"); M5_DUMMY_RETURN }; 572623SN/A''' 582623SN/A 592623SN/Amem_ini_sig_template = ''' 602623SN/Avirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN }; 612155SN/A''' 622155SN/A 632292SN/Amem_comp_sig_template = ''' 642292SN/Avirtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN }; 652292SN/A''' 662292SN/A 672292SN/A# Generate a temporary CPU list, including the CheckerCPU if 682292SN/A# it's enabled. This isn't used for anything else other than StaticInst 692292SN/A# headers. 702292SN/Atemp_cpu_list = env['CPU_MODELS'][:] 712766Sktlim@umich.edu 722766Sktlim@umich.eduif env['USE_CHECKER']: 732766Sktlim@umich.edu temp_cpu_list.append('CheckerCPU') 742766Sktlim@umich.edu SimObject('CheckerCPU.py') 752766Sktlim@umich.edu 762766Sktlim@umich.edu# Generate header. 772766Sktlim@umich.edudef gen_cpu_exec_signatures(target, source, env): 782178SN/A f = open(str(target[0]), 'w') 792155SN/A print >> f, ''' 802155SN/A#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__ 812155SN/A#define __CPU_STATIC_INST_EXEC_SIGS_HH__ 822155SN/A''' 832155SN/A for cpu in temp_cpu_list: 842155SN/A xc_type = CpuModel.dict[cpu].strings['CPU_exec_context'] 852766Sktlim@umich.edu print >> f, exec_sig_template % (xc_type, xc_type, xc_type) 862155SN/A print >> f, ''' 872623SN/A#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__ 882155SN/A''' 892155SN/A 902155SN/A# Generate string that gets printed when header is rebuilt 912155SN/Adef gen_sigs_string(target, source, env): 922178SN/A return "Generating static_inst_exec_sigs.hh: " \ 932178SN/A + ', '.join(temp_cpu_list) 942178SN/A 952766Sktlim@umich.edu# Add command to generate header to environment. 962178SN/Aenv.Command('static_inst_exec_sigs.hh', models_db, 972178SN/A Action(gen_cpu_exec_signatures, gen_sigs_string, 982178SN/A varlist = temp_cpu_list)) 992178SN/A 1002766Sktlim@umich.eduenv.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER'])) 1012766Sktlim@umich.eduenv.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS'])) 1022766Sktlim@umich.edu 1032788Sktlim@umich.edu# List of suppported CPUs by the Checker. Errors out if USE_CHECKER=True 1042178SN/A# and one of these are not being used. 1052733Sktlim@umich.eduCheckerSupportedCPUList = ['O3CPU', 'OzoneCPU'] 1062733Sktlim@umich.edu 1072817Sksewell@umich.eduSimObject('BaseCPU.py') 1082733Sktlim@umich.eduSimObject('FuncUnit.py') 1092178SN/ASimObject('ExeTracer.py') 1102178SN/ASimObject('IntelTrace.py') 1112178SN/A 1122178SN/ASource('activity.cc') 1132178SN/ASource('base.cc') 1142178SN/ASource('cpuevent.cc') 1152155SN/ASource('exetrace.cc') 1162155SN/ASource('func_unit.cc') 1172155SN/ASource('inteltrace.cc') 1182623SN/ASource('pc_event.cc') 1192623SN/ASource('quiesce_event.cc') 1202623SN/ASource('static_inst.cc') 1212623SN/ASource('simple_thread.cc') 1222623SN/ASource('thread_context.cc') 1232623SN/ASource('thread_state.cc') 1242623SN/A 1252623SN/Aif env['FULL_SYSTEM']: 1262623SN/A SimObject('IntrControl.py') 1272623SN/A 1282623SN/A Source('intr_control.cc') 1292155SN/A Source('profile.cc') 1302155SN/A 1312155SN/A if env['TARGET_ISA'] == 'sparc': 1322155SN/A SimObject('LegionTrace.py') 1332817Sksewell@umich.edu Source('legiontrace.cc') 1342817Sksewell@umich.edu 1352155SN/Aif env['TARGET_ISA'] == 'x86': 1362155SN/A SimObject('NativeTrace.py') 1372765Sktlim@umich.edu Source('nativetrace.cc') 1382155SN/A 1392155SN/Aif env['USE_CHECKER']: 1402155SN/A Source('checker/cpu.cc') 1412155SN/A TraceFlag('Checker') 1422155SN/A checker_supports = False 1432155SN/A for i in CheckerSupportedCPUList: 1442292SN/A if i in env['CPU_MODELS']: 1452155SN/A checker_supports = True 1462155SN/A if not checker_supports: 1472155SN/A print "Checker only supports CPU models", 1482292SN/A for i in CheckerSupportedCPUList: 1492292SN/A print i, 1502155SN/A print ", please set USE_CHECKER=False or use one of those CPU models" 1512155SN/A Exit(1) 1522155SN/A# Workaround for bug in SCons version > 0.97d20071212 1532155SN/A# Scons bug id: 2006 M5 Bug id: 308 1542155SN/Aelse: 1552292SN/A Dir('checker') 1562155SN/A 1572155SN/ATraceFlag('Activity') 1582155SN/ATraceFlag('Commit') 1592766Sktlim@umich.eduTraceFlag('Context') 1602765Sktlim@umich.eduTraceFlag('Decode') 1612155SN/ATraceFlag('DynInst') 1622792Sktlim@umich.eduTraceFlag('ExecEnable') 1632292SN/ATraceFlag('ExecCPSeq') 1642792Sktlim@umich.eduTraceFlag('ExecEffAddr') 1652792Sktlim@umich.eduTraceFlag('ExecFetchSeq') 1662292SN/ATraceFlag('ExecOpClass') 1672292SN/ATraceFlag('ExecRegDelta') 1682292SN/ATraceFlag('ExecResult') 1692292SN/ATraceFlag('ExecSpeculative') 1702297SN/ATraceFlag('ExecSymbol') 1712297SN/ATraceFlag('ExecThread') 1722792Sktlim@umich.eduTraceFlag('ExecTicks') 1732292SN/ATraceFlag('Fetch') 1742766Sktlim@umich.eduTraceFlag('IntrControl') 1752765Sktlim@umich.eduTraceFlag('PCEvent') 1762292SN/ATraceFlag('Quiesce') 1772766Sktlim@umich.edu 1782789Sktlim@umich.eduCompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread', 1792733Sktlim@umich.edu 'ExecEffAddr', 'ExecResult', 'ExecSymbol' ]) 1802733Sktlim@umich.edu