SConscript revision 4381
14202Sbinkertn@umich.edu# -*- mode:python -*- 24202Sbinkertn@umich.edu 34202Sbinkertn@umich.edu# Copyright (c) 2006 The Regents of The University of Michigan 44202Sbinkertn@umich.edu# All rights reserved. 54202Sbinkertn@umich.edu# 64202Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 74202Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 84202Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 94202Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 104202Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 114202Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 124202Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 134202Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 144202Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 154202Sbinkertn@umich.edu# this software without specific prior written permission. 164202Sbinkertn@umich.edu# 174202Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 184202Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 194202Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 204202Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 214202Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 224202Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 234202Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 244202Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 254202Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 264202Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 274202Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 284202Sbinkertn@umich.edu# 294202Sbinkertn@umich.edu# Authors: Steve Reinhardt 304202Sbinkertn@umich.edu 314202Sbinkertn@umich.eduImport('*') 324202Sbinkertn@umich.edu 339398Sandreas.hansson@arm.com################################################################# 349398Sandreas.hansson@arm.com# 359398Sandreas.hansson@arm.com# Generate StaticInst execute() method signatures. 369398Sandreas.hansson@arm.com# 379398Sandreas.hansson@arm.com# There must be one signature for each CPU model compiled in. 389398Sandreas.hansson@arm.com# Since the set of compiled-in models is flexible, we generate a 399850Sandreas.hansson@arm.com# header containing the appropriate set of signatures on the fly. 409259SAli.Saidi@ARM.com# 414486Sbinkertn@umich.edu################################################################# 4210146Sandreas.hansson@arm.com 4310478SAndrew.Bardsley@arm.com# CPU model-specific data is contained in cpu_models.py 4410478SAndrew.Bardsley@arm.com# Convert to SCons File node to get path handling 456165Ssanchezd@stanford.edumodels_db = File('cpu_models.py') 469850Sandreas.hansson@arm.com# slurp in contents of file 4710614Skanishk.sugand@arm.comexecfile(models_db.srcnode().abspath) 4810405Sandreas.hansson@arm.com 496168Snate@binkert.org# Template for execute() signature. 509850Sandreas.hansson@arm.comexec_sig_template = ''' 519259SAli.Saidi@ARM.comvirtual Fault execute(%s *xc, Trace::InstRecord *traceData) const = 0; 524202Sbinkertn@umich.eduvirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const 5310405Sandreas.hansson@arm.com{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN }; 5410431SOmar.Naji@arm.comvirtual Fault completeAcc(Packet *pkt, %s *xc, 5510146Sandreas.hansson@arm.com Trace::InstRecord *traceData) const 5610478SAndrew.Bardsley@arm.com{ panic("completeAcc not defined!"); M5_DUMMY_RETURN }; 5710478SAndrew.Bardsley@arm.com''' 584202Sbinkertn@umich.edu 598761Sgblack@eecs.umich.edumem_ini_sig_template = ''' 6010405Sandreas.hansson@arm.comvirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN }; 614202Sbinkertn@umich.edu''' 624202Sbinkertn@umich.edu 638914Sandreas.hansson@arm.commem_comp_sig_template = ''' 6410405Sandreas.hansson@arm.comvirtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN }; 6510405Sandreas.hansson@arm.com''' 6610405Sandreas.hansson@arm.com 6710405Sandreas.hansson@arm.com# Generate a temporary CPU list, including the CheckerCPU if 6810614Skanishk.sugand@arm.com# it's enabled. This isn't used for anything else other than StaticInst 694202Sbinkertn@umich.edu# headers. 7010405Sandreas.hansson@arm.comtemp_cpu_list = env['CPU_MODELS'][:] 716168Snate@binkert.org 729850Sandreas.hansson@arm.comif env['USE_CHECKER']: 739850Sandreas.hansson@arm.com temp_cpu_list.append('CheckerCPU') 749850Sandreas.hansson@arm.com 758763Sgblack@eecs.umich.edu# Generate header. 7610299Salexandru.dutu@amd.comdef gen_cpu_exec_signatures(target, source, env): 7710299Salexandru.dutu@amd.com f = open(str(target[0]), 'w') 787768SAli.Saidi@ARM.com print >> f, ''' 7910131Sandreas.hansson@arm.com#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__ 8010131Sandreas.hansson@arm.com#define __CPU_STATIC_INST_EXEC_SIGS_HH__ 8110131Sandreas.hansson@arm.com''' 8210131Sandreas.hansson@arm.com for cpu in temp_cpu_list: 8310066Sandreas.hansson@arm.com xc_type = CpuModel.dict[cpu].strings['CPU_exec_context'] 8410612SMarco.Elver@ARM.com print >> f, exec_sig_template % (xc_type, xc_type, xc_type) 8510612SMarco.Elver@ARM.com print >> f, ''' 8610612SMarco.Elver@ARM.com#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__ 8710612SMarco.Elver@ARM.com''' 8810405Sandreas.hansson@arm.com 8910405Sandreas.hansson@arm.com# Generate string that gets printed when header is rebuilt 9010405Sandreas.hansson@arm.comdef gen_sigs_string(target, source, env): 9110405Sandreas.hansson@arm.com return "Generating static_inst_exec_sigs.hh: " \ 9210399Sstephan.diestelhorst@arm.com + ', '.join(temp_cpu_list) 9310405Sandreas.hansson@arm.com 9410405Sandreas.hansson@arm.com# Add command to generate header to environment. 959036Sandreas.hansson@arm.comenv.Command('static_inst_exec_sigs.hh', models_db, 969164Sandreas.hansson@arm.com Action(gen_cpu_exec_signatures, gen_sigs_string, 978981Sandreas.hansson@arm.com varlist = temp_cpu_list)) 989243Sandreas.hansson@arm.com 9910247Sandreas.hansson@arm.comenv.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER'])) 10010208Sandreas.hansson@arm.comenv.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS'])) 10110478SAndrew.Bardsley@arm.com 1028335Snate@binkert.org# List of suppported CPUs by the Checker. Errors out if USE_CHECKER=True 1038335Snate@binkert.org# and one of these are not being used. 1048335Snate@binkert.orgCheckerSupportedCPUList = ['O3CPU', 'OzoneCPU'] 1058914Sandreas.hansson@arm.com 10610614Skanishk.sugand@arm.comSource('activity.cc') 10710066Sandreas.hansson@arm.comSource('base.cc') 10810612SMarco.Elver@ARM.comSource('cpuevent.cc') 10910612SMarco.Elver@ARM.comSource('exetrace.cc') 11010612SMarco.Elver@ARM.comSource('func_unit.cc') 111Source('op_class.cc') 112Source('pc_event.cc') 113Source('quiesce_event.cc') 114Source('static_inst.cc') 115Source('simple_thread.cc') 116Source('thread_state.cc') 117 118if env['FULL_SYSTEM']: 119 Source('intr_control.cc') 120 Source('profile.cc') 121 122if env['USE_CHECKER']: 123 Source('checker/cpu.cc') 124 checker_supports = False 125 for i in CheckerSupportedCPUList: 126 if i in env['CPU_MODELS']: 127 checker_supports = True 128 if not checker_supports: 129 print "Checker only supports CPU models", 130 for i in CheckerSupportedCPUList: 131 print i, 132 print ", please set USE_CHECKER=False or use one of those CPU models" 133 Exit(1) 134