SConscript revision 12016
16019Shines@cs.fsu.edu# -*- mode:python -*-
26019Shines@cs.fsu.edu
36019Shines@cs.fsu.edu# Copyright (c) 2006 The Regents of The University of Michigan
46019Shines@cs.fsu.edu# All rights reserved.
56019Shines@cs.fsu.edu#
66019Shines@cs.fsu.edu# Redistribution and use in source and binary forms, with or without
76019Shines@cs.fsu.edu# modification, are permitted provided that the following conditions are
86019Shines@cs.fsu.edu# met: redistributions of source code must retain the above copyright
96019Shines@cs.fsu.edu# notice, this list of conditions and the following disclaimer;
106019Shines@cs.fsu.edu# redistributions in binary form must reproduce the above copyright
116019Shines@cs.fsu.edu# notice, this list of conditions and the following disclaimer in the
126019Shines@cs.fsu.edu# documentation and/or other materials provided with the distribution;
136019Shines@cs.fsu.edu# neither the name of the copyright holders nor the names of its
146019Shines@cs.fsu.edu# contributors may be used to endorse or promote products derived from
156019Shines@cs.fsu.edu# this software without specific prior written permission.
166019Shines@cs.fsu.edu#
176019Shines@cs.fsu.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
186019Shines@cs.fsu.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
196019Shines@cs.fsu.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
206019Shines@cs.fsu.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
216019Shines@cs.fsu.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
226019Shines@cs.fsu.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
236019Shines@cs.fsu.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
246019Shines@cs.fsu.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
256019Shines@cs.fsu.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
266019Shines@cs.fsu.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
276019Shines@cs.fsu.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
286019Shines@cs.fsu.edu#
296019Shines@cs.fsu.edu# Authors: Steve Reinhardt
306019Shines@cs.fsu.edu
316019Shines@cs.fsu.eduImport('*')
326019Shines@cs.fsu.edu
336019Shines@cs.fsu.eduif env['TARGET_ISA'] == 'null':
346019Shines@cs.fsu.edu    SimObject('IntrControl.py')
356019Shines@cs.fsu.edu    Source('intr_control_noisa.cc')
366019Shines@cs.fsu.edu    Return()
376019Shines@cs.fsu.edu
386019Shines@cs.fsu.edu# Only build the protocol buffer instructions tracer if we have protobuf support
396019Shines@cs.fsu.eduif env['HAVE_PROTOBUF'] and env['TARGET_ISA'] != 'x86':
406019Shines@cs.fsu.edu    SimObject('InstPBTrace.py')
416019Shines@cs.fsu.edu    Source('inst_pb_trace.cc')
426019Shines@cs.fsu.edu
436019Shines@cs.fsu.eduSimObject('CheckerCPU.py')
446019Shines@cs.fsu.edu
456019Shines@cs.fsu.eduSimObject('BaseCPU.py')
466019Shines@cs.fsu.eduSimObject('CPUTracers.py')
476019Shines@cs.fsu.eduSimObject('FuncUnit.py')
486019Shines@cs.fsu.eduSimObject('IntrControl.py')
496019Shines@cs.fsu.eduSimObject('TimingExpr.py')
506019Shines@cs.fsu.edu
516019Shines@cs.fsu.eduSource('activity.cc')
526019Shines@cs.fsu.eduSource('base.cc')
536019Shines@cs.fsu.eduSource('cpuevent.cc')
546019Shines@cs.fsu.eduSource('exetrace.cc')
556019Shines@cs.fsu.eduSource('exec_context.cc')
566019Shines@cs.fsu.eduSource('func_unit.cc')
576019Shines@cs.fsu.eduSource('inteltrace.cc')
586019Shines@cs.fsu.eduSource('intr_control.cc')
596019Shines@cs.fsu.eduSource('nativetrace.cc')
606019Shines@cs.fsu.eduSource('pc_event.cc')
616019Shines@cs.fsu.eduSource('profile.cc')
62Source('quiesce_event.cc')
63Source('reg_class.cc')
64Source('static_inst.cc')
65Source('simple_thread.cc')
66Source('thread_context.cc')
67Source('thread_state.cc')
68Source('timing_expr.cc')
69
70SimObject('DummyChecker.py')
71SimObject('StaticInstFlags.py')
72Source('checker/cpu.cc')
73Source('dummy_checker.cc')
74DebugFlag('Checker')
75
76DebugFlag('Activity')
77DebugFlag('Commit')
78DebugFlag('Context')
79DebugFlag('Decode')
80DebugFlag('DynInst')
81DebugFlag('ExecEnable', 'Filter: Enable exec tracing (no tracing without this)')
82DebugFlag('ExecCPSeq', 'Format: Instruction sequence number')
83DebugFlag('ExecEffAddr', 'Format: Include effective address')
84DebugFlag('ExecFaulting', 'Trace faulting instructions')
85DebugFlag('ExecFetchSeq', 'Format: Fetch sequence number')
86DebugFlag('ExecOpClass', 'Format: Include operand class')
87DebugFlag('ExecRegDelta')
88DebugFlag('ExecResult', 'Format: Include results from execution')
89DebugFlag('ExecSymbol', 'Format: Try to include symbol names')
90DebugFlag('ExecThread', 'Format: Include thread ID in trace')
91DebugFlag('ExecTicks', 'Format: Include tick count')
92DebugFlag('ExecMicro', 'Filter: Include microops')
93DebugFlag('ExecMacro', 'Filter: Include macroops')
94DebugFlag('ExecUser', 'Filter: Trace user mode instructions')
95DebugFlag('ExecKernel', 'Filter: Trace kernel mode instructions')
96DebugFlag('ExecAsid', 'Format: Include ASID in trace')
97DebugFlag('ExecFlags', 'Format: Include instruction flags in trace')
98DebugFlag('Fetch')
99DebugFlag('IntrControl')
100DebugFlag('O3PipeView')
101DebugFlag('PCEvent')
102DebugFlag('Quiesce')
103DebugFlag('Mwait')
104
105CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
106    'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
107    'ExecResult', 'ExecSymbol', 'ExecThread',
108    'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
109    'ExecAsid', 'ExecFlags' ])
110CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
111    'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecMacro',
112    'ExecFaulting', 'ExecUser', 'ExecKernel' ])
113CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
114    'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecMacro', 'ExecFaulting',
115    'ExecUser', 'ExecKernel' ])
116